Patent application number | Description | Published |
20080303097 | Power FET With Low On-Resistance Using Merged Metal Layers - In one embodiment, relatively thin but wide metal bus strips overlying a high power FET are formed to conduct current to the source and drain narrow metal strips. A passivation layer is formed over the surface of the FET, and the passivation layer is etched to expose almost the entire top surface of the bus strips. A copper seed layer is then formed over the surface of the wafer, and a mask is formed to expose only the seed layer over the bus strips. The seed layer over the bus strips is then copper or gold electroplated to deposit a very thick metal layer, which effectively merges with the underlaying metal layer, to reduce on-resistance. The plating metal does not need to be passivated due to its thickness and wide line/space. Other techniques may also be used for depositing a thick metal over the exposed bus strips. | 12-11-2008 |
20090026578 | Vertical NPN Transistor Fabricated in a CMOS Process With Improved Electrical Characteristics - A vertical NPN bipolar transistor includes a P-type semiconductor structure, an N-well as the collector, a P-Base region in the N-well and an N-type region as the emitter. The transistor further includes P-type region formed in the P-Base region and underneath the field oxide layer where the P-type region has a doping concentration higher than the P-base region. The P-type region functions to inhibit the lateral parasitic bipolar action so that the transistor action is confined to the intrinsic base region vertically underneath the emitter. In one embodiment, the P-type region is a boron field doping region. The boron field doping region can be the same field doping region used to form channel stops for NMOS transistors in a CMOS fabrication process. | 01-29-2009 |
20090032850 | N-channel MOS Transistor Fabricated Using A Reduced Cost CMOS Process - An NMOS transistor includes a semiconductor substrate of a first conductivity type, first and second well regions of a second conductivity type formed spaced apart in the substrate, a conductive gate formed over the region between the spaced apart first and second well regions where the region of the substrate between the spaced apart first and second well regions forms the channel region, dielectric spacers formed on the sidewalls of the conductive gate, first and second heavily doped source and drain regions of the second conductivity type formed in the semiconductor substrate and being self-aligned to the edges of the dielectric spacers. The first and second well regions extend from the respective heavily doped regions through an area under the spacers to the third well region. The first and second well regions bridge the source and drain regions to the channel region of the transistor formed by the third well. | 02-05-2009 |
20090283843 | NMOS Transistor Including Extended NLDD-Drain For Improved Ruggedness - A MOS transistor includes a conductive gate insulated from a semiconductor layer by a first dielectric layer, lightly-doped source/drain regions being formed self-aligned to respective first and second edges of the conductive gate, a source region being formed self-aligned to a first spacer, a drain region being formed a first distance away from the edge of a second spacer, a source contact opening and source metallization formed above the source region, and a drain contact opening and drain metallization formed above the drain region. The lightly-doped source region remains under the first spacer while the lightly-doped drain region remains under the second spacer and extends over the first distance to the drain region. The distance between the first edge of the conductive gate to the source contact opening is the same as the distance between the second edge of the conductive gate to the drain contact opening. | 11-19-2009 |
20100032753 | MOS Transistor Including Extended NLDD Source-Drain Regions For Improved Ruggedness - A MOS transistor includes a conductive gate insulated from a semiconductor layer by a dielectric layer, first and second lightly-doped diffusion regions formed self-aligned to respective first and second edges of the conductive gate, a first diffusion region formed self-aligned to a first spacer, a second diffusion region formed a first distance away from the edge of a second spacer, a first contact opening and metallization formed above the first diffusion region, and a second contact opening and metallization formed above the second diffusion region. The first lightly-doped diffusion region remains under the first spacer. The second lightly-doped diffusion region remains under the second spacer and extends over the first distance to the second diffusion region. The distance between the first edge of the conductive gate to the first contact opening is the same as the distance between the second edge of the conductive gate to the second contact opening. | 02-11-2010 |
20100065906 | SYSTEM FOR VERTICAL DMOS WITH SLOTS - A device for providing a high power, low resistance, efficient vertical DMOS device is disclosed. The device comprises providing a semiconductor substrate with a source body structure thereon. The device further comprises a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted design, an oxide isolated process without any due extra steps other than the slots, lower capacitance, lower leakage, smaller die, improved heat transfer, improved electro-migration, lower ground resistance, less cross talk, drops the isolation diffusion and the sinker diffusion, mostly low temperature processing and provides double metal with single metal processing. Also disclosed is a method for integrating this vertical DMOS with CMOS, bipolar and BCD to provide an optimized small, efficient die using the buried power buss approach and these technologies. | 03-18-2010 |
20100230774 | Diode Having High Breakdown Voltage and Low on-Resistance - A Schottky or PN diode is formed where a first cathode portion is an N epitaxial layer that is relatively lightly doped. An N+ buried layer is formed beneath the cathode for conducting the cathode current to a cathode contact. A more highly doped N-well is formed, as a second cathode portion, in the epitaxial layer so that the complete cathode comprises the N-well surrounded by the more lightly doped first cathode portion. An anode covers the upper areas of the first and second cathode portions so both portions conduct current when the diode is forward biased. When the diode is reverse biased, the depletion region in the central N-well will be relatively shallow but substantially planar so will have a relatively high breakdown voltage. The weak link for breakdown voltage will be the curved edge of the deeper depletion region in the lightly doped first cathode portion under the outer edges of the anode. Therefore, the N-well lowers the on-resistance without lowering the breakdown voltage. | 09-16-2010 |
20110115017 | LDMOS transistor with asymmetric spacer as gate - The present invention provides a laterally diffused metal oxide semiconductor (LDMOS) transistor and a method for fabricating it. The LDMOS transistor includes an n-type epitaxial layer formed on a p-type substrate, and an asymmetric conductive spacer which acts as its gate. The LDMOS transistor also includes a source and a drain region on either side of the asymmetric conductive spacer, and a channel region formed by ion-implantation on the asymmetric conductive spacer. The height of the asymmetric conductive spacer increases from the source region to the drain region. The channel region is essentially completely under the asymmetric conductive spacer and has smaller length than that of the channel region of the prior art LDMOS transistors. The LDMOS transistor of the present invention also includes a field oxide layer surrounding the active region of the transistor, and a thin dielectric layer isolating the asymmetric conductive spacer from the n-type epitaxial layer. | 05-19-2011 |
20130316508 | LDMOS TRANSISTOR WITH ASYMMETRIC SPACER AS GATE - The present invention provides a laterally diffused metal oxide semiconductor (LDMOS) transistor and a method for fabricating it. The LDMOS transistor includes an n-type epitaxial layer formed on a p-type substrate, and an asymmetric conductive spacer which acts as its gate. The LDMOS transistor also includes a source and a drain region on either side of the asymmetric conductive spacer, and a channel region formed by ion-implantation on the asymmetric conductive spacer. The height of the asymmetric conductive spacer increases from the source region to the drain region. The channel region is essentially completely under the asymmetric conductive spacer and has smaller length than that of the channel region of the prior art LDMOS transistors. The LDMOS transistor of the present invention also includes a field oxide layer surrounding the active region of the transistor, and a thin dielectric layer isolating the asymmetric conductive spacer from the n-type epitaxial layer. | 11-28-2013 |