Patent application number | Description | Published |
20100062769 | Base Station Apparatus, Wireless Communication Terminal Apparatus, Communication Method and Computer Readable Medium Thereof - A base station used in a communication system including the base station for broadcasting service information to a wireless communication terminal, and the wireless communication terminal for receiving the service information during an idle state, the base station includes: a storing section for storing information of other base stations existing nearby the base station and service compliant information indicative of whether the other base stations are compliant with transmission of the service information. | 03-11-2010 |
20120094646 | BASE STATION AND METHOD OF CONTROLLING THE SAME - Provided is a base station capable of maintaining a communication quality of a communication terminal (mobile station) having registered its position with the base station itself, even if an operating frequency is changed. According to the present invention, the base station includes a transmission and reception unit | 04-19-2012 |
20120287892 | Communication System Radio Communication Terminal, and Radio Base Station - A wireless communication line is between a wireless base station and a wireless communication terminal, the base station includes a wireless base station transmission rate broadcast section that notifies the communication terminal of a transmission rate that enables support by the base station on the wireless communication line from the communication terminal to the base station, and the wireless communication terminal includes a storage section that stores a transmission rate required by the communication terminal on the communication line from the wireless communication terminal to the base station; a transmission rate comparison section that compares the transmission rate notified from the base station with the transmission rate stored in the storage section A transmission rate determination section determines a transmission rate on the communication line from the communication terminal to the base station based on a comparison result of the transmission rate comparison section. | 11-15-2012 |
Patent application number | Description | Published |
20090003081 | Non-volatile memory and method of manufacturing same - The number of process steps for manufacturing a non-volatile memory is reduced while the performance of the non-volatile memory is improved. The non-volatile memory has a memory cell in which first, second and third P-type diffusion regions are formed in an N-type well, a select gate is formed via a select-gate insulating film over a channel between the first and second P-type diffusion regions, and a floating gate is formed via a floating-gate insulating film over a channel between the second and third P-type diffusion regions. The non-volatile memory has a peripheral circuit in which fourth and fifth P-type diffusion regions are formed in an N-type well, and a peripheral-circuit gate is formed via a peripheral-circuit gate insulating film over a channel between the fourth and fifth P-type diffusion regions. The film thickness of the floating-gate insulating film is greater than that of the select-gate insulating film and peripheral-circuit gate insulating film. | 01-01-2009 |
20090184350 | Non-volatile semiconductor memory device - A non-volatile semiconductor memory device having a memory cell in which operating potentials are few and the scale of the peripheral circuitry is reduced includes a select transistor having a source/drain on both sides of a channel of a semiconductor substrate and having a gate electrode disposed on the channel via a thick gate insulating film; an element isolation region formed on the semiconductor substrate in an area adjacent to the select transistor; an antifuse adjacent to the element isolation region, having a lower electrode formed on the semiconductor substrate and having an upper electrode disposed on the semiconductor substrate in an area between the element isolation region and lower electrode via a thin gate insulating film; and a connection contact electrically connecting the source and upper electrode and contacting the source and the upper electrode. | 07-23-2009 |
20110108923 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device has a conventional NMOS transistor and an NMOS transistor functioning as an anti-fuse element and having an n type channel region. The conventional NMOS transistor is equipped with an n type extension region and a p type pocket region, while the anti-fuse element is not equipped with an extension region and a pocket region. This makes it possible to improve the performance of the transistor and at the same time improve the characteristics of the anti-fuse element after breakdown of its gate dielectric film. | 05-12-2011 |
20110122672 | Non-volatile semiconductor memory device - A non-volatile semiconductor memory device having a memory cell in which operating potentials are few and the scale of the peripheral circuitry is reduced includes a select transistor having a source/drain on both sides of a channel of a semiconductor substrate and having a gate electrode disposed on the channel via a thick gate insulating film; an element isolation region formed on the semiconductor substrate in an area adjacent to the select transistor; an antifuse adjacent to the element isolation region, having a lower electrode formed on the semiconductor substrate and having an upper electrode disposed on the semiconductor substrate in an area between the element isolation region and lower electrode via a thin gate insulating film; and a connection contact electrically connecting the source and upper electrode and contacting the source and the upper electrode. | 05-26-2011 |
20120026810 | SEMICONDUCTOR MEMORY DEVICE AND ANTIFUSE PROGRAMMING METHOD - An antifuse comprised of an NMOS transistor or an NMOS capacitor includes a first terminal coupled to a gate electrode, a second terminal coupled to a diffusion layer, and a gate insulating film interposed between the gate electrode and the diffusion layer. A programming circuit includes a first programming circuit which has first current drive capability and which performs first programming operation and a second programming circuit which has second current drive capability larger than the first current drive capability and which performs second programming operation to follow the first programming operation. In the first programming operation, the first programming circuit breaks down the gate insulating film by applying a first programming voltage between the first terminal and the second terminal. In the second programming operation, the second programming circuit applies a second programming voltage lower than the first programming voltage between the first terminal and the second terminal. | 02-02-2012 |
20120044741 | Semiconductor device having memory unit, method of writing to or reading from memory unit, and semiconductor device manufacturing method - A first semiconductor device is formed over a substrate and includes a first insulation film, a first electrode, and a first diffusion layer. A second semiconductor device is formed over a substrate and includes a second insulation film, a second electrode, and a second diffusion layer. The second electrode is coupled to the first electrode. A control transistor allows one of a source and a drain to be coupled to the first electrode and the second electrode, allows the other one of the source and the drain to be coupled to a bit line, and allows a gate electrode to be coupled to a word line. A first potential control line is coupled to the first diffusion layer and controls a potential of the first diffusion layer. A second potential control line is coupled to the second diffusion layer and controls a potential of the second diffusion layer. | 02-23-2012 |
20120080736 | SEMICONDUCTOR DEVICE - An antifuse whose internal written information cannot be analyzed even by utilizing methods to determine whether there is a charge-up in the electrodes. The antifuse includes a gate insulation film, a gate electrode, and a first diffusion layer. A second diffusion layer is isolated from the first diffusion layer by way of a device isolator film, and is the same conduction type as the first diffusion layer. The gate wiring is formed as one integrated piece with the gate electrode, and extends over the device isolator film. A common contact couples the gate wiring to the second diffusion layer. The gate electrode is comprised of semiconductor material such as polysilicon that is doped with impurities of the same conduction type as the first diffusion layer. The second diffusion layer is coupled only to the common contact. | 04-05-2012 |
20130033921 | SEMICONDUCTOR DEVICE - A semiconductor device using resistive random access memory (ReRAM) elements and having improved tamper resistance is provided. The semiconductor device is provided with a unit cell which stores one bit of cell data and a control circuit. The unit cell includes n ReRAM elements (n being an integer of 2 or larger). At least one of the ReRAM elements is an effective element where the cell data is recorded. In reading the cell data, the control circuit at least selects the effective element and reads data recorded thereon as the cell data. | 02-07-2013 |
20130058150 | OTP MEMORY - The present invention provides an OTP memory having higher confidentiality. A memory cell has a memory transistor forming a current path between first and second nodes, a selection transistor forming a current path between third and fourth nodes, the third node being coupled to the gate of the memory transistor via a line, and a capacitor coupled to the first node. By applying high voltage which does not break but deteriorates a gate oxide film and increases gate leak current to a memory transistor, data is written. Data can be read by the presence/absence of leak of charges accumulated in the capacitor. Since the position of deterioration in the gate oxide film cannot be discriminated by a physical analysis, confidentiality is high. | 03-07-2013 |
20150311216 | OTP MEMORY - The present invention provides an OTP memory having higher confidentiality. A memory cell has a memory transistor forming a current path between first and second nodes, a selection transistor forming a current path between third and fourth nodes, the third node being coupled to the gate of the memory transistor via a line, and a capacitor coupled to the first node. By applying high voltage which does not break but deteriorates a gate oxide film and increases gate leak current to a memory transistor, data is written. Data can be read by the presence/absence of leak of charges accumulated in the capacitor. Since the position of deterioration in the gate oxide film cannot be discriminated by a physical analysis, confidentiality is high. | 10-29-2015 |
Patent application number | Description | Published |
20100015449 | COMPOSITION FOR FORMING GAS-BARRIER MATERIAL, GAS-BARRIER MATERIAL, A METHOD OF PRODUCING THE SAME, AND GAS-BARRIER PACKING MATERIAL - A composition for forming a gas-barrier material, comprising a polycarboxylic acid-type polymer (A) and at least a bifunctional alicyclic epoxy compound (B). The composition for forming a gas-barrier material features excellent gas-barrier property, retort resistance and flexibility, can be cured at a low temperature in a short period of time without affecting the plastic base material, and contributes to improving the productivity. | 01-21-2010 |
20110091743 | METHOD OF PRODUCING GAS-BARRIER LAMINATED MEMBER - A method of producing a gas-barrier laminated member having a gas-barrier layer formed by crosslinking the carboxyl groups of a polycarboxylic acid polymer with multivalent metal ions. The method comprises forming a layer (A) containing an alkaline compound of a multivalent metal on at least one surface of a plastic base material, applying a solution (b) obtained by dissolving a polycarboxylic acid polymer in a solvent containing at least water onto the layer (A) that contains the alkaline compound of the multivalent metal, and removing the solvent by a heat treatment so that a metal-ionically crosslinked structure is formed with the multivalent metal ions among the carboxyl groups in the solution (b). The gas-barrier laminated member has excellent adhesion to the base material, gas-barrier property, retort resistance and flexibility, and is efficiently produced by only being heated at a low temperature for a short period of time through a decreased number of simplified steps. | 04-21-2011 |
20120238696 | COATING COMPOSITION FOR UNDERCOATING - To provide a coating composition for undercoating which, in forming a gas-barrier layer having a crosslinked structure between a polycarboxylic acid type polymer and polyvalent metal ions by the heating at a low temperature for a short period of time, permits polyvalent metal ions to be easily and quickly fed into the polycarboxylic acid type polymer and, besides, into the whole gas-barrier layer. A coating composition containing, as chief components, a nonaqueous polyester polyol, an isocyanate compound, and an alkaline compound of a polyvalent metal that serves as an ion source for forming the crosslinked structure, wherein the nonaqueous polyester polyol contains a nonaqueous polyester polyol which contains a metal element in the resin skeleton thereof as an essential component, and the alkaline compound of the polyvalent metal has an average primary particle size in a range of 0.005 to 0.5 μm. | 09-20-2012 |