Koji Arita
Koji Arita, Osaka JP
Patent application number | Description | Published |
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20100061142 | MEMORY ELEMENT AND MEMORY APPARATUS - Memory elements ( | 03-11-2010 |
20100090193 | NONVOLATILE MEMORY ELEMENT ARRAY AND MANUFACTURING METHOD THEREOF - A lower electrode ( | 04-15-2010 |
20100190313 | METHOD FOR MANUFACTURING NONVOLATILE STORAGE ELEMENT AND METHOD FOR MANUFACTURING NONVOLATILE STORAGE DEVICE - A method for manufacturing a nonvolatile storage element that minimizes shape shift between an upper electrode and a lower electrode, and which includes: depositing, in sequence, a connecting electrode layer which is conductive, a lower electrode layer and a variable resistance layer which are made of a non-noble metal nitride and are conductive, an upper electrode layer made of noble metal, and a mask layer; forming the mask layer, into a predetermined shape; forming the upper electrode layer, the variable resistance layer, and the lower electrode layer into the predetermined shape by etching using the mask layer as a mask; and removing, simultaneously, the mask and a region of the connecting electrode layer that has been exposed by the etching. | 07-29-2010 |
20100193760 | CURRENT RESTRICTING ELEMENT, MEMORY APPARATUS INCORPORATING CURRENT RESTRICTING ELEMENT, AND FABRICATION METHOD THEREOF - In a current rectifying element ( | 08-05-2010 |
20100308298 | NONVOLATILE MEMORY ELEMENT AND NONVOLATILE MEMORY DEVICE INCORPORATING NONVOLATILE MEMORY ELEMENT - A nonvolatile memory element includes a first electrode ( | 12-09-2010 |
20110002155 | CURRENT CONTROL ELEMENT, MEMORY ELEMENT, AND FABRICATION METHOD THEREOF - A memory element ( | 01-06-2011 |
20110103133 | MEMORY CELL ARRAY, NONVOLATILE STORAGE DEVICE, MEMORY CELL, AND METHOD OF MANUFACTURING MEMORY CELL ARRAY - A method of manufacturing a memory cell array in which first conductive layers ( | 05-05-2011 |
20110114912 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device ( | 05-19-2011 |
20110164447 | CURRENT STEERING ELEMENT, STORAGE ELEMENT, STORAGE DEVICE, AND METHOD FOR MANUFACTURING CURRENT STEERING ELEMENT - A current steering element which can prevent occurrence of write disturb even when electric pulses having different polarities are applied and can cause large current to flow through a variable resistance element, and with which data can be written without problem. In a storage element ( | 07-07-2011 |
20110220862 | RESISTANCE VARIABLE ELEMENT AND RESISTANCE VARIABLE MEMORY DEVICE - A resistance variable element ( | 09-15-2011 |
20110284816 | NONVOLATILE MEMORY ELEMENT, NONVOLATILE MEMORY DEVICE, NONVOLATILE SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING NONVOLATILE MEMORY ELEMENT - A nonvolatile memory element comprises a first electrode ( | 11-24-2011 |
20120069632 | CURRENT CONTROL, MEMORY ELEMENT, MEMORY DEVICE, AND PRODUCTION METHOD FOR CURRENT CONTROL ELEMENT - Provided is a current steering element that can prevent write didturb even when an electrical pulse with different polarities is applied and that can cause a large current to flow through a variable resistance element. The current steering element includes a first electrode ( | 03-22-2012 |
20120256156 | MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a memory device provided with a plurality of memory cells and a lead-out line ( | 10-11-2012 |
20130171799 | CURRENT STEERING ELEMENT AND NON-VOLATILE MEMORY ELEMENT INCORPORATING CURRENT STEERING ELEMENT - A current steering element ( | 07-04-2013 |
Koji Arita, Sagamihara-Shi JP
Patent application number | Description | Published |
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20090236747 | Semiconductor device and method for fabricating the same - A multilevel interconnect structure in a semiconductor device comprises a first insulating layer ( | 09-24-2009 |
Koji Arita, Kanagawa JP
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20080283404 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE TO DECREASE DEFECT NUMBER OF PLATING FILM - A method for manufacturing a semiconductor device is provided which includes performing an electroplating step to fill concavities formed on a substrate. The electroplating step further includes: performing a first electroplating step; performing a first reverse bias step; performing a second electroplating step; performing a second reverse bias step; and a third electroplating step. The polarity of the first and the second reverse bias steps is different from that of the first electroplating step. A difference between the third current density and the fourth current density is larger than a difference between the first current density and the second current density. | 11-20-2008 |
Koji Arita, Kawasaki JP
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20080203572 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - The present invention provides a semiconductor device having interconnects, reduced in leakage current between the interconnects and improved in the TDDB characteristic, which comprises an insulating interlayer | 08-28-2008 |
Koji Arita, Toyama JP
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20130224930 | METHOD FOR MANUFACTURING VARIABLE RESISTANCE ELEMENT - A variable resistance element manufacturing method includes: forming a conductive plug in an interlayer insulating film on a substrate; planarizing an upper surface of the insulating film such that an upper part of the conductive plug protrudes from an upper surface of the insulating film by removing (i) a depression in the insulating film formed around the conductive plug and (ii) a depression in the insulating film formed across a plurality of conductive plugs; forming, on the insulating film and the plug, a lower electrode layer electrically connected to the plug; planarizing an upper surface of the lower electrode layer to remove a protruding part on the upper surface of the lower electrode layer; forming, on the lower electrode layer, a variable resistance layer; forming an upper electrode layer on the variable resistance layer; and forming a lower electrode, the variable resistance layer, and an upper electrode layer. | 08-29-2013 |
Koji Arita, Sagamihara JP
Patent application number | Description | Published |
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20130089979 | SEMICONDUCTOR DEVICE HAVING A MULTILEVEL INTERCONNECT STRUCTURE AND METHOD FOR FABRICATING THE SAME - A multilevel interconnect structure in a semiconductor device and methods for fabricating the same are described. The multilevel interconnect structure in the semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere. | 04-11-2013 |