Patent application number | Description | Published |
20100060310 | Systems and Methods Utilizing Redundancy in Semiconductor Chip Interconnects - An integrated circuit, or combination of integrated circuits, has a primary interconnect, a redundant interconnect, and circuitry connecting the primary and redundant interconnects allowing selection of the redundant interconnect to bypass the primary interconnect. | 03-11-2010 |
20100141286 | INTEGRATED CIRCUIT WITH IMPROVED TEST CAPABILITY VIA REDUCED PIN COUNT - An integrated circuit that supports testing of multiple pads via a subset of these pads includes at least two sections. Each section has multiple pads and multiple test access circuits coupled to these pads. For each section, one pad is designated as a primary pad and the remaining pads are designated as secondary pads. For each section, the test access circuits couple the secondary pads to the primary pad such that all of the pads in the section can be tested by probing just the primary pad. Each test access circuit may be implemented with a simple switch. A controller generates a set of control signals for the test access circuits in all sections. These control signals enable and disable the test access circuits such that all of the sections can be tested in parallel, and the pads in each section can be tested in a sequential order. | 06-10-2010 |
20110164808 | TECHNIQUES PROVIDING FIDUCIAL MARKERS FOR FAILURE ANALYSIS - A semiconductor die includes a group of spacer cells within the semiconductor die. The spacer cells include fiducial markings therein. The fiducial markings can be located within a metal layer, a diffusion layer, a polysilicon layer, and/or a Shallow Trench Isolation (STI) structure. | 07-07-2011 |
20130297981 | LOW COST HIGH THROUGHPUT TSV/MICROBUMP PROBE - A first apparatus, such as a die or a semiconductor package, has signal paths extending through the apparatus. The signal paths can include through vias and other components. The signal paths are operable to communicate with a second apparatus when the second apparatus is stacked with the first apparatus. The first apparatus also has pass gates. Each pass gate is configurable in response to a signal, to short a pair of the signal paths to enable substantially simultaneous testing of the signal paths. The pass gates may be configurable to isolate the signal paths during operation of the first apparatus. | 11-07-2013 |
Patent application number | Description | Published |
20090206868 | METHODOLOGIES AND TOOL SET FOR IDDQ VERIFICATION, DEBUGGING AND FAILURE DIAGNOSIS - Quiescent supply current (I | 08-20-2009 |
20110231720 | DATA RECIRCULATION IN CONFIGURED SCAN PATHS - An Automated Test Equipment (ATE) system is configured to test a Device Under Test (DUT). The ATE system stores a Procedure Description Language program. The ATE system interprets the program, thereby causing a configured scan path to be set up in the DUT and causing bit values to be loaded into that scan path. During testing, it is sometimes desirable to change only bit values in certain scan path bit locations. In a data recirculation operation, the ATE system shifts bit values, on a bit-by-bit basis, out of the configured scan path via the TDO terminal of the DUT and shifts back in either the shifted out bit value or a replacement bit value. The shift back into the configured scan path occurs via the TDI terminal of the DUT so that each bit value in the scan path is replaced with its previous value or a replacement value. | 09-22-2011 |
20110270548 | AUTOMATED VERIFICATION AND ESTIMATION OF QUIESCENT POWER SUPPLY CURRENT - Procedures are disclosed to automate constraint and power mode (PM) setup determination for quiescent power supply current (I | 11-03-2011 |
20110307748 | TECHNIQUES FOR ERROR DIAGNOSIS IN VLSI SYSTEMS - Techniques for designing and storing test input and output data vectors to diagnose bit errors in a testing sequence. In an aspect, test input vectors may be chosen such that the corresponding correct output vectors form codewords of a forward error-correcting code. In another aspect, the correct test output vectors may be compressed to reduce the memory requirements of the testing system. In yet another aspect, test input vectors may be sorted such that the test output vectors are monotonically increasing or decreasing in sequence, and corresponding delta's between output vectors in the sequence may be stored to reduce the memory requirements. Further aspects provide for storing information relating to the correct output vectors in various efficient formats, including storing base value-referenced offsets, and storing relative operations and output vector segments to allow derivation of correct output vectors from memory when required. | 12-15-2011 |
20120110531 | DEFECT AND YIELD PREDICTION FOR SEGMENTS OF AN INTEGRATED CIRCUIT - Defect prediction information is determined for a segment of an integrated circuit layout. Marker information is obtained, for example from user input into a computer design tool, where the marker information defines the segment. A segment can be defined to be any arbitrary portion of the layout and can include portions of multiple blocks. The marker information is used to extract layout information corresponding to the segment. The extracted segment layout information is analyzed to determine the defect prediction information. In one example, the determination involves performing a Critical Area Analysis such that the defect prediction information is a yield prediction value. This process is repeated for multiple segments, and the defect prediction information for the segments is compared to identify the segment most susceptible to defects. The user can modify the design of the segment, and repeat the process to improve yield in the manufacture of the integrated circuit. | 05-03-2012 |
20120324302 | INTEGRATED CIRCUIT FOR TESTING USING A HIGH-SPEED INPUT/OUTPUT INTERFACE - An integrated circuit configured for testing is described. The integrated circuit includes a high-speed input/output interface. The integrated circuit also includes a test controller coupled to the high-speed input/output interface. The integrated circuit further includes test circuitry coupled to the test controller. The test controller controls the test circuitry based on controller protocol test information from the high-speed input/output interface. | 12-20-2012 |
20140264331 | DAISY CHAIN CONNECTION FOR TESTING CONTINUITY IN A SEMICONDUCTOR DIE - An integrated circuit product package configured to continuity testing is described. The integrated circuit product package includes a package substrate. The package substrate includes internal routing connections. The integrated circuit product package also includes a semiconductor die coupled to the package substrate. The semiconductor die includes input/output (I/O) pins and switches. The switches selectively coupled the I/O pins to facilitate a daisy chain connection. The daisy chain connection includes circuitry fabricated on the semiconductor die, more than two of the internal routing connections, more than two of the I/O pins and at least one switch. | 09-18-2014 |