Patent application number | Description | Published |
20100059476 | METHOD FOR MANUFACTURING A MAGNETIC STORAGE MEDIUM - A method for manufacturing a magnetic storage medium that improves the flatness of the magnetic storage medium. A storage layer is formed on a substrate. Next, a resist mask is formed above the storage layer. Then, a pit is formed in the storage layer using the resist mask. Afterwards, a non-magnetic layer having a thickness that is in accordance with the depth of the pit is formed in the pit and above the resist mask. Subsequently, the resist mask and the non-magnetic layer formed above the resist mask are removed from the storage layer. | 03-11-2010 |
20100187197 | METHOD FOR MANUFACTURING A VERTICAL MAGNETIC RECORDING MEDIUM - A method for manufacturing a vertical magnetic recording medium that has: a substrate; a soft magnetic layer formed on the substrate; a magnetic recording layer formed directly on the soft magnetic layer or formed on the soft magnetic layer with an intermediate layer therebetween, and having an axis of easy magnetization perpendicular to a surface thereof, in which a plurality of grooves dividing the magnetic recording layer into a plurality of recording elements, the method including a step of forming the grooves by reactive ion etching using a gas containing at least halogen and oxygen, and using the hard mask layer as a mask. | 07-29-2010 |
20100308012 | MAGNETIC DEVICE MANUFACTURING METHOD - A method for manufacturing a magnetic device that obtains sufficient processing accuracy without increasing mask removal steps. A first mask layer is formed above a magnetic layer using one selected from the group consisting of Ti, Ta, W, and an oxide or a nitride thereof. A second mask layer is formed on the first mask layer using Ru or Cr. A resist pattern is formed on the second mask layer. A second mask pattern is formed by performing reactive ion etching with reactive gas containing oxygen on the second mask layer using the resist pattern. A first mask pattern is formed by performing reactive ion etching with reactive gas containing halogen gas on the first mask layer using the second mask pattern. A magnetic pattern is formed by performing reactive ion etching with reactive gas containing oxygen on the magnetic layer using the first mask pattern. | 12-09-2010 |
Patent application number | Description | Published |
20090097514 | FEMTOSECOND LASER PROCESSING SYSTEM WITH PROCESS PARAMETERS, CONTROLS AND FEEDBACK - A femtosecond laser based laser processing system having a femtosecond laser, frequency conversion optics, beam manipulation optics, target motion control, processing chamber, diagnostic systems and system control modules. The femtosecond laser based laser processing system allows for the utilization of the unique heat control in micromachining, and the system has greater output beam stability, continuously variable repetition rate and unique temporal beam shaping capabilities. | 04-16-2009 |
20110139760 | FEMTOSECOND LASER PROCESSING SYSTEM WITH PROCESS PARAMETERS CONTROLS AND FEEDBACK - A femtosecond laser based laser processing system having a femtosecond laser, frequency conversion optics, beam manipulation optics, target motion control, processing chamber, diagnostic systems and system control modules. The femtosecond laser based laser processing system allows for the utilization of the unique heat control in micromachining, and the system has greater output beam stability, continuously variable repetition rate and unique temporal beam shaping capabilities. | 06-16-2011 |
20130003065 | FEMTOSECOND LASER PROCESSING SYSTEM WITH PROCESS PARAMETERS CONTROLS AND FEEDBACK - A femtosecond laser based laser processing system having a femtosecond laser, frequency conversion optics, beam manipulation optics, target motion control, processing chamber, diagnostic systems and system control modules. The femtosecond laser based laser processing system allows for the utilization of the unique heat control in micromachining, and the system has greater output beam stability, continuously variable repetition rate and unique temporal beam shaping capabilities. | 01-03-2013 |
20140092927 | FEMTOSECOND LASER PROCESSING SYSTEM WITH PROCESS PARAMETERS CONTROLS AND FEEDBACK - A femtosecond laser based laser processing system having a femtosecond laser, frequency conversion optics, beam manipulation optics, target motion control, processing chamber, diagnostic systems and system control modules. The femtosecond laser based laser processing system allows for the utilization of the unique heat control in micromachining, and the system has greater output beam stability, continuously variable repetition rate and unique temporal beam shaping capabilities. | 04-03-2014 |
Patent application number | Description | Published |
20090049455 | COMMAND INTERFACE SYSTEMS AND METHODS - Apparatus, systems, and methods are disclosed that operate within a memory to execute internal commands, to suspend the execution of commands during a transfer period, and to execute external commands following the transfer period. Additional apparatus, systems, and methods are disclosed. | 02-19-2009 |
20110302328 | COMMAND INTERFACE SYSTEMS AND METHODS - Apparatus, systems, and methods are disclosed that operate within a memory to execute internal commands, to suspend the execution of commands during a transfer period, and to execute external commands following the transfer period. Additional apparatus, systems, and methods are disclosed. | 12-08-2011 |
20120327728 | METHOD AND APPARATUS FOR MEMORY COMMAND INPUT AND CONTROL - Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. The memory further may include chip enable circuits having control logic configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories. | 12-27-2012 |
20140052878 | COMMAND INTERFACE SYSTEMS AND METHODS - Apparatus, systems, and methods are disclosed that operate within a memory to execute internal commands, to suspend the execution of commands during a transfer period, and to execute external commands following the transfer period. Additional apparatus, systems, and methods are disclosed. | 02-20-2014 |
20140205056 | IDENTIFYING STACKED DICE - Various embodiments comprise apparatuses to assign unique device identifier values to addressable devices in a stacked package. In one embodiment, an apparatus is disclosed including a stacked package with at least two addressable devices. Each of the addressable devices includes data input and switch path circuitry, a shift register coupled to the data input and switch path circuitry, and a single through-substrate via (TSV) through which the unique device identifier values can be assigned. The single TSV is coupled to the data input and switch path circuitry and between adjacent ones of the at least two addressable devices. Additional apparatuses, systems, and methods are described. | 07-24-2014 |
20150085968 | IDENTIFYING STACKED DICE - Various embodiments comprise apparatuses to assign unique device identifier values to addressable devices in a stacked package. In one embodiment, an apparatus is disclosed including a stacked package with at least two addressable devices. Each of the addressable devices includes data input and switch path circuitry, a shift register coupled to the data input and switch path circuitry, and a single through-substrate via (TSV) through which the unique device identifier values can be assigned. The single TSV is coupled to the data input and switch path circuitry and between adjacent ones of the at least two addressable devices. Additional apparatuses, systems, and methods are described. | 03-26-2015 |