Patent application number | Description | Published |
20120307960 | X-RAY COMPUTED TOMOGRAPHIC IMAGING APPARATUS AND METHOD FOR SAME - Disclosed are an X-ray computed tomographic imaging apparatus and a method for same. The X-ray computed tomographic imaging apparatus of the present invention comprises: a tomograph which radiates light onto an object being imaged by tomography, and detects the light passing through the object being imaged by tomography; a magnification rate determining unit which determines the magnification rate of an image of the object being imaged by tomography using the hardware property of the tomograph and/or the size of an input voxel; and a magnification rate controller which moves the tomography in accordance with the determined magnification rate, thereby obtaining images having a high resolution. | 12-06-2012 |
20150117743 | APPARATUS AND METHOD FOR RECONSTRUCTING PANORAMIC X-RAY IMAGE - The present invention provides an apparatus and method for reconstructing a panoramic X-ray image. The apparatus includes a storage unit for storing image data of multiple image layers; an image processing unit for determining a reference image layer among the multiple image layers, finding blocks that correspond to at least one block designated in the reference image layer from other image layers, selecting a clearest block by comparing image data of the corresponding blocks, and reconstructing the reference image layer by replacing the designated block in the reference image layer with the clearest block selected in any of the other image layers, if the selected block is not the same as the designated block in the reference image layer; and a display unit for displaying a panoramic image of the reconstructed reference image layer. | 04-30-2015 |
20150139524 | METHOD AND APPARATUS FOR PROVIDING PANORAMA IMAGE DATA - A method and an apparatus for providing panoramic image data by reconstructing frame images captured by a panoramic imaging apparatus, are disclosed. In reconstruction of images with multiple image layers, sizes of images reconstructed with an image layer or images to be used for a reconstruction are scaled. An image is selected by analyzing sharpness. A panoramic image is provided by combining selected image. According to the present invention, parts having unclear focal planes may be completely removed in a panoramic image and it is possible to provide an image including only with focused regions. | 05-21-2015 |
20150238153 | X-RAY IMAGING DEVICE - The purpose of the present invention is to provide an X-ray imaging device capable of obtaining more diversified X-ray image information. To this end, the present invention comprises: an X-ray generation device for generating an X-ray; an X-ray detection device for detecting the X-ray which is generated in the X-ray generation device and penetrates the subject; and a collimator arranged between the X-ray generation device and the X-ray detection device, wherein the X-ray detection device and/or the collimator provides an X-ray imaging device configured to rotate relative to the X-ray generation device. Thus, since it is possible to adjust an X-ray detection area if necessary, the visual field of the imaging device can be adjusted such that diversified X-ray image information can be obtained. | 08-27-2015 |
Patent application number | Description | Published |
20120222952 | PLASMA IMMERSION ION MILLING APPARATUS AND METHOD - Disclosed is an apparatus and method for low-temperature plasma immersion processing of a variety of workpieces using accelerated ions, wherein low-temperature plasma is distributed around a cylindrical workpiece placed in a chamber, the workpiece is enclosed with a housing including a multi-slot extracting electrode to isolate the workpiece from plasma, and a negative potential sufficient to induce sputtering is applied to the workpiece and the electrode, so that ions from plasma are accelerated within the sheath formed between the extracting electrode and plasma, pass through the slot part of the electrode and bombard the workpiece, thus polishing the surface of the workpiece. This apparatus and method is effective for surface smoothing to ones of nm of large cylindrical substrates particularly substrates for micro or nanopattern transfer. This method includes plasma cleaning, surface activating, surface smoothing, dry etching, deposition, plasma immersion ion implantation and deposition within a single or multi chamber. | 09-06-2012 |
20130120732 | CYLINDRICAL MAGNETIC LEVITATION STAGE AND LITHOGRAPHY - The present invention provides a cylindrical magnetic levitation stage and an exposure apparatus, which can form a nanoscale pattern of a large area directly on the surface of a large cylinder. The present invention provides an exposure apparatus including a new type of cylindrical magnetic levitation stage, which can levitate, rotate, and move a cylinder in the axial direction by the principle of magnetic levitation in a non-contact manner and form a nanoscale pattern on the surface of the cylinder, and a light source for irradiating light on the surface of the cylinder, thereby reducing the position error of the cylindrical magnetic levitation stage to a nanoscale size and correcting the error caused by mechanical processing in real time. Moreover, the present invention provides an exposure apparatus, which includes a differential vacuum means combined with the cylindrical magnetic levitation stage to create a partial vacuum environment between the light source and the surface of the cylinder, and thus it is possible to employ light sources such as X-rays, electron beams, extreme ultraviolet (EUV) rays, etc. | 05-16-2013 |
Patent application number | Description | Published |
20100023327 | METHOD FOR IMPROVING SPEECH SIGNAL NON-LINEAR OVERWEIGHTING GAIN IN WAVELET PACKET TRANSFORM DOMAIN - The present invention relates to speech enhancement accomplished by applying an overweighting gain of a nonlinear structure in a wavelet packet transform domain or a Fourier transform domain. The present invention relates to a method for improving quality of speech signals, which can be applied in a variety of noise-level conditions using noise estimation of the least-square line method and a modified spectral subtraction method having a nonlinear overweighting gain for each sub-band. According to the method for improving quality of speech of the present invention, it is effective in that quality of speech can be further effectively improved in a variety of noise-level conditions. Particularly, according to the present invention, generation of musical tones can be efficiently suppressed, and intelligibility of speech is reliably guaranteed in the improved speech. | 01-28-2010 |
20110022383 | METHOD FOR PROCESSING NOISY SPEECH SIGNAL, APPARATUS FOR SAME AND COMPUTER-READABLE RECORDING MEDIUM - A sound quality improvement method for a noisy speech signal according to an embodiment of the present invention comprises the steps of estimating a noise signal of an input noisy speech signal by performing a predetermined noise estimation procedure for the noisy speech signal; measuring a relative magnitude difference to represent a relative difference between the noisy speech signal and the estimated noise signal; calculating a modified overweighting gain function with a non-linear structure in which a relatively high gain is allocated to a low-frequency band than a high-frequency band by using the relative magnitude difference; and obtaining an enhanced speech signal by multiplying the noisy speech signal and a time-varying gain function obtained by using the overweighting gain function. Accordingly, the amount of calculation for noise estimation is small, and large-capacity memory is not required. Furthermore, the present invention can be easily implemented in hardware or software, and the accuracy of noise estimation can be increase because an adaptive procedure can be performed on each frequency sub-band. | 01-27-2011 |
20110029305 | METHOD FOR PROCESSING NOISY SPEECH SIGNAL, APPARATUS FOR SAME AND COMPUTER-READABLE RECORDING MEDIUM - A noise estimation method for a noisy speech signal according to an embodiment of the present invention includes the steps of approximating a transformation spectrum by transforming an input noisy speech signal to a frequency domain, calculating a smoothed magnitude spectrum having a decreased difference in a magnitude of the transformation spectrum between neighboring frames, calculating a search spectrum to represent an estimated noise component of the smoothed magnitude spectrum, and estimating a noise spectrum by using a recursive average method using an adaptive forgetting factor defined by using the search spectrum. According to an embodiment of the present invention, the amount of calculation for noise estimation is small, and large-capacity memory is not required. Accordingly, the present invention can be easily implemented in hardware or software. Further, the accuracy of noise estimation can be increase because an adaptive procedure can be performed on each frequency sub-band. | 02-03-2011 |
20110029310 | PROCEDURE FOR PROCESSING NOISY SPEECH SIGNALS, AND APPARATUS AND COMPUTER PROGRAM THEREFOR - Provided are a noise state determination method and an apparatus and a computer readable recording medium therefor. A noisy speech signal processing method according to the present invention includes calculating a transformed spectrum by transforming an input noisy speech signal to a frequency domain; calculating a smoothed magnitude spectrum by reducing magnitude differences of the transformed spectrum between neighboring frames; calculating a search spectrum which represents an estimated noise component of the smoothed magnitude spectrum; and calculating an identification ratio which represents a ratio of a noise component included in the input noisy speech signal, by using the smoothed magnitude spectrum and the search spectrum. Since a small amount of calculation is required and a large-capacity memory is not required, the present invention may be easily implemented as hardware or software. Also, since an adaptive operation is performed with respect to each frequency sub-band, the accuracy of determining a noise state may be improved. | 02-03-2011 |
Patent application number | Description | Published |
20100134372 | THZ-BAND FOLDED DIPOLE ANTENNA HAVING HIGH INPUT IMPEDANCE - Provided is a folded dipole antenna including a meander line formed on a photoconductive substrate, characterized by an input impedance of several kΩ, which is much higher than that of a conventional dipole antenna, due to optimization of a horizontal length, a line interval, a width, and a line number of the meander line. Accordingly, use of the folded dipole antenna greatly improves an impedance matching characteristic between the antenna and a photomixer having an output impedance of 10 kΩ or more, and accordingly an output of a THz continuous wave. | 06-03-2010 |
20150380996 | MOTOR AND ITS ROTOR - A motor that minimizes demagnetization to improve a force resistant to the demagnetization without increasing a thickness of each permanent magnet and a distance between each permanent magnet and a stator includes a rotor that rotates in one direction and includes cavities configured to hold magnets, flux barriers configured to communicate with first ends of the cavities and formed adjacent to an outer circumferential surface of the rotor, and ribs formed between the outer circumferential surface of the rotor and the flux barriers. Each of the ribs is configured such that a width of one end thereof at an upstream side in a rotational direction of the rotor is wider than that of the other thereof at a downstream side in the rotational direction. | 12-31-2015 |
20160112285 | APPARATUS AND METHOD FOR DETECTING ABNORMAL CONNECTION - Disclosed are an apparatus and method for detecting an abnormal connection. The apparatus for detecting an abnormal connection includes a log pattern identifier configured to identify a plurality of connection patterns each indicating connection stages from log data regarding a system connection; and a log analyzer configured to perform at least one of a first log analysis for detecting an abnormal connection stage pair indicated by a specific connection pattern among the plurality of connection patterns and a second log analysis for detecting an abnormal connection pattern indicating a specific connection stage pair among the plurality of connection patterns. | 04-21-2016 |
20160112500 | GLOBAL SERVER LOAD BALANCER APPARATUS AND METHOD FOR DYNAMICALLY CONTROLLING TIME-TO-LIVE - Disclosed are a global server load balancer (GSLB) apparatus and a method for dynamically controlling cache time-to-live (TTL) in the GSLB apparatus. The GSLB apparatus which performs load balancing among a plurality of local servers includes a domain name system (DNS) query processor that receives a query message from a DNS server, a server selector that selects a local server among the plurality of local servers based on the received query message, a load calculator that collects state information of the GSLB apparatus, and calculates a load of the GSLB apparatus from the collected state information, and a TTL controller that updates a TTL of the GSLB apparatus based on the calculated load. | 04-21-2016 |
20160117457 | METHOD AND APPARATUS FOR ANALYZING PATIENT'S CONSTITUTIONAL PECULIARITY - A method of analyzing checkup data of a target object, using an apparatus including at least one processor, includes receiving checkup data of a target object associated with a first disease, the checkup data including checkup values for a plurality of onset factors of the first disease; determining whether the checkup data corresponds to a first disease statistic model obtained from checkup values of a plurality of objects associated with the first disease; and calculating, when the checkup data is determined not to correspond to the first disease statistic model as a result of the determination, a peculiarity value of the target object such that a sum of adjusted checkup values, the adjusted checkup values being obtained by adjusting checkup values for respective onset factors of the first disease of the target object based on the peculiarity value, is equal to a reference value. | 04-28-2016 |
Patent application number | Description | Published |
20090286004 | METHOD OF FORMING PRINTED CIRCUIT PATTERN, FORMING GUIDE FOR PATTERN, AND GUIDE-FORMING INK - Disclosed are methods of forming a printed circuit pattern and forming a guide, and a guide-forming ink. The method of forming a printed circuit pattern in accordance with the present invention includes forming a guide by using guide-forming ink having a slip property, curing the formed guide by in-situ UV, and forming a printed circuit pattern on the inside of the cured guide by using metal ink. | 11-19-2009 |
20100053256 | INK SUCTION APPARATUS - An ink suction apparatus is disclosed. In accordance with an embodiment of the present invention, the ink suction apparatus, which sucks in residual ink of an inkjet head, includes: a suction nozzle, which sucks in the residual ink; a heater, which is adjacent to the suction nozzle and heats the suction nozzle to prevent the suction nozzle from being blocked by the residual ink; a nozzle cover, which is installed on the suction nozzle and opens and closes the suction nozzle to control sucking power of the suction nozzle; a collection chamber, which collects the residual ink having been sucked into the suction nozzle; and a suction pump, which generates sucking power and provides the sucking power to the suction nozzle. The ink suction apparatus can prevent a suction nozzle from being blocked when sucking in hyper-viscous residual ink and control the sucking power of the suction nozzle by controlling the suction nozzle's opening and closing. | 03-04-2010 |
20100196681 | METHOD OF FORMING METAL WIRING AND METAL WIRING FORMED USING THE SAME - Disclosed are a method of forming metal wiring and metal wiring formed using the same. The method includes printing wiring using an ink composition including metallic nanoparticles and dispersants maintaining dispersion of the metallic nanoparticles, performing a first firing process of firing the wiring under vacuum or in an inert atmosphere to suppress grain growth, and performing a second firing process of firing the wiring with the vacuum or inert atmosphere released, to accelerate grain growth. The method of forming metal wiring induces abnormal grain growth by rapidly removing dispersants, capable of inducing the growth of metallic nanoparticles, at a temperature at which the growth force of the metallic nanoparticles is high, in the process of firing the metallic nanoparticles. Accordingly, the metal wiring has a coarse-grained structure containing metallic particles with a large average particle size, and the electrical and mechanical characteristics thereof can be enhanced. | 08-05-2010 |
20100209619 | Printed wiring board and method for manufacturing the same - A method for manufacturing a printed wiring board having one or more layers of a conductive pattern and an insulating pattern, including forming an insulating pattern on an insulating substrate; semi-hardening at least one of the insulating substrate and the insulating pattern; forming a conductive pattern on the insulating substrate and/or the insulating pattern, thereby providing a stack structure; performing a thermal treatment on the stack structure to fully harden the semi-hardened insulating substrate and/or insulating pattern; and firing the conductive pattern. In the method, the conductive pattern and the insulating pattern are simultaneously formed on the same layer using an inkjet process. | 08-19-2010 |
20110134181 | Inkjet printer - An inkjet printer includes: a cartridge body provided with an ink chamber; a head unit coupled to a bottom surface of the cartridge body and provided with nozzles for jetting ink; and an energy irradiation unit coupled to the cartridge body so as to irradiate energy onto the ink jetted from the nozzles of the head unit. | 06-09-2011 |
20110308844 | Conductive electrode pattern and solar cell with the same - Disclosed herein is a conductive electrode pattern used as an electrode of a solar cell. The conductive electrode pattern includes a lower metal layer and an upper metal layer vertically disposed on a substrate, wherein any one of the lower metal layer and the upper metal layer includes silver (Ag) and the other one of the lower metal layer and the upper metal layer includes a metal of transition metals, different from that of the lower metal layer. | 12-22-2011 |
20110312123 | Method for forming conductive electrode pattern and method for manufacturing solar cell with the same - Disclosed herein is a conductive electrode pattern used as an electrode of a solar cell. The conductive electrode pattern includes a lower metal layer and an upper metal layer vertically disposed on a substrate, wherein any one of the lower metal layer and the upper metal layer includes silver (Ag) and the other one of the lower metal layer and the upper metal layer includes a metal of transition metals, different from that of the lower metal layer. | 12-22-2011 |
20120111401 | SOLAR CELL AND METHOD OF MANUFACTURING THE SAME - There are provided a solar cell and a method of manufacturing the same. The solar cell includes: a solar cell unit absorbing sunlight to generate electricity; a surface treatment layer formed on at least one of upper and lower surfaces of the solar cell unit by a condensation reaction of a compound having a functional group —Y having a lone pair and an alkoxy group —OR; and a metal electrode layer bonded to the functional group —Y having the lone pair of the surface treatment layer. The solar cell has excellent energy conversion efficiency. | 05-10-2012 |
20120168201 | THIN METAL FILM ELECTRODE AND FABRICATING METHOD THEREOF - There are provided a method of fabricating a thin metal film electrode and a thin metal film electrode fabricated by the same. The method of fabricating a thin metal film electrode according to an embodiment of the present invention includes applying a metal paste including a metal powder and a dispersant to a substrate to form a thin metal film; and subjecting the thin metal film to reduction firing in an atmosphere containing an organic acid and an aqueous solution in a ratio ranging from 10:90 to 90:10. | 07-05-2012 |
20120220072 | COPPER NANO PASTE, METHOD FOR FORMING THE COPPER NANO PASTE, AND METHOD FOR FORMING ELECTRODE USING THE COPPER NANO PASTE - Provided is a copper nano paste that can be calcined at a relatively low temperature. The copper nano paste includes: a binder added in an amount of 0.1 to 30 parts by weight; an additive added in an amount of not more than 10 parts by weight; and copper particles added in an amount of 1 to 95 parts by weight, wherein the copper particles have a particle size of 150 nm or less, and the surfaces of the copper particles are coated with a capping material. | 08-30-2012 |
Patent application number | Description | Published |
20100291243 | EXTRACTOR HAVING POTTERY WITH A DARK BROWN GLAZE AND THE METHOD FOR EXTRACTING USING THEREOF - Disclosed are an extractor having a “pottery with dark brown glaze” called “Onggi” in Korean, and a method of extracting using the same. The extractor includes a body, a body cover, a heating part, a pottery and a gas valve. The pottery is located within the body. The extractor extracts by injecting nitrogen gas, etc. into the body through a gas valve, thereby rendering the inside of the body to be high pressure state during extraction. Thus, the inside of the body is maintained under high pressure during extraction. Accordingly, an extract is located only within the pottery, and thus changes that can be caused while an extract contacts with the body can be prevented. | 11-18-2010 |
20110014149 | COMPOSITION FOR SKIN EXTERNAL APPLICATION CONTAINING COMPLEX OF HERBAL EXTRACTS - Disclosed is a combination for skin external use, which contains as an active ingredient an herbal extract complex consisting of Chinese herbal extracts of Granate bark, seed of | 01-20-2011 |
20120184628 | O/W TYPE COSMETIC COMPOSITION WITH IMPROVED DOSAGE FORM STABILITY - The present invention relates to an O/W type cosmetic composition with improved formulation stability, and more particularly, to an O/W type cosmetic composition comprising a branched polymer having a lipophilic alkyl side chain and an anionic surfactant, as active ingredients for improving formulation stability. | 07-19-2012 |
20130011454 | Oil-in-Water Type Nano-Emulsion Composition and Method for Preparing Same - The present invention relates to an oil-in-water (O/W) type nano-emulsion composition comprising an oil component containing oil and a polyethylene glycol ester-based emulsifier; and a water component containing a polyol or a polyol derivative. The present invention also relates to a cosmetic composition comprising the oil-in-water type nano-emulsion composition, and to a method for preparing the oil-in-water type nano-emulsion composition. According to the present invention, a nano-sized low-viscosity emulsion having a high inner phase can be obtained through the method that is different from the conventional methods of phase inversion temperature emulsification or high pressure emulsification, thereby significantly improving the stability of the emulsion. In addition, the nano-emulsion composition of the present invention can be added to a variety of cosmetic compositions having a variety of methods of use and can thus deliver active ingredients to the skin effectively since it has small-sized particles. | 01-10-2013 |
20130028951 | Polymer-Liposome Nanocomposite Composition for Percutaneous Absorption, and Method for Preparing Same - Provided are a polymer/liposome nanocomposite composition comprising lipids and poly(amino acids), and a method for preparing same. The polymer/liposome nanocomposite composition has excellent formation stability with respect to surfactants and salts, and can be used in various ways as a drug delivery system in the fields of medicine and cosmetics. | 01-31-2013 |
20130243712 | COSMETIC COMPOSITION FOR WHITENING AND IMPROVING THE RESILIENCE OF SKIN - The present invention relates to a cosmetic composition for skin whitening and anti-aging, which contains 2 or more of collagen peptides, snake needle grass extract, and white ginseng saccharides as effective ingredients, improves skin resilience by increasing the content of collagen in the skin and suppresses the growth of melanin cells, improves skin brightness and uniformity, and alleviates skin yellowness and redness, so as to provide the effect of making the skin appear clearer and more radiant. | 09-19-2013 |
20150105476 | O/W TYPE COSMETIC COMPOSITION WITH IMPROVED DOSAGE FORM STABILITY - The present invention relates to an O/W type cosmetic composition with improved formulation stability, and more particularly, to an O/W type cosmetic composition comprising a branched polymer having a lipophilic alkyl side chain and an anionic surfactant, as active ingredients for improving formulation stability. | 04-16-2015 |
Patent application number | Description | Published |
20100079717 | LIQUID CRYSTAL DISPLAY DEVICE - An LCD device preventing a short-circuit of adjacent link lines is disclosed. The LCD device includes a pixel area in which a plurality of gate lines and a plurality of data lines crossing the plurality of gate lines at a right angle are formed, a pad area formed at a side of the pixel area, a gate pad portion and a data pad portion formed in the pad area and respectively connected to the plurality of gate lines and the plurality of data lines, first, second, third, and fourth gate link lines connected to the plurality of gate lines and the gate pad portion and alternately arranged with an insulation layer interposed between the first, second, third, and fourth gate link lines, and first and second auto probe pads electrically connected to the first, second, third, and fourth gate link lines. The first and second gate link lines are connected to the first auto probe pad and the third and fourth gate link lines are connected to the second auto probe pad. | 04-01-2010 |
20120313905 | FLAT DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - The present invention relates to a flat display device and method of fabricating the same which can make narrow bezel design easy and minimize resistance variation between adjacent link lines for improving of a picture quality. The flat display device includes a display region having a plurality of pixels, a driving integrated circuit for forwarding driving signals for driving the plurality of pixels, and a plurality of link lines for transmitting the driving signals to the display region, wherein each of the plurality of link lines includes a first metal line, a second metal line formed on a layer different from the first metal line, and a contact portion for connecting the first and second metal lines to each other. | 12-13-2012 |
Patent application number | Description | Published |
20080302094 | COOLING APPARATUS OF EXHAUST GAS RECIRCULATION SYSTEM AND METHOD USING THE SAME - A cooling apparatus of an exhaust gas recirculation system includes a first cooling portion, made of a first material, that receives recirculation exhaust gas; and a second cooling portion, made of a second, different material, that receives the recirculation exhaust gas from the first cooling portion and exhausts the recirculation exhaust gas out of the apparatus. A cooling method of an exhaust gas recirculation system includes receiving a recirculation exhaust gas in a first cooling portion made of a first material; cooling the recirculation exhaust gas in the first coolant portion; receiving the recirculation exhaust gas in a second cooling portion made of a second, different material; and cooling the recirculation exhaust gas in the second coolant portion. | 12-11-2008 |
20090007565 | TURBO CHARGE SYSTEM OF AN ENGINE - A turbo charge system of an engine minimizes energy loss of exhaust gas as a consequence of a crossover pipe that connects exhaust manifolds respectively mounted to cylinder heads at both sides of the engine with each other and that is mounted in each cylinder head, and the crossover pipe is formed as a double pipe structure. The turbo charge system of the engine may include a pair of exhaust manifolds respectively mounted to cylinder heads at both sides of the engine; a pair of turbo chargers connected respectively to the pair of exhaust manifolds and increasing intake air amount by using energy of exhaust gas; and a crossover pipe connecting the pair of exhaust manifolds with each other, wherein a crossover pipe is mounted in each cylinder head. | 01-08-2009 |
20090050081 | EGR COOLANT CONTROL SYSTEM - An EGR coolant control system according to an exemplary embodiment of the present invention may include a coolant exhaust pipe connected with the coolant supply pipe, an EGR coolant supply pipe connected with the coolant supply pipe and the coolant exhaust pipe, a coolant control plate that is disposed in a junction portion of the coolant supply pipe, the coolant exhaust pipe, and the EGR coolant supply pipe, and that controls supply of a coolant, and an actuator controlling the coolant control plate according to in engine rotation speed. | 02-26-2009 |
20100139584 | Intercooler Assembly for Vehicle - An intercooler assembly for a vehicle. The intercooler assembly may include an inflow portion on which an inflow hose is mounted, the inflow portion including a buffering space to temporarily accumulate an in-flowing air, a first cooling portion fluidly connected to the inflow portion, an outflow portion on which an outflow hose is mounted, a second cooling portion fluidly connected to the outflow portion, and a turnaround portion fluidly connecting the first cooling portion and the second cooling portion, wherein the turnaround portion changes a flow direction of the in-flowing air and guides the in-flowing air toward the outflow portion so as to discharge the air. | 06-10-2010 |
20130098341 | INTERCOOLER FOR VEHICLE - An intercooler for a vehicle that cools a mixture of EGR gas and exhaust gas may include a cooler main body with an inlet portion through which the mixture flows in formed at one side thereof and an outlet portion through which the mixture flows out formed at the other end side thereof, connection tubes that connect the inlet portion with the outlet portion and are arranged from an upper side to a lower side of the cooler main body to cool the mixture, and a condensate storage unit that connects a lower end portion of the inlet portion with a lower end portion of the outlet portion and stores the condensate that is formed in the connection tubes. | 04-25-2013 |
Patent application number | Description | Published |
20110085385 | Nonvolatile Memory Devices Having Dummy Cell and Bias Methods Thereof - Provided are nonvolatile memory devices and methods of operating thereof. The nonvolatile memory devices include: dummy cells connected to a dummy bit line; and a dummy bit line bias circuit providing a dummy bit line voltage to the dummy bit line during a program operation, wherein, due to the dummy bit line voltage, at least one of the dummy cells is programmed with a threshold voltage lower than the top programmed state and higher than an erased state during the program operation. | 04-14-2011 |
20110205802 | NONVOLATILE MEMORY DEVICE AND METHOD OF READING THE SAME - Provided are a nonvolatile memory device and a method of reading the same. The nonvolatile memory device includes: a memory cell; a transistor disposed between a common source line and the memory cell; and a control logic for controlling a bias voltage of the transistor to reduce the amount of current flowing into the common source line during a read operation. The method includes: applying a read voltage to the memory cell; and controlling a bias voltage of the transistor to reduce the amount of current flowing into the common source line. | 08-25-2011 |
20110286274 | NONVOLATILE MEMORY DEVICE, PROGRAMMING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME - A nonvolatile memory device preventing a program disturb, a program method thereof and a memory system including the nonvolatile memory device and the program method. The nonvolatile memory device includes a memory cell array; first and second word lines connected to a NAND string in the memory cell array; a third word line connected to the NAND string, the third word line being disposed between the first and second word lines; a temperature sensor configured to measure the temperature of the nonvolatile memory device; and a voltage generator configured to generate first and second pass voltages and a program voltage, and the voltage level of at least one of the first and second pass voltages is controlled according to the measured temperature. When a program operation is performed, the program voltage is applied to the third word line, the first pass voltage is applied to the first word line, the second pass voltage is applied to the second word line. | 11-24-2011 |
20110298037 | VERTICAL STRUCTURE NONVOLATILE MEMORY DEVICES - A vertical structure nonvolatile memory device can include a channel layer that extends in a vertical direction on a substrate. A memory cell string includes a plurality of transistors that are disposed on the substrate in the vertical direction along a vertical sidewall of the channel layer. At least one of the plurality of transistors includes at least one recess in a gate of the transistor into which at least one protrusion, which includes the channel layer, extends. | 12-08-2011 |
20110305079 | NONVOLATILE MEMORY DEVICE INCLUDING DUMMY MEMORY CELL AND PROGRAM METHOD THEREOF - A nonvolatile memory device including a dummy memory cell and a method of programming the same, wherein the nonvolatile memory device includes a dummy memory cell, and a plurality of memory cells serially connected to the dummy memory cell. The nonvolatile memory device sets a voltage provided to the dummy memory cell according to a distance between a selected memory cell among the plurality of memory cells and the dummy memory cell when a program operation is performed. | 12-15-2011 |
20120003828 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME - A method of manufacturing a semiconductor device includes forming a laminated structure including sacrificial layers and a select gate layer on a substrate, forming a penetration region penetrating the laminated structure, forming a select gate insulating layer on a sidewall of the select gate layer exposed by the penetration region, and forming an active pattern in the penetration region. The method also includes exposing a portion of the active pattern by removing the sacrificial layers and forming an information storage layer on the exposed portion of the active pattern. | 01-05-2012 |
20120043673 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the conductive patterns and vertical adjacent regions between the channel regions, and a semiconductor connecting layer extending from an outer sidewall of the semiconductor pattern to connect the semiconductor pattern to the substrate. | 02-23-2012 |
20120112264 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure. | 05-10-2012 |
20120146118 | NON-VOLATILE MEMORY DEVICE WITH HIGH SPEED OPERATION AND LOWER POWER CONSUMPTION - A semiconductor memory device has a memory cell region and a peripheral region. The device includes low voltage transistors at the peripheral region having gate insulation films with different thicknesses. For example, a gate insulation film of a low voltage transistor used in an input/output circuit of the memory device may be thinner than the gate insulation film of a low voltage transistor used in a core circuit for the memory device. Since low voltage transistors used at an input/output circuit are formed to be different from low voltage transistors used at a core circuit or a high voltage pump circuit, high speed operation and low power consumption characteristics of a non-volatile memory device may be. | 06-14-2012 |
20120199897 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICES - Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed. | 08-09-2012 |
20120326225 | NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a substrate having an active region defined by a device isolation region that has a trench and an air gap, a device isolation pattern positioned at a lower portion of the trench, a memory cell layer including a tunnel insulation layer, a trap insulation layer and a blocking insulation layer that are sequentially stacked on the active region and one of which extends from the active region toward the device isolation region encloses top of the air gap whose bottom is defined by a layer other than that of the top, and a control gate electrode positioned on the cell structure. The one of the insulation layer extending includes a recess at a region corresponding to the center of the air gap. | 12-27-2012 |
20130301350 | Vertical Structure Nonvolatile Memory Device - A vertical structure nonvolatile memory device can include a channel layer that extends in a vertical direction on a substrate. A memory cell string includes a plurality of transistors that are disposed on the substrate in the vertical direction along a vertical sidewall of the channel layer. At least one of the plurality of transistors includes at least one recess in a gate of the transistor into which at least one protrusion, which includes the channel layer, extends. | 11-14-2013 |
20140087534 | METHODS OF MANUFACTURING VERTICAL STRUCTURE NONVOLATILE MEMORY DEVICES - A vertical structure nonvolatile memory device can include a channel layer that extends in a vertical direction on a substrate. A memory cell string includes a plurality of transistors that are disposed on the substrate in the vertical direction along a vertical sidewall of the channel layer. At least one of the plurality of transistors includes at least one recess in a gate of the transistor into which at least one protrusion, which includes the channel layer, extends. | 03-27-2014 |
20140094012 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES - Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the conductive patterns and vertical adjacent regions between the channel regions, and a semiconductor connecting layer extending from an outer sidewall of the semiconductor pattern to connect the semiconductor pattern to the substrate. | 04-03-2014 |
20150132906 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A 3D semiconductor device includes an electrode structure has electrodes stacked on a substrate, semiconductor patterns penetrating the electrode structure, charge storing patterns interposed between the semiconductor patterns and the electrode structure, and blocking insulating patterns interposed between the charge storing patterns and the electrode structure. Each of the blocking insulating patterns surrounds the semiconductor patterns, and the charge storing patterns are horizontally spaced from each other and configured in such a way as to each be disposed around a respective one of the semiconductor patterns. Also, each of the charge storing patterns includes a plurality of horizontal segments, each interposed between vertically adjacent ones of the electrodes. | 05-14-2015 |
20150187791 | METHODS OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR DEVICES - A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure. | 07-02-2015 |
20150303215 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A 3D semiconductor device includes an electrode structure has electrodes stacked on a substrate, semiconductor patterns penetrating the electrode structure, charge storing patterns interposed between the semiconductor patterns and the electrode structure, and blocking insulating patterns interposed between the charge storing patterns and the electrode structure. Each of the blocking insulating patterns surrounds the semiconductor patterns, and the charge storing patterns are horizontally spaced from each other and configured in such a way as to each be disposed around a respective one of the semiconductor patterns. Also, each of the charge storing patterns includes a plurality of horizontal segments, each interposed between vertically adjacent ones of the electrodes. | 10-22-2015 |
Patent application number | Description | Published |
20090026515 | Semiconductor memory device and method of forming the same - Example embodiments relate to a semiconductor memory device and a method of forming the semiconductor memory device. The semiconductor memory device may include a first interlayer insulating layer on a semiconductor substrate. A bit line may be arranged in a first direction on the first interlayer insulating layer. A bit line contact pad may be disposed in the first interlayer insulating layer and electrically connected to the bit line. A storage contact pad may be disposed in the first interlayer insulating layer. A top surface of the bit line contact pad may be lower than a top surface of the storage contact pad. | 01-29-2009 |
20090186471 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE FOR REDUCING THERMAL BURDEN ON IMPURITY REGIONS OF PERIPHERAL CIRCUIT REGION - A method of fabricating a semiconductor device for reducing a thermal burden on impurity regions of a peripheral circuit region includes preparing a substrate including a cell active region in a cell array region and peripheral active regions in a peripheral circuit region. A cell gate pattern and peripheral gate patterns may be formed on the cell active region and the peripheral active regions. First cell impurity regions may be formed in the cell active region. A first insulating layer and a sacrificial insulating layer may be formed to surround the cell gate pattern and the peripheral gate patterns. Cell conductive pads may be formed in the first insulating layer to electrically connect the first cell impurity regions. The sacrificial insulating layer may be removed adjacent to the peripheral gate patterns. First and second peripheral impurity regions may be sequentially formed in the peripheral active regions adjacent to the peripheral gate patterns. | 07-23-2009 |
20100270647 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING CAPACITOR - Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode. | 10-28-2010 |
20110183512 | METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING CONTACT PLUG - A method of forming a semiconductor device includes forming a lower conductive pattern on a substrate, forming an insulating layer over the lower conductive pattern, forming a contact hole through the insulating layer to expose the lower conductive pattern, forming a first spacer along sides of the contact hole, and then forming a contact plug in the contact hole. The contact plug is formed so as to contact the lower conductive pattern. | 07-28-2011 |
20110241102 | SEMICONDUCTOR DEVICES INCLUDING BIT LINE CONTACT PLUG AND BURIED CHANNEL ARRAY TRANSISTOR, METHODS OF FABRICATING THE SAME, AND SEMICONDUCTOR MODULES, ELECTRONIC CIRCUIT BOARDS AND ELECTRONIC SYSTEMS INCLUDING THE SAME - A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode. | 10-06-2011 |
20110256719 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a first contact opening having a relatively larger depth than a second contact opening to expose first and second contacts through an insulation layer, where the first and second contacts are located at different depths with respect to an upper surface of the insulation layer. Therefore, it is possible to prevent excessive over-etch of the second contact opening and minimize etching damage to the contact region exposed by the second contact opening. | 10-20-2011 |
20130228856 | SEMICONDUCTOR DEVICES INCLUDING BIT LINE CONTACT PLUG AND PERIPHERAL TRANSISTOR - A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode. | 09-05-2013 |
20140028567 | DISPLAY DEVICE AND CONTROL METHOD THEREOF - Disclosed are a display device and a control method thereof. The display device includes a display, a camera capturing a gesture in a three dimensional space; and a controller selectively displaying a virtual keyboard corresponding to a hand gesture for character input on the display when the captured gesture includes the hand gesture for the character input. Accordingly, the virtual keyboard corresponding to the hand gesture for the character input is displayed, so that the user may not perform an additional operation to display the virtual keyboard. | 01-30-2014 |
20150048444 | SEMICONDUCTOR DEVICES INCLUDING BIT LINE CONTACT PLUG AND PERIPHERAL TRANSISTOR - A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode. | 02-19-2015 |
20160104671 | SEMICONDUCTOR DEVICES INCLUDING BIT LINE CONTACT PLUG AND PERIPHERAL TRANSISTOR - A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode. | 04-14-2016 |
Patent application number | Description | Published |
20080294767 | Ubiquitous Wireless Network System, Node Module, and Operation Method of the Node Module - A ubiquitous wireless network system, node module, and operation method of the node module are disclosed. The present invention allows a display unit to display detected information or received information when the information corresponds to its own node module as an arrival destination. Therefore, the present invention enables users to ascertain the surrounding physical context around the corresponding node module or the information inputted by the administrator. | 11-27-2008 |
20120150438 | Road Information Provision System Using Navigation Device - The present invention relates to a system for providing road information using a navigation device, and provides road information detected by a road information provision device installed on the road to a driver by transmitting the road information to a navigation device in a wireless manner. Accordingly, the present invention has the advantage of a driver being able to promptly and precisely perceive road information, which has been detected by a road information provision device installed on the road and has been transmitted to a navigation device in a wireless manner, thus allowing the driver to safely drive the vehicle. Further, there is the advantage of road information being able to be provided directly from a road information provision device, so that there is no need to pass a separate facility for collecting, analyzing and providing road information or to subscribe to a separate service for road information. | 06-14-2012 |
20120297974 | SYSTEM FOR COLLECTING POLLUTED AIR, DEVICE FOR COLLECTING POLLUTED AIR AND METHOD THEREOF - An apparatus for collecting contaminated air, including: an air pollution detecting unit for monitoring pollution status of air existing in the pertinent area; an air collecting unit for collecting and storing part of the air; and a control unit for comparing data about the pollution status monitored by the detecting unit with preset critical values and commanding the collecting unit to collect a part of the air when data about the pollution status is equal to or greater than the critical values. Since contaminated air is collected by monitoring the pollution status of contaminated air existing in the atmosphere of a pertinent area or the gaseous contaminant-containing air discharged from sources in real time, it is possible to collect air pollution evidence. The collecting unit provided at the outlet of a source, allows air pollution data to be stored after analyzing collected air, making it possible to lawfully sanction air polluter. | 11-29-2012 |
Patent application number | Description | Published |
20090283316 | CIRCUIT BOARD VIAHOLES AND METHOD OF MANUFACTURING THE SAME - Provided are a circuit board with a viahole and a method of manufacturing the same. The circuit board includes: a substrate formed of an insulating material; a conductive layer disposed on the substrate; a plated layer comprising nickel and disposed on the conductive layer; and a viahole passing through the substrate, the conductive layer, and the plated layer, wherein a crystal growth direction of nickel in the plated layer is parallel to a thickness-wise direction of the substrate. | 11-19-2009 |
20090283884 | LEAD FRAME, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE LEAD FRAME AND THE SEMICONDUCTOR PACKAGE - Provided are a lead frame, a semiconductor package, and a method of manufacturing the lead frame and the semiconductor package. The lead frame includes: a die pad on which a semiconductor chip is installable; a plurality of lead patterns formed around a circumference of the die pad; an insulating organic material filling etching spaces interposed between the die pad and the lead patterns and structurally supporting the die pad and the lead patterns; and a pre-plating layer formed on both upper and lower surfaces of the die pad and the lead patterns. | 11-19-2009 |
20100116528 | PRINTED CIRCUIT BOARD WITH MULTIPLE METALLIC LAYERS AND METHOD OF MANUFACTURING THE SAME - Provided is a printed circuit board (PCB) with multiple metallic layers and a method of manufacturing the PCB to improve adhesion between a metal film and a polymer film, on which a circuit pattern is formed. The PCB includes: a first metal film; a polymer film formed on one surface of the first metal film; and a second metal film, interposed between the first metal film and the polymer film, having a first surface facing the first metal film and a second surface facing the polymer film, wherein the second surface is rougher than the first surface. | 05-13-2010 |
20120098112 | LEAD FRAME MANUFACTURED FROM LOW-PRICED MATERIAL AND NOT REQUIRING STRICT PROCESS CONTROL, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE LEAD FRAME AND THE SEMICONDUCTOR PACKAGE - Provided are a lead frame, a semiconductor package, and a method of manufacturing the lead frame and the semiconductor package. The lead frame includes: a die pad on which a semiconductor chip is installable; a plurality of lead patterns formed around a circumference of the die pad; an insulating organic material filling etching spaces interposed between the die pad and the lead patterns and structurally supporting the die pad and the lead patterns; and a pre-plating layer formed on both upper and lower surfaces of the die pad and the lead patterns. | 04-26-2012 |
20120279775 | CIRCUIT BOARD VIAHOLES AND METHOD OF MANUFACTURING THE SAME - Provided are a circuit board with a viahole and a method of manufacturing the same. The circuit board includes: a substrate formed of an insulating material; a conductive layer disposed on the substrate; a plated layer comprising nickel and disposed on the conductive layer; and a viahole passing through the substrate, the conductive layer, and the plated layer, wherein a crystal growth direction of nickel in the plated layer is parallel to a thickness-wise direction of the substrate. | 11-08-2012 |
Patent application number | Description | Published |
20130181566 | ROTOR AND MOTOR INCLUDING THE SAME - A rotor is and a motor including the rotor and a stator are provided. The rotor includes a rotor core and rotor poles. The rotor poles are arranged circumferentially around the rotor core, and each of the rotor poles is formed in an asymmetric shape. The stator is spaced apart from the rotor and includes slots configured for a coil to be wound therearound. | 07-18-2013 |
20150014322 | CUP LID AND PORTABLE PROTECTION CASE THEREFOR - Provided is a cup lid including: a cover portion that covers an upper opened portion of a cup; a coupling portion that is formed at edges of the cover portion and is coupled to the upper opened portion of the cup; a beverage guide portion that is formed between the cover portion and the coupling portion, is elevated to have a predetermined height, provides a cooling space of a beverage and guides the beverage to a user's mouth; and beverage discharge portions that are formed at the cover portion and the beverage guide portion, discharge the beverage in the cup to be accommodated in the cooling space or cause all of the beverage that remains in the cup to be discharged to a portion that faces the cooling space. | 01-15-2015 |
20150145371 | MOTOR - A motor includes a cylindrical stator having a hollow, and a rotor rotatably arranged inside the stator. The rotor includes a cylindrical rotor body, a permanent magnet group provided to the rotor body to generate a magnetic field, and a flux barrier group to interrupt magnetic flux. The rotor body, the permanent magnet group and the flux barrier group are asymmetrically formed with respect to a center of poles of the rotor. | 05-28-2015 |
20150194749 | CONNECTOR AND REFRIGERATOR INCLUDING THE SAME - A refrigerator having an inner case that constitutes a storage compartment, an outer case that is coupled to an outer side of the inner case and constitutes an exterior, and a connector that connects a flexible flat cable (FFC) and wires. The connector includes a first housing having an accommodation space in which the FFC is inserted, a plurality of second housings in which a wire insertion hole into which the wires are inserted, is formed and which are coupled to the first housing, and connection members provided in the first housing and the plurality of second housings so as to electrically connect the FFC and the wires. The connector is installed at the inner case in such a way that the first housing faces the outer case and the second housings face the storage compartment. | 07-09-2015 |
20150201777 | CUP LID AND PORTABLE PROTECTION CASE THEREFOR - Provided is a cup lid including: a cover portion that covers an upper opened portion of a cup; a coupling portion that is formed at edges of the cover portion and is coupled to the upper opened portion of the cup; a beverage guide portion that is formed between the cover portion and the coupling portion, is elevated to have a predetermined height, provides a cooling space of a beverage and guides the beverage to a user's mouth; and beverage discharge portions that are formed at the cover portion and the beverage guide portion, discharge the beverage in the cup to be accommodated in the cooling space or cause all of the beverage that remains in the cup to be discharged to a portion that faces the cooling space. | 07-23-2015 |
20150288233 | ROTOR AND MOTOR USING THE SAME - A rotor and a motor using the same may include a cylindrical main core having an inner diameter and an outer diameter; a plurality of radial cores, each of which extends in a direction perpendicular to an outer circumference edge of the main core; a plurality of magnetic flux concentration cores placed between the radial cores, respectively; a plurality of inner coupling parts, each of which connects the main core and the plurality of magnetic flux concentration cores and has a width smaller than the width of the radial core; a rotor core having permanent magnet seating parts provided at both sides of the radial core in parallel with the radial core; and a plurality of permanent magnets placed on the permanent magnet seating parts, and magnetized such that opposite poles face each other with the radial core centered therebetween. | 10-08-2015 |
Patent application number | Description | Published |
20100054717 | STEAM GENERATOR OF STEAM OVEN - Disclosed is a steam oven to cook food in a cooking chamber by use of steam. More particularly, disclosed is a steam generator of a steam oven, which can simplify the configuration of a device required to generate steam and is detachably attached to a cabinet to assure easy cleaning and washing thereof. The steam generator includes a single body having an inner space divided into a water supply compartment and a boiler compartment by a partition, the water supply compartment having a water pouring hole, and the boiler compartment having a heater and a steam discharge hole. Also, a water supply passage is defined between the water supply compartment and the boiler compartment. This configuration has the effects of achieving improved workability and reduced manufacturing costs of the steam generator and also, of overcoming a limit in the inner volume of a cooking chamber of the steam oven. | 03-04-2010 |
20130019143 | Memory Device And Method Of Storing Data With Error Correction Using Codewords - Memory devices and/or methods of storing memory data bits are provided. A memory device includes a multi-level cell (MLC) array including a plurality of MLCs, an error correction unit configured to encode data to be recorded in an MLC, where the encoded data is converted to convert the encoded data into a codeword, an error pattern analysis unit configured to analyze a first data pattern included in the codeword corresponding to an error pattern included in the codeword and a data conversion unit configured to convert the analyzed first data pattern into a second data pattern. According to the above memory devices and/or methods, it is possible to efficiently reduce a data error that occurs when the data is stored for a relatively long period of time, thereby improving reliability. | 01-17-2013 |
20150195198 | METHOD AND APPARATUS FOR RELAYING PACKET TRANSMISSION AND UPDATING NETWORK ADDRESS INFORMATION IN COMMUNICATION SYSTEM - A method to transmit and receive a packet in a bridge of a communication system is provided. The method includes receiving a first packet from a first network. The method also includes converting a medium access control (MAC) layer source address of the received first packet into a MAC address of the bridge. The method further includes transmitting the address-converted first packet to a node of a second network. | 07-09-2015 |
20150237515 | METHOD FOR COLLECTING INFORMATION BY ELECTRONIC DEVICE AND ELECTRONIC DEVICE THEREFOR - A method of an electronic device and a method of a server are provided. The method of the electronic device includes receiving a broadcast signal broadcast by another electronic device via a wireless communication; determining, based on the received broadcast signal, a number of times the another electronic device has been detected; and sending a request for information to the another electronic device, based on the determined number of times the another electronic device has been detected. The method of the server includes receiving information from a first electronic device; receiving, from a second electronic device, an information request message relating to the first electronic device which has been detected a threshold number of times or more by the second electronic device; and transmitting information registered by the first electronic device to the second electronic device. | 08-20-2015 |