Patent application number | Description | Published |
20110273974 | METHOD AND APPARATUS FOR OFFSET AND GAIN CORRECTION - Aspects of the disclosure provide a signal processing circuit that has fast response time to sudden profile changes in an electrical signal. The signal processing circuit includes a processing path configured to process an electrical signal that is generated in response to reading data on a storage medium, and a feed-forward correction module. The feed-forward correction module is configured to detect a profile variation based the electrical signal in a time window, and correct the electrical signal in the time window based on the detected profile variation. | 11-10-2011 |
20140126342 | METHOD AND APPARATUS FOR OFFSET AND GAIN CORRECTION - Aspects of the disclosure provide a signal processing circuit that has fast response time to sudden profile changes in an electrical signal. The signal processing circuit includes a processing path configured to process an electrical signal that is generated in response to reading data on a storage medium, and a feed-forward correction module. The feed-forward correction module is configured to detect a profile variation based the electrical signal in a time window, and correct the electrical signal in the time window based on the detected profile variation. | 05-08-2014 |
20150139603 | Modeless Video and Still Frame Capture - In an embodiment, an electronic device may be configured to capture still frames during video capture, but may capture the still frames in the 4×3 aspect ratio and at higher resolution than the 16×9 aspect ratio video frames. The device may interleave high resolution, 4×3 frames and lower resolution 16×9 frames in the video sequence, and may capture the nearest higher resolution, 4×3 frame when the user indicates the capture of a still frame. Alternatively, the device may display 16×9 frames in the video sequence, and then expand to 4×3 frames when a shutter button is pressed. The device may capture the still frame and return to the 16×9 video frames responsive to a release of the shutter button. | 05-21-2015 |
20150206558 | SYSTEMS AND METHODS FOR MONITORING AND CONTROLLING REPETITIVE ACCESSES TO VOLATILE MEMORY - Systems and methods for monitoring and controlling repetitive accesses to a dynamic random-access memory (DRAM) row are disclosed. A method for monitoring and controlling repetitive accesses to a DRAM can include dividing a bank of the DRAM into a number of logical blocks, mapping each row of the bank to one of the logical blocks, monitoring accesses to the logical blocks, and controlling accesses to the logical blocks based on the monitoring. | 07-23-2015 |
Patent application number | Description | Published |
20090030944 | CONTRACT-CENTRIC CONTENT SYSTEM - A method and system to manage content is provided to generate an abstraction layer between a user application and content, based on a formal definition of content (referred to as a content contract). An example content system comprises a content bundle module, a user application, and a content access interface module. The content bundle module may be configured to store content items. A content item may include text items and placeholders. The user application, which does not have to be coded with specific knowledge regarding the content bundle, may be configured to receive a request to provide to a to a client system a presentation package (e.g., a web page) that has the content item, and to obtain the content item and any associated metadata from the content access interface module. Content item metadata may include, for example, information regarding a value to populate a placeholder in the content item. | 01-29-2009 |
20090031287 | CONTAINER-LESS JSP TEMPLATE - A container-less JSP system is provided. An example container-less JSP system comprises a detector, a trigger module, and an invoker. The detector may be configured to detect a request initiated by a client application to invoke a JSP template. The request is a protocol-neutral Java™ interface. The trigger module may be configured to trigger the protocol-neutral Java™ interface to invoke the JSP template. The invoker may be configured to invoke the JSP template. | 01-29-2009 |
20100280915 | SYSTEMS AND METHODS FOR PROVIDING INFORMATION ON A MOBILE DEVICE - Example methods and systems described herein provide information on a mobile device. Some example embodiments may include receiving information that is current as of a specific period. The information may be subject to change with a progression of time. An example embodiment includes causing the received information to be output to a user interface of a mobile device at the same time that an element of a computing application is being output to the user interface. The element of the computing application may be associated with a computing application that is being executed by the mobile device. | 11-04-2010 |
20110197197 | WIDGET FRAMEWORK, REAL-TIME SERVICE ORCHESTRATION, AND REAL-TIME RESOURCE AGGREGATION - A method to optimize calls to a service by components of an application running on an application server is provided. The method includes receiving a first call and a second call, the first call made to a service by a first one of a plurality of components included in the application, and the second call made to the service by a second one of the plurality of components; selecting one of a plurality of optimizations, the plurality of optimizations including orchestrating the first call and the second call into a third call to the service; and, in response to the selecting of the orchestrating of the first call and the second call into the third call as the one of the plurality of optimizations, orchestrating the first call and the second call into the third call. | 08-11-2011 |
20120233312 | MANAGING DELIVERY OF APPLICATION SERVER CONTENT - A method of managing delivery of content to end users of an application executing on an application server is disclosed. A definition of a first variant of a web page is received, the definition of the first variant specifying that an instance of a first widget is to be included in the first variant at a first region conforming to a page layout of the web page. A definition of a second variant of the web page is received, the definition of the second variant specifying that an instance of a second widget is to be included in the second variant at a second region conforming to the page layout of the web page. A comparison of the first variant and the second variant is presented with respect to a performance metric, the performance metric pertaining to an effectiveness of the web page at bringing in revenues to a network-based publication system. | 09-13-2012 |
20140236783 | MANAGING DELIVERY OF APPLICATION SERVER CONTENT - A method of managing delivery of content to end users of an application executing on an application server is disclosed. A definition of a first variant of a web page is received, the definition of the first variant specifying that an instance of a first widget is to be included in the first variant at a first region conforming to a page layout of the web page. A definition of a second variant of the web page is received, the definition of the second variant specifying that an instance of a second widget is to be included in the second variant at a second region conforming to the page layout of the web page. A comparison of the first variant and the second variant is presented with respect to a performance metric, the performance metric pertaining to an effectiveness of the web page at bringing in revenues to a network-based publication system. | 08-21-2014 |
Patent application number | Description | Published |
20090086448 | SOLID STATE DRIVE WITH COVERLESS CASING - The present invention discloses a solid state drive with a coverless casing, which comprises: a printed circuit board assembly and a coverless casing. In the resent invention, the coverless casing is free of a top cover; thereby, air circulation can be enhanced to cool down the electronic components on a printed circuit board assembly more efficiently. Further, in the present invention, the coverless casing is designed to have the printed circuit board assembly electrically connected to the chassis ground of the host system via the coverless casings; thereby, unwanted electrostatic charges can be dissipated to the chassis ground of the host system before it can damage the electronic components on the printed circuit board assembly; thus, the ESD resistance thereof is promoted. Furthermore, the solid state drive with a coverless casing of the present invention is made of lightweight materials and easy to fabricate and simple to assemble; therefore, the present invention have the advantages of light weight and low cost. | 04-02-2009 |
20090097215 | UV-EPOXY AND ULTRASONIC CASE ASSEMBLY METHODS FOR USB FLASH DRIVE - The present invention discloses UV-epoxy and ultrasonic case assembly methods for a USB flash drive, wherein a transparent or translucent top cover is fastened to a bottom cover containing a printed circuit board assembly via an UV-cure epoxy glue or an ultrasonic weld method. As the top cover of the USB flash drive is transparent or translucent, the USB flash drive has a see-through property and presents an aesthetic taste, which can attract the attention of consumers. Further, the method of the present invention uses less case parts and fewer steps and thus can fabricate a USB flash drive having a lower cost and a better quality at a higher throughput. Furthermore, the USB flash drive fabricated according to the method of the present invention has a better moisture resistance and a better water resistance. | 04-16-2009 |
20100000655 | Memory Module Assembly Including Heat Sink Attached To Integrated Circuits By Adhesive And Clips - A memory module assembly includes two-plate heat sink attached to one or more of the integrated circuits (e.g., memory devices) of a memory module PCBA by adhesive. The adhesive is either heat-activated or heat-cured. The adhesive is applied to either the memory devices or the heat-sink plates, and then compressed between the heat-sink plates and memory module using a fixture. The fixture is then passed through an oven to activate/cure the adhesive. The two heat sink plates are then secured by a clip to form a rigid frame. | 01-07-2010 |
Patent application number | Description | Published |
20110070661 | RAMAN-ACTIVE REAGENTS AND THE USE THEREOF - The present invention provides a new class of Raman-active reagents for use in biological and other applications, as well as methods and kits for their use and manufacture. Each reagent includes a Raman-active reporter molecule, a binding molecule, and a surface enhancing particle capable of causing surface enhanced Raman scattering (SERS). The Raman-active reporter molecule and the binding molecule are affixed to the particle to give both a strong SERS signal and to provide biological functionality, i.e. antigen or drug recognition. The Raman-active reagents can function as an alternative to fluorescence-labeled reagents, with advantages in detection including signal stability, sensitivity, and the ability to simultaneously detect several biological materials. The Raman-active reagents also have a wide range of applications, especially in clinical fields (e.g., immunoassays, imaging, and drug screening). | 03-24-2011 |
20110070662 | RAMAN-ACTIVE REAGENTS AND THE USE THEREOF - The present invention provides a new class of Raman-active reagents for use in biological and other applications, as well as methods and kits for their use and manufacture. Each reagent includes a Raman-active reporter molecule, a binding molecule, and a surface enhancing particle capable of causing surface enhanced Raman scattering (SERS). The Raman-active reporter molecule and the binding molecule are affixed to the particle to give both a strong SERS signal and to provide biological functionality, i.e. antigen or drug recognition. The Raman-active reagents can function as an alternative to fluorescence-labeled reagents, with advantages in detection including signal stability, sensitivity, and the ability to simultaneously detect several biological materials. The Raman-active reagents also have a wide range of applications, especially in clinical fields (e.g., immunoassays, imaging, and drug screening). | 03-24-2011 |
Patent application number | Description | Published |
20110084371 | MODULAR LOW STRESS PACKAGE TECHNOLOGY - A protective modular package cover has first and second fastening sections located at opposing first and second ends with one or more subassembly receiving sections disposed thereto and is configured to fasten the protective modular package cover to a core. Each fastening section has a foot surface located on a bottom surface of a fastening section and configured to make contact with the core, a mounting hole configured to receive a fastener, and a torque element. Each subassembly receiving section is configured to receive a subassembly and has a cross member formed along the underside of the protective modular package cover. Activation of the first torque element transfers a downward clamping force generated at the fastening element to a top surface of one or more subassemblies disposed in the one or more subassembly receiving sections via the cross member of each of the one or more subassembly receiving sections. | 04-14-2011 |
20110084376 | MODULAR LOW STRESS PACKAGE TECHNOLOGY - A protective modular package assembly with one or more subassemblies, each having a base element, a sidewall element coupled to the base element, and a semiconductor device disposed within and coupled to the sidewall element and the base element; a protective modular package cover having fastening sections located at opposing ends of the cover, torque elements disposed on the opposing ends and configured to fasten the cover to a core, and subassembly receiving sections disposed between the fastening sections with each subassembly receiving section operable to receive a subassembly and having a cross member along the underside of the cover; and an adhesive layer configured to affix subassemblies to respective subassembly receiving sections. The torque elements are configured to transfer a downward clamping force generated at the fastening elements to a top surface of the subassemblies via the cross member of each of the one or more subassembly receiving sections. | 04-14-2011 |
20110086469 | MODULAR LOW STRESS PACKAGE TECHNOLOGY - A method of manufacturing a protected package assembly: providing a protective modular package cover in accordance with a modular design; selectively applying an adhesive to the cross member of each subassembly receiving section of the protective modular package cover that will receive a subassembly to form an adhesive layer of the protective modular package cover; encapsulating the one or more subassemblies in the subassembly receiving sections on the selectively applied adhesive layer to generate a protected package assembly; and controlling application of a distributed downward clamping force applied to the top surfaces of the subassemblies received by the protective modular package cover and useful for mounting the protected package assembly to a core through activation of fastener elements and cross members of the subassembly receiving sections. | 04-14-2011 |
20110087353 | MODULAR LOW STRESS PACKAGE TECHNOLOGY - A method of designing a modular package: determining a package outline of a modular package assembly from package outline design data; determining seating plane and overall package length characteristics of the assembly from seating plane and package length design data; the design tool calculating minimum package height of the modular package assembly from the seating plane and package length design data; designing the dimensions and configuration of one or more subassemblies from subassembly design data; defining dimensions and configuration of a plurality of mechanical layers of a protective modular package cover given the defined package outline, the seating plane, overall package length, the minimum package height, and the subassemblies; defining an adhesive deposition strategy to join mechanical layers of the cover; designing the cover in accordance with the dimensions and configuration of the mechanical layers; and incorporating the assembly and the adhesive deposition strategy into a manufacturing assembly process. | 04-14-2011 |
20110087356 | MODULAR LOW STRESS PACKAGE TECHNOLOGY - A method of designing a desired modular package assembly: determining the configuration and dimensions of the assembly from received user input design data, the assembly having a protective modular package cover with first and second fastening sections, subassembly receiving sections disposed between the fastening sections and having a cross member formed along the underside of the protective modular package cover and configured to receive a subassembly, and one or more subassemblies to be received by the subassembly receiving sections; determining an adhesive deposition strategy for deposition of an adhesive layer to the cross members of the subassembly receiving sections sufficient to affix the top side of the subassemblies to the cross members on the underside of the subassembly receiving sections; and incorporating the configuration and dimensions of the modular package assembly and the adhesive deposition strategy into a manufacturing assembly process configured to manufacture the modular package assembly. | 04-14-2011 |
Patent application number | Description | Published |
20110295836 | SYSTEMS AND METHODS FOR PROVIDING VALUE HIERARCHIES, RAGGED HIERARCHIES AND SKIP-LEVEL HIERARCHIES IN A BUSINESS INTELLIGENCE SERVER - A business intelligence (BI) server and repository are described which support a set of hierarchical relationships among the data. The BI server receives user input specifying a set of parent-child or other ancestral relationship among a set of data in a data source. The BI server generates a set of SQL queries and executes the queries to pre-populate a set of tables which specify the parent child relationships among the data in the data source. One such table is a parent-child relationship closure table that defines the inter-member relationships among the data members. Once the tables are populated, the BI server uses the closure tables to answer queries that require knowledge of the ancestral relationships among data. | 12-01-2011 |
20110295837 | SYSTEMS AND METHODS FOR PROVIDING MULTILINGUAL SUPPORT FOR DATA USED WITH A BUSINESS INTELLIGENCE SERVER - A business intelligence (BI) server is described that supports data and schemas stored in multiple languages. The BI server implements a lookup table and lookup function that allows users to work with queries in different languages. When the user logs in, a session object is created for the user, which maintains the state information. A session variable specifies the language currently being used by the user. The BI server can inspect this session variable to determine the language of the user and perform the lookup translations as necessary. For example, if the language used by the session is different from the language of the base table storing the necessary information, the BI server can perform a translation by invoking a lookup function. The execution of the lookup can include performing a join operation of the base table with the lookup table to yield a translated value requested by the query. | 12-01-2011 |
20110295870 | SYSTEMS AND METHODS FOR PROVIDING CUSTOM OR CALCULATED DATA MEMBERS IN QUERIES OF A BUSINESS INTELLIGENCE SERVER - A business intelligence (BI) server and repository are described which support a set of customized and/or calculated data members. In accordance with an embodiment, the BI server maintains a connection to a plurality of data sources which may store a set of dimension members. The data source can be relational, file storage based, multidimensional and other types. In accordance with an embodiment, the BI server can accept queries from the user that contain calculated members as a parameter. The calculated member is defined by an expression including multiple dimension members and one or more arithmetic operators. The BI server can parse and validate the query and rewrite the query for the data source. After the query is rewritten and optimized, it is executed against the data source and a set of results is received. | 12-01-2011 |
Patent application number | Description | Published |
20110095367 | ESD/ANTENNA DIODES FOR THROUGH-SILICON VIAS - Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone. | 04-28-2011 |
20110138157 | CONVOLUTION COMPUTATION FOR MANY-CORE PROCESSOR ARCHITECTURES - A convolution of the kernel over a layout in a multi-core processor system includes identifying a sector, called a dynamic band, of the layout including a plurality of evaluation points. Layout data specifying the sector of the layout is loaded in shared memory, which is shared by a plurality of processor cores. A convolution operation of the kernel and the evaluation points in the sector is executed. The convolution operation includes iteratively loading parts of the basis data set, called a stride, into space available in shared memory given the size of the layout data specifying the sector. A plurality of threads is executed concurrently using the layout data for the sector and the currently loaded part of the basis data set. The iteration for the loading basis data set proceeds through the entire data set until the convolution operation is completed. | 06-09-2011 |
20120295433 | ESD/ANTENNA DIODES FOR THROUGH-SILICON VIAS - Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone. | 11-22-2012 |
20130263076 | BANDED COMPUTATION ARCHITECTURES - A convolution of the kernel over a layout in a multi-core processor system includes identifying a sector, called a dynamic band, of the layout including a plurality of evaluation points. Layout data specifying the sector of the layout is loaded in shared memory, which is shared by a plurality of processor cores. A convolution operation of the kernel and the evaluation points in the sector is executed. The convolution operation includes iteratively loading parts of the basis data set, called a stride, into space available in shared memory given the size of the layout data specifying the sector. A plurality of threads is executed concurrently using the layout data for the sector and the currently loaded part of the basis data set. The iteration for the loading basis data set proceeds through the entire data set until the convolution operation is completed. | 10-03-2013 |
Patent application number | Description | Published |
20080202688 | Silicon Carbide Gas Distribution Plate and RF Electrode for Plasma Etch Chamber - A showerhead for use in a capacitively-coupled plasma chamber and made of low resistivity bulk layer coated with CVD SiC. The bulk low resitivity material may be, for example, graphite, Silicon Carbide (SiC), converted graphite, SiC+C, etc. Sintered SiC may be used as the bulk material coated with CVD SiC to provide a showerhead that is suitable for use in a capacitively-coupled plasma chamber. | 08-28-2008 |
20110253673 | PLASMA PROCESSING METHOD AND APPARATUS WITH CONTROL OF PLASMA EXCITATION POWER - The amount of RF power supplied to a plasma in a vacuum plasma processing chamber is gradually changed on a preprogrammed basis in response to signals stored in a computer memory. The computer memory stores signals so that other processing chamber parameters (pressure, gas species and gas flow rates) remain constant while the gradual change occurs. The stored signals enable rounded corners, instead of sharp edges, to be etched, e.g., at an intersection of a trench wall and base. | 10-20-2011 |
20130048216 | CAPACITIVE CVD REACTOR AND METHODS FOR PLASMA CVD PROCESS - A decoupled capacitive CVD reactor is described, which provides improved CVD capabilities, including processing at lower temperatures, performing alternating deposition and etching steps, and performing in situ cleaning of the chamber, without the need for a remote plasma source. Two RF frequencies are coupled to the susceptor, while the anode is grounded. The high frequency RF source is operated so as to control the plasma density, while the low frequency RF source is operated to control species bombardment on the substrate, so as to control the properties of the film being deposited. Additionally, both RF sources may be controlled, together with selection of gasses supplied to the chamber, to operate the chamber either in deposition mode, partial etch mode, etching mode, or cleaning mode. | 02-28-2013 |
20130102155 | ICP SOURCE DESIGN FOR PLASMA UNIFORMITY AND EFFICIENCY ENHANCEMENT - An ICP A plasma reactor having an enclosure wherein at least part of the ceiling forms a dielectric window. A substrate support is positioned within the enclosure below the dielectric window. An RF power applicator is positioned above the dielectric window to radiate RF power through the dielectric window and into the enclosure. A plurality of gas injectors are distributed uniformly above the substrate support to supply processing gas into the enclosure. A circular baffle is situated inside the enclosure and positioned above the substrate support but below the plurality of gas injectors so as to redirect flow of the processing gas. | 04-25-2013 |
20130306240 | System and Method for Controlling Plasma With an Adjustable Coupling to Ground Circuit - A system and method for controlling plasma. The system includes a semiconductor chamber comprising a powered electrode, another electrode, and an adjustable coupling to ground circuit. The powered electrode is configured to receive a wafer or substrate. There is at least one grounded electrode configured to generate an electrical connection with the powered electrode. At least one of the grounded electrodes is electrically coupled to the adjustable coupling to ground circuit. The adjustable coupling to ground circuit is configured to modify the impedance of the grounded electrode. The ion energy of the plasma is controlled by the adjustable coupling to ground circuit. | 11-21-2013 |
Patent application number | Description | Published |
20140033149 | CAPTURING MUTUAL COUPLING EFFECTS BETWEEN AN INTEGRATED CIRCUIT CHIP AND CHIP PACKAGE - Systems and methods are provided for capturing mutual coupling effects between an integrated circuit chip and chip package using electronic design automation (EDA) tools. Specifically, a method is provided that is implemented in a computer infrastructure for designing an integrated circuit chip. The method includes compiling process technology parameters that describe electrical behavior for a chip-package coupling and a package of the integrated circuit chip. The method also includes generating a parasitic technology file to include the compiled process technology parameters. | 01-30-2014 |
20150371763 | NESTED-HELICAL TRANSFORMER - Some examples describe a first helical electromagnetic coil of a transformer. In some instances, at least a portion of the first helical electromagnetic coil is inside a first semi-conductive substrate. Further, in some examples, the first helical electromagnetic coil has a shape with an internal space. Further, some examples describe a second helical electromagnetic coil of the transformer. In some instances, at least a portion of the second helical electromagnetic coil is nested within the internal space of the first helical electromagnetic coil. Further, in some examples, the at least the portion of the second electromagnetic coil is inside the first semi-conductive substrate. | 12-24-2015 |
20150371764 | NESTED HELICAL INDUCTOR - Some examples describe a first helical structure of an electromagnetic inductor coil. In some examples, at least a portion of the first helical structure of the electromagnetic inductor coil is inside a first substrate. Further, some examples describe a second helical structure of the electromagnetic inductor coil. In some instances, at least a portion of the second helical structure is nested within the first helical structure of the electromagnetic inductor coil. Further, in some examples, the at least the portion of the second helical structure is inside the first substrate. | 12-24-2015 |
Patent application number | Description | Published |
20100057740 | ACCELERATING A QUIESCENCE PROCESS OF TRANSACTIONAL MEMORY - A method to perform validation of a read set of a transaction is presented. In one embodiment, the method compares a read signature of a transaction to a plurality of write signatures associated with a plurality of transactions. The method determines based on the result of comparison, whether to update a local value of the transaction to a commit value of another transaction from the plurality of the transactions. | 03-04-2010 |
20100058344 | ACCELERATING A QUIESCENCE PROCESS OF TRANSACTIONAL MEMORY - A method to perform validation of a read set of a transaction is presented. In one embodiment, the method compares a read signature of a transaction to a plurality of write signatures associated with a plurality of transactions. The method determines based on the result of comparison, whether to update a local value of the transaction to a commit value of another transaction from the plurality of the transactions. | 03-04-2010 |
20100153953 | UNIFIED OPTIMISTIC AND PESSIMISTIC CONCURRENCY CONTROL FOR A SOFTWARE TRANSACTIONAL MEMORY (STM) SYSTEM - A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled. | 06-17-2010 |
20110145512 | Mechanisms To Accelerate Transactions Using Buffered Stores - In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed. | 06-16-2011 |
20120159495 | NON-BLOCKING WAIT-FREE DATA-PARALLEL SCHEDULER - Methods, systems, and mediums are described for scheduling data parallel tasks onto multiple thread execution units of processing system. Embodiments of a lock-free queue structure and methods of operation are described to implement a method for scheduling fine-grained data-parallel tasks for execution in a computing system. The work of one of a plurality of worker threads is wait-free with respect to the other worker threads. Each node of the queue holds a reference to a task that may be concurrently performed by multiple thread execution units, but each on a different subset of data. Various embodiments relate to software-based scheduling of data-parallel tasks on a multi-threaded computing platform that does not perform such scheduling in hardware. Other embodiments are also described and claimed. | 06-21-2012 |
20120254497 | METHOD AND APPARATUS TO FACILITATE SHARED POINTERS IN A HETEROGENEOUS PLATFORM - A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified. | 10-04-2012 |
20120272210 | METHODS AND SYSTEMS FOR MAPPING A FUNCTION POINTER TO THE DEVICE CODE - Methods for mapping a function pointer to the device code are presented. In one embodiment, a method includes identifying a function which is executable by processing devices. The method includes generating codes including a first code corresponds to a first processing device and a second code corresponds to a second processing device. The second processing device is architecturally different from the first processing device. The method further includes storing the second code in a byte string such that the second code is retrievable if the function will be executed by the second processing device. | 10-25-2012 |
20130046924 | Mechanisms To Accelerate Transactions Using Buffered Stores - In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed. | 02-21-2013 |
20130046925 | Mechanisms To Accelerate Transactions Using Buffered Stores - In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed. | 02-21-2013 |
20130046947 | Mechanisms To Accelerate Transactions Using Buffered Stores - In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed. | 02-21-2013 |
20140071144 | METHOD AND APPARATUS TO FACILITATE SHARED POINTERS IN A HETEROGENEOUS PLATFORM - A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified. | 03-13-2014 |
20140156953 | Unified Optimistic and Pessimistic Concurrency Control for a Software Transactional Memory (STM) System - A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled. | 06-05-2014 |
20150134896 | MECHANISMS TO ACCELERATE TRANSACTIONS USING BUFFERED STORES - In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed. | 05-14-2015 |
20150186273 | METHOD AND APPARATUS TO FACILITATE SHARED POINTERS IN A HETEROGENEOUS PLATFORM - A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified. | 07-02-2015 |
Patent application number | Description | Published |
20140331489 | Method of Assembling a Modular LED Recessed Fixture - A method of assembling a modular LED recessed fixture has the steps of: building LED module, building LED driver device, assembling LED modules to main frame, and assembling LED driver device to main frame. Since LED module elements and LED driver device of the said fixture are replaceable, the fixture could be easily maintained or upgraded by changing the corresponding elements. | 11-13-2014 |
20140376218 | LED Strip Assembly for Generating an Extra Wide Beam of Light - The invention discloses an LED strip assembly for generating an extra wide beam light of greater than 180 degrees, comprising one linear support structure (typically of aluminum material), and at least two LED arrays. In addition, the support structure has an upper part, a lower part and two grooves in between. The said LED arrays are arranged on the upper part; the lower part is arc shaped and of 1 PI radians or less, having fins to dissipate heat to ambient environment. | 12-25-2014 |
20150008151 | Pin Protector for Light Bulbs - The invention discloses a pin protector for protecting pins of light bulbs from damage during transportation. The protector is made of plastic and includes a top having at least one recessed hole for inserting pins of light bulbs into, a bottom and a surrounding side structure. This particular feature mechanically protects the pins when there is an external force. | 01-08-2015 |
20150028759 | LED Lighting System Based on a Multiple-output Constant Current LED Driver - An LED lighting system includes a multiple output constant current LED driver and a plurality of LED arrays. The LED driver has AC/DC converter, PFC circuit, DC/DC converter and a plurality of DC/DC modules. The PFC circuit is connected to AC/DC converter, the DC/DC converter is connected to the PFC circuit, and the DC/DC modules are connected to DC/DC converter. The LED arrays are connected to DC/DC modules. | 01-29-2015 |
Patent application number | Description | Published |
20130302295 | FEEDER-FREE DERIVATION OF HUMAN-INDUCED PLURIPOTENT STEM CELLS WITH SYNTHETIC MESSENGER RNA - The present disclosure relates generally to novel methods and compositions for using engineered reprogramming factor(s) for the creation of induced pluripotent stem cells (iPSCs) through a kinetically controlled process. Specifically, this disclosure relates to establishing combinations of reprogramming factors, including fusions between conventional reprogramming factors with transactivation domains, optimized for reprogramming various types of cells. More specifically, the exemplary methods disclosed herein can be used for creating induced pluripotent stem cells from various mammalian cell types, including human fibroblasts. Exemplary methods of feeder-free derivation of human induced pluripotent stem cells using synthetic messenger RNA are also disclosed. | 11-14-2013 |
20140038267 | NOVEL MONOMERIC YELLOW-GREEN FLUORESCENT PROTEIN FROM CEPHALOCHORDATE - The present disclosure provides isolated nucleic acid sequences encoding a monomeric green/yellow fluorescent proteins, and fragments and derivatives thereof. Also provided is a method for engineering the nucleic acid sequence, a vector comprising the nucleic acid sequence, a host cell comprising the vector, and use of the vector in a method for expressing the nucleic acid sequence. The present invention further provides an isolated nucleic acid, or mimetic or complement thereof, that hybridizes under stringent conditions to the nucleic acid sequence. Additionally, the present invention provides a monomeric green/yellow fluorescent protein encoded by the nucleic acid sequence, as well as derivatives, fragments, and homologues thereof. Also provided is an antibody that specifically binds to the green/yellow fluorescent protein. | 02-06-2014 |
Patent application number | Description | Published |
20090131304 | Semi-Synthetic Desmethyl-Vancomycin-Based Glycopeptides With Antibiotic Activity - Semi-synthetic glycopeptides that have antibacterial activity are based on modifications of the desmethyl-vancomycin scaffold, in particular, acylation of the amino substituent on the amino-substituted sugar moiety on this scaffold with certain acyl groups; and/or conversion of the acid moiety on the macrocyclic ring of this scaffolds to certain substituted amides. In addition, compounds of the invention include desmethyl-vancomycin scaffolds on which the acid moiety on the macrocyclic ring is converted to certain substituted amides and the amino substituent on the amino-substituted sugar moiety is alkylated with certain alkyl groups. Also provided are methods for synthesis of the compounds, pharmaceutical compositions containing the compounds, and methods of use of the compounds for the treatment and/or prophylaxis of diseases, especially bacterial infections. | 05-21-2009 |
20090281100 | Benzimidazole quinolinones and uses thereof - Methods of inhibiting various enzymes and treating various conditions are provided that include administering to a subject a compound of Structure I or IB, a pharmaceutically acceptable salt thereof, a tautomer thereof, or a pharmaceutically acceptable salt of the tautomer. Compounds having the Structure I and IB have the following structures and have the variables described herein. Such compounds may be used to prepare medicaments for use in inhibiting various enzymes and for use in treating conditions mediated by such enzymes. | 11-12-2009 |
20090285849 | Thiosemicarbazones as anti-virals and immunopotentiators - Novel immune potentiators, novel vaccine adjuvants, novel compounds and pharmaceutical compositions, as well as novel methods for treating viral infections, including HCV, by administering the compounds and compositions, and novel methods for modulating the immune response by administering the compounds and/or compositions. | 11-19-2009 |
Patent application number | Description | Published |
20080214444 | SEMI-SYNTHETIC REARRANGED VANCOMYCIN/DESMETHYL-VANCOMYCIN-BASED GLYCOPEPTIDES WITH ANTIBIOTIC ACTIVITY - Semi-synthetic glycopeptides that have antibacterial activity are based on modifications of a rearranged vancomycin or desmethyl-vancomycin scaffold, in particular, alkylation or acylation of the amino substituent on the amino-substituted sugar moiety on this scaffold with certain acyl groups; and/or conversion of the acid moiety on the macrocyclic ring of this scaffolds to certain substituted amides. Also provided are methods for synthesis of the compounds, pharmaceutical compositions containing the compounds, and methods of use of the compounds for the treatment and/or prophylaxis of diseases, especially bacterial infections. | 09-04-2008 |
20090042858 | LACTAM CONTAINING HCV INHIBITORS - The present invention discloses novel methods and compositions for viral inhibition, particularly inhibition of HCV and SARS. The invention also provides compositions including novel oxoazepanylacetamide derivatives useful for viral inhibition. | 02-12-2009 |
20100048547 | PI 3-KINASE INHIBITORS AND METHODS OF THEIR USE - Phosphatidylinositol (PI) 3-kinase inhibitor compounds, their pharmaceutically acceptable salts, and prodrugs thereof; compositions of the new compounds, either alone or in combination with at least one additional therapeutic agent, with a pharmaceutically acceptable carrier; and uses of the new compounds, either alone or in combination with at least one additional therapeutic agent, in the prophylaxis or treatment of diseases characterized by the abnormal activity of growth factors, protein serine/threonine kinases, and phospholipid kinases, including proliferative diseases, inflammatory and obstructive airways diseases, allergic conditions, autoimmune and cardiovascular diseases. | 02-25-2010 |
20100075965 | PI3 KINASE INHIBITORS AND METHODS OF THEIR USE - Phosphatidylinositol (PI) 3 kinase inhibitor compounds, their pharmaceutically acceptable salts, and prodrugs thereof; compositions of the new compounds, either alone or in combination with at least one additional therapeutic agent, with a pharmaceutically acceptable carrier; and uses of the new compounds, either alone or in combination with at least one additional therapeutic agent, in the prophylaxis or treatment of proliferative diseases characterized by the abnormal activity of growth factors, protein serine/threonine kinases, phospholipid kinases, G-protein coupled receptors, and phosphatases. | 03-25-2010 |
20100249126 | PYRIMIDINE DERIVATIVES USED AS PI-3-KINASE INHIBITORS - Phosphatidylinositol (PI) 3-kinase inhibitor compounds (I), their pharmaceutically acceptable salts, and prodrugs thereof; compositions of the new compounds, either alone or in combination with at least one additional therapeutic agent, with a pharmaceutically acceptable carrier; and uses of the new compounds, either alone or in combination with at least one additional therapeutic agent, in the prophylaxis or treatment of proliferative diseases characterized by the abnormal activity of growth factors, protein serine/threonine kinases, and phospholipid kinases. | 09-30-2010 |