Patent application number | Description | Published |
20090052249 | SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY BLOCK CONFIGURATION - A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the analog and logic circuits and the pad band including power supply and data pads. The analog circuit is positioned close to the power supply pad, so that voltage drop due to the resistance of power supply interconnection is restricted. It is also possible to separate a charge pumping power supply interconnection and a peripheral circuit power supply interconnection in the vicinity of the power supply pad. | 02-26-2009 |
20090080252 | SEMICONDUCTOR MEMORY DEVICE - A multi-level semiconductor memory device for storing multi-level data having three or more values is implemented by utilizing a nonvolatile memory device for storing 2-valued data. Identification of successive 16-bit data externally applied is performed with external address bit AA [2], and a storage block is selected with external address bit AA [23]. Upper word data LW and lower word data UW are compressed into byte data of 8 bits, respectively, and stored in a memory cell array. | 03-26-2009 |
20090129149 | Nonvolatile semiconductor memory device for writing multivalued data - A memory cell of a memory array stores two bits. A memory array sense amplifier provides two bits in a verify operation. Two bits in a page buffer stores a write target value for the corresponding memory cell. Each bit in a mask buffer stores a value defining processing to be effected on the corresponding memory cell. A write driver applies a write pulse when the bit in the mask buffer corresponding to the selected memory cell is “0”. A verify circuit compares the two bits provided from the memory array sense amplifier with the corresponding two bits in the page buffer, and changes the corresponding bit in the mask buffer from “0” to “1” when the result of the comparison represents matching. | 05-21-2009 |
20110002170 | SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY BLOCK CONFIGURATION - A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the analog and logic circuits and the pad band including power supply and data pads. The analog circuit is positioned close to the power supply pad, so that voltage drop due to the resistance of power supply interconnection is restricted. It is also possible to separate a charge pumping power supply interconnection and a peripheral circuit power supply interconnection in the vicinity of the power supply pad. | 01-06-2011 |
20110261617 | SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY BLOCK CONFIGURATION - A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the analog and logic circuits and the pad band including power supply and data pads. The analog circuit is positioned close to the power supply pad, so that voltage drop due to the resistance of power supply interconnection is restricted. It is also possible to separate a charge pumping power supply interconnection and a peripheral circuit power supply interconnection in the vicinity of the power supply pad. | 10-27-2011 |
20120230107 | SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY BLOCK CONFIGURATION - A semiconductor device includes a semiconductor substrate having first and second edge lines, address pads along the first edge line, and memory mats, each including normal memory blocks and a spare memory block. Each normal memory block has nonvolatile memory cells and is a unit of batch erase. The memory mats are arranged in a U-shaped area having a hollow portion facing the second edge line. The device includes column decoders arranged correspondingly to the memory mats, an analog/logic circuit arranged in the hollow portion, and a power supply pad arranged between the analog/logic circuit and the second edge line. The analog/logic circuit includes a charge pump circuit. The device further includes a first power supply interconnection supplying power supply voltage to the charge pump circuit from the power supply pad, and a second power supply interconnection supplying power supply voltage to the column decoder from the power supply pad. | 09-13-2012 |
Patent application number | Description | Published |
20100051851 | IRON-BASED SOFT MAGNETIC POWDER FOR DUST CORE, METHOD FOR PRODUCING THE SAME AND DUST CORE - Disclosed herein is an iron powder for dust cores which effectively keeps insulation among iron powder particles and excels in mechanical strength even though the amount of insulating material is reduced to achieve high-density forming and which also exhibits good thermal stability necessary for electrical insulating properties even after heat treatment at high temperatures. | 03-04-2010 |
20100188179 | IRON-BASED SOFT MAGNETIC POWDER FOR DUST CORE AND DUST CORE - The invention relates to an iron-based soft magnetic powder for a dust core, wherein a film comprising Fe and Co, a phosphoric acid-based chemical conversion film and a silicone resin film are formed in this order on the surface of an iron-based soft magnetic powder, and to a dust core obtained by molding the iron-based soft magnetic powder for a dust core. The invention also relates to an iron-based soft magnetic powder for a dust core formed by coating the surface of an iron-based soft magnetic powder with an insulating film, wherein the powder has a particle diameter of from 45 μm to 180 μm, the insulating film is composed of two layers in which a lower layer composed of a phosphoric acid-based chemical conversion film and an upper layer composed of a silicone resin film, and each of the films has a thickness of from 100 nm to 280 nm, and to a dust core obtained by molding the iron-based soft magnetic powder for a dust core. | 07-29-2010 |
20120105190 | REACTOR - Provided is a reactor that enables high inductance to be generated with stability in a wide current range, while minimizing noise, processing cost, and eddy-current loss. The reactor (D | 05-03-2012 |
Patent application number | Description | Published |
20140153958 | SEALING ASSEMBLY, DEVELOPING DEVICE, PROCESS UNIT, AND IMAGE FORMING APPARATUS INCORPORATING SAME - A sealing assembly to contact a rotator includes a sealing member to slidably contact a surface of an end of the rotator in an axial direction of the rotator. The sealing member has an end in a circumferential direction thereof to contact the surface of the rotator with a first pressure. The end in the circumferential direction is fixed to a bearing surface formed on the opening on at least one of an upstream side and a downstream side in a rotation direction of the rotator. The sealing member has an intermediate portion between an upstream end and a downstream end in the circumferential direction to contact the surface of the rotator with a second pressure lower than the first pressure. | 06-05-2014 |
20140270861 | DEVELOPING DEVICE AND PROCESS UNIT AND IMAGE FORMING APPARATUS INCORPORATING SAME - A developing device includes a toner bearer including a surface in which multiple recesses having a cross-sectional void rate of 50% or smaller are formed, a toner supply member to supply toner to the toner bearer, and a developer regulator disposed facing or in contact with the toner bearer and including a bent tip portion. The toner bearer has a surface roughness Ra within a range from 1.0 μm to 2.0 μm, and a surface area ratio within a range from 2.0 to 4.0. The developing device uses polymerized toner having a weight average particle diameter of 8.0 μm or smaller and an average circularity of 0.98 or greater. | 09-18-2014 |
20150063865 | TONER CONTAINER, PROCESS CARTRIDGE, AND IMAGE FORMING APPARATUS - A toner container includes a substantially tetrahedral toner-containing portion having an openable edge to discharge toner contained in the toner-containing portion, and a reference fold along which the toner container is foldable after the openable edge is opened. The reference fold extends from the openable edge and is provided on medians of two triangular faces of the toner-containing portion adjoining each other along the openable edge. | 03-05-2015 |