Patent application number | Description | Published |
20140077832 | TEST AND CONNECTION APPARATUS ARRANGEMENT, AND CONNECTION APPARATUS - A testing arrangement is provided for testing the electrical circuits of an assembly of terminal blocks arranged in side-to-side relation, each of the terminal blocks including two mutually-insulated collinearly-arranged horizontal bus bar sections that are normally electrically connected by first and second pairs of leaf spring contacts arranged above and below the bus bar sections, respectively. During the testing operation, the testing device may be arranged either above or below the assembly, and an insulating test plug on the testing device is inserted either vertically downwardly from above, or upwardly from below, the terminal block, thereby to disengage one pair of contacts. A dummy plug is vertically inserted in the opposite direction to disengage the other pair of contacts. The remote ends of the bus bar sections are provided with clamping devices for connection with the bare ends of insulated conductors, respectively. | 03-20-2014 |
20140097855 | TEST AND CONNECTION APPARATUS ARRANGEMENT, AND TEST APPARATUS - A testing arrangement for testing the electrical circuits of a terminal block assembly, comprising a generally rectangular testing unit housing formed of insulating material and containing a chamber, at least one connection device mounted in chamber and having an elongated connector body formed of insulating material and including center and end portions. An integral measuring tab portion extends downwardly from the body center portion for insertion into a testing opening contained in the terminal block assembly, and a pair of coplanar measurement portions extend upwardly from the connector body ends and terminating at different elevations, thereby to afford a compact testing arrangement. Two electrical circuit connecting portions are mounted on the connector body, each including an input conductive contact plate mounted on one side of said measuring tab portion, and an output contact mounted within one of said measurement portions for connection with one end of a testing component. | 04-10-2014 |
20140148035 | TERMINAL BLOCK ASSEMBLY - A terminal block arrangement includes a plurality of generally rectangular terminal blocks having vertical parallel side walls, vertical end walls, and horizontal top and bottom walls, a connecting arrangement connecting said terminal blocks in contiguous side-by-side stacked relation, thereby to define a terminal block assembly in which at least portions of the terminal block top and bottom walls are exposed, and a fastening arrangement for fastening the bottom portion of the terminal block assembly to a fixed support. In a first embodiment, the fastening arrangement includes vertically displaceable end support members arranged at each end of the terminal block assembly, each support member having pairs of support feet arranged for connection with the fixed support. In a second embodiment, an adapter plate is secured to the fixed support, and the terminal block assembly is fastened to the adapter plate. | 05-29-2014 |
Patent application number | Description | Published |
20080255325 | Process for the Continuous Preparation and Isolation of Soluble Preceramic Oligomers and/or Polymers - The invention relates to a method for continuously producing pre-ceramic polymers. The inventive method consists in synthesising polymers, in separating polymers from a reaction mixture and in thermally conditioning for defining a cross linkage degree and Theological properties, wherein all said steps are integrated into a single method. The thus obtainable polymers are used in the form of an initial material for producing non-oxidised ceramics in ternary X/Y/N or X/Y/N/C quaternary systems. Said materials are characterized by the high mechanical, thermal and chemical resistance thereof, wherein any X and Y combination can represent in particular Si, B, P, Al, Ti, V, Zr, Ta elements. | 10-16-2008 |
20090030157 | Method for the Continuous Production of Mono-, Oligo- and/or Polyborosilazanes that Contain Carbon - The invention relates to a device and a method for producing mono-, oligo- and/or polyborosilazanes that contain carbon. According to said method (i) a one-component precursor compound is reacted with ammonia or an organic amino in an aminolysis step, (ii) a reaction mixture is extracted at least once from the aminolysis in a continuous extraction step using an organic solvent, (iii) ammonia or a phase containing organoamine that accumulates during the extraction process is discarded, recovered or at least partly recirculated and (iv) mono-, oligo- and/or polyborosilazanes containing carbon are obtained from the extraction phase containing the solvent. | 01-29-2009 |
Patent application number | Description | Published |
20100055902 | REDUCING CRITICAL DIMENSIONS OF VIAS AND CONTACTS ABOVE THE DEVICE LEVEL OF SEMICONDUCTOR DEVICES - Contact elements may be formed on the basis of a mask layer having openings, the width of which may be reduced by etching or deposition, thereby extending the process margins for a given lithography technique. Consequently, yield losses caused by short circuits in the contact level of sophisticated semiconductor devices may be reduced. | 03-04-2010 |
20100289083 | MULTI-STEP DEPOSITION OF A SPACER MATERIAL FOR REDUCING VOID FORMATION IN A DIELECTRIC MATERIAL OF A CONTACT LEVEL OF A SEMICONDUCTOR DEVICE - In advanced semiconductor devices, spacer elements may be formed on the basis of a multi-station deposition technique, wherein a certain degree of variability of the various sub-layers of the spacer materials, such as a different thickness, may be applied in order to enhance etch conditions during the subsequent anisotropic etch process. Consequently, spacer elements of improved shape may result in superior deposition conditions when using a stress-inducing dielectric material. Consequently, yield losses due to contact failures in densely packed device areas, such as static RAM areas, may be reduced. | 11-18-2010 |
20110073959 | STRESS ENGINEERING IN A CONTACT LEVEL OF SEMICONDUCTOR DEVICES BY STRESSED CONDUCTIVE LAYERS AND AN ISOLATION SPACER - In sophisticated semiconductor devices, strain-inducing materials having a reduced dielectric strength or having certain conductivity, such as metal nitride and the like, may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors. For this purpose, a strain-inducing material may be efficiently encapsulated on the basis of a dielectric layer stack that may be patterned prior to forming the actual interlayer dielectric material in order to mask sidewall surface areas on the basis of spacer elements. | 03-31-2011 |
20110104866 | ENHANCED ADHESION OF PECVD CARBON ON DIELECTRIC MATERIALS BY PROVIDING AN ADHESION INTERFACE - Amorphous carbon material may be deposited with superior adhesion on dielectric materials, such as TEOS based silicon oxide materials, in complex semiconductor devices by applying a plasma treatment, such as an argon treatment and/or forming a thin adhesion layer based on silicon dioxide, carbon-doped silicon dioxide, prior to depositing the carbon material. Consequently, the hard mask concept based on amorphous carbon may be applied with an increased degree of flexibility, since a superior adhesion may allow a higher degree of flexibility in selecting appropriate deposition parameters for the carbon material. | 05-05-2011 |