Przemek
Przemek Czerepinski, Wroclaw PL
Patent application number | Description | Published |
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20100050034 | SOFT BUTTER MEMORY CONFIGURATION IN A COMMUNICATION SYSTEM - In accordance with an embodiment of the present invention, an apparatus, comprising a processor configured to determine a total number of soft channel bits, a first number associated with hybrid automatic retransmit request processes and a second number associated with hybrid automatic retransmit request processes; and the processor further configured to select a size of a soft buffer memory partition based at least in part on the total number of soft channel bits, the first number associated with hybrid automatic retransmit request processes and the second number associated with hybrid automatic retransmit request processes, is disclosed. | 02-25-2010 |
Przemek Drochomirecki, Krakow PL
Patent application number | Description | Published |
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20140373063 | ENHANCED PROGRAM GUIDE - Systems and methods described herein relate to an enhanced program guide for programs that are broadcast according to a defined schedule. Program titles included in the guide can be ordered based on a relevance rank or score, potentially with no other parameter employed in determining a position of a program title within the guide. Presentation of the guide can be independent of a time axis or dimension and a channel axis or dimension. Titles can be displayed in a manner that is independent of a start time or running length of the associated program. | 12-18-2014 |
Przemek Guzy, Richmond Hill CA
Patent application number | Description | Published |
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20080216034 | Performance Visualization of Delay in Circuit Design - Methods are provided for presenting delay characteristics of a circuit design. The methods acquire routing delay data and logic delay data for each of a number of paths within the circuit design. In one method, a scatterplot of the routing delay data versus the logic delay data for each of the paths is generated and rendered. In another method, the paths are specified as being associated with modules within the circuit design. In this method, a histogram plot of the paths within each module is generated, wherein the paths within each module are identified as being dominated by routing delay or logic delay. In another embodiment, a connectivity diagram is generated to convey an amount of connectivity within modules and between modules. Each of the methods can be implemented as program instructions on a computer readable medium. | 09-04-2008 |
Przemek Guzy, Markham CA
Patent application number | Description | Published |
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20120110400 | Method and Apparatus for Performing Memory Interface Calibration - A universal memory interface on an integrated circuit includes an external memory interface unit operable to perform data rate conversion for a data signal between a first rate associated with the integrated circuit and a second rate associated with a memory system. The universal memory interface also includes a sequencer unit operable to calibrate at least one of a delay for the data signal and a delay for a strobe for the data signal by executing a calibration procedure instruction. | 05-03-2012 |
Przemek Struminski, Waterloo CA
Patent application number | Description | Published |
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20150026309 | SYSTEMS AND METHODS FOR ADAPTIVE STREAMING CONTROL - Systems and methods for adaptive streaming control include a network, a network device, and a plurality of media clients served by the network. The network device monitors media session conditions for a media session with a media client served by the network and enforces policy on the media session based on the media session conditions. The network device can enforce policy by determining a current estimated media quality of the media session based on the monitored media session conditions, determining a target media quality for the media session, and modifying the media session responsive to a difference between the current estimated media quality and the target media quality exceeding a threshold. | 01-22-2015 |