Lamb, NY
Craig R. Lamb, Penfield, NY US
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20110039572 | CELLULAR DEVICE CONTROL - A method of controlling a cellular device includes determining a velocity of the cellular device and temporarily disabling a short messaging service function of the cellular device in response to the velocity while a voice function of the cellular device remains enabled. | 02-17-2011 |
Curtis D. Lamb, Scottsville, NY US
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20090258264 | Cartridge adsorber system for removing hydrogen sulfide from reformate - A system for removal of H | 10-15-2009 |
James J. Lamb, Duanesburg, NY US
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20090062472 | NOVOLAK RESINS AND RUBBER COMPOSITIONS COMPRISING THE SAME - The present invention relates to novolak resins prepared with, inter alia, one or more alkylphenols. The invention further relates to compositions comprising the novolak resins, such as vulcanizable rubber compositions, and to products obtained therewith. | 03-05-2009 |
20150322193 | MODIFIED PHENOLIC RESINS AND METHODS OF MAKING AND USING THE SAME AS REINFORCING RESINS - This invention relates to processes for preparing novolak resins and using the same as reinforcing resins. One process comprises reacting one or more alkylphenols with an aldehyde in the presence of a base to form a resole resin, wherein for each mole of alkylphenol at least 1.5 moles of aldehyde are reacted; and reacting the resole resin with one or more phenolic compounds in the presence of an acidic catalyst to form a novolac resin, wherein for each mole of alkylphenol at least 1.5 moles of the phenolic compounds are reacted. Another process comprises reacting one or more alkylphenols with an aldehyde in the presence of a base to form a resole resin, and reacting the resole resin with one or more phenolic compounds under an elevated temperature to form a novolac resin. | 11-12-2015 |
John P. Lamb, White Plains, NY US
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20160034659 | ANALYZING DATA FROM A SENSOR-ENABLED DEVICE - An approach for analyzing data collected by a sensor-enabled device over a network is provided. Specifically, in a typical embodiment, a set of usage data will be received from a device over a network. The set of usage data may be collected via at least one sensor integrated with the device, and the set of usage data may pertain to use of the device by a user. Regardless, the set of usage data will be compared to a set of diagnostic information stored in at least one computer storage device. The set of diagnostic information typically pertains to a condition (e.g., medical) treated by use of the device (e.g., dental, cardiac, renal, etc.). Based on the comparison, at least one determination (e.g., diagnosis, treatment plan, level of compliance with applicable standards, etc.) will be made and a set of reports will be generated based thereon. | 02-04-2016 |
John P. Lamb, White Plaines, NY US
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20130282695 | ANALYZING DATA FROM A SENSOR-ENABLED DEVICE - An approach for analyzing data collected by a sensor-enabled device over a network is provided. Specifically, in a typical embodiment, a set of usage data will be received from a device over a network. The set of usage data may be collected via at least one sensor integrated with the device, and the set of usage data may pertain to use of the device by a user. Regardless, the set of usage data will be compared to a set of diagnostic information stored in at least one computer storage device. The set of diagnostic information typically pertains to a condition (e.g., medical) treated by use of the device (e.g., dental, cardiac, renal, etc.). Based on the comparison, at least one determination (e.g., diagnosis, treatment plan, level of compliance with applicable standards, etc.) will be made and a set of reports will be generated based thereon. | 10-24-2013 |
Kirk D. Lamb, Poughkeepsie, NY US
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20150317248 | SIZING A WRITE CACHE BUFFER BASED ON EMERGENCY DATA SAVE PARAMETERS - Embodiments relate to saving data upon loss of power. An aspect includes sizing a write cache buffer based on parameters related to carrying out this emergency data save procedure. A computer implemented method for allocating a write cache on a storage controller includes retrieving, at run-time by a processor, one or more operating parameters of a component used in a power-loss save of the write cache. The component is selected from the group consisting of an energy storage element, a non-volatile memory, and a transfer logic. A size for the write cache on the storage controller is determined, based on the one or more operating parameters. A write cache, of the determined size, is allocated from a volatile memory coupled to the storage controller. | 11-05-2015 |
Kirk D. Lamb, Kingston, NY US
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20080235444 | SYSTEM AND METHOD FOR PROVIDING SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (SDRAM) MODE REGISTER SHADOWING IN A MEMORY SYSTEM - A system and method for providing SDRAM mode register shadowing in a memory system. A system includes a memory interface device adapted for use in a memory system. The memory interface device includes an interface to one or more ranks of memory devices, and each memory device includes one or more types of mode registers. The memory interface device also includes an interface to a memory bus for receiving commands from a memory controller. The commands include a mode register set command specifying a new mode register setting for one or more ranks of memory devices and a mode register type. The memory interface device further includes a mode register shadow module to capture settings applied to the mode registers. The module includes a shadow register for each type of mode register and a shadow log for each type of mode register. The module also includes mode register shadow logic to detect a mode register set command, to store the new mode register setting in the shadow register corresponding to the specified mode register type, and to set one or more bits in the shadow log corresponding to the specified mode register type to indicate which of the ranks of memory devices have been programmed with the new mode register setting. | 09-25-2008 |
20080307374 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR MAPPING A LOGICAL DESIGN ONTO AN INTEGRATED CIRCUIT WITH SLACK APPORTIONMENT - A logical design including multiple logical blocks is mapped onto an integrated circuit chip. A chip level floor plan is created on the chip, including temporary areas on the chip set aside for accommodating logical blocks having logical content including timing requirements based on the logical design. The temporary areas are translated into physical cells on the chip with pins assigned for inputs and outputs for the logical blocks. The logical blocks are mapped to the physical cells on the chip in a time sensitive manner using timing assertions to form temporary logical partitions. Blocks on the chip, including the temporary logical partitions, are connected based on the timing assertions. A timing analysis is performed on the chip to determine timing slack associated with each temporary logical partition. A determination is made whether the timing slack is acceptable. If the timing slack is not acceptable, the slack is apportioned for, and apportioned slack information is fed back in the form of timing assertions. Mapping, connecting, performing a timing analysis, and apportioning for slack are repeated until the timing slack associated with each temporary logical partition is determined to be acceptable. | 12-11-2008 |
Kirk David Lamb, Kingston, NY US
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20090249174 | Fault Tolerant Self-Correcting Non-Glitching Low Power Circuit for Static and Dynamic Data Storage - In a computer system in which personalization data for an ASIC is stored in latches, this data is susceptible to soft errors. Many computer systems require high levels of error detection, error correction, fault isolation, fault tolerance, and self-healing. In order to complete an ASIC design and release it to a foundry, it must first be verified that the design meets the frequency requirements of its specification. A fault tolerant, self-correcting, non-glitching, low power circuit is described which meets all the requirements for reliability, while also eliminating any requirement to add area or power to the ASIC in order to meet the frequency specification for personalization latches. By using the circuits as a repeatable structure, the verification of the self-healing property is simplified relative to a collection of Error Correction Code usages of various bit widths. | 10-01-2009 |
20090322376 | SMI MEMORY READ DATA CAPTURE MARGIN CHARACTERIZATION CIRCUITS AND METHODS - The present invention is directed to margin characterization of memory devices, such as interface ASICs connected to SDRAM. The circuits and method perform margin characterization on a chip during wafer test; however the characterization could also be performed at module test or in a system. | 12-31-2009 |
20110145771 | Modeling for Soft Error Specification - Soft error modeling of circuits. Soft error upset (SEU) specification and design information is received from a design entry. The SEU specification comprises expected SEU behavior of a node. A logical simulation model is created based on the SEU specification and the design information. A logical verification is performed based on the logical simulation model to produce a first result. The logical verification comprises selecting a first node for injection, injecting an SEU into the first node to produce a first result, and responsive to the first result not agreeing with the SEU specification, providing the first result to the design entry. A netlist based on the SEU specification and the design information is created. The netlist comprises a specification-based-logic-derating derived from the SEU specification. A physical design verification based on the netlist, a logic derating, and clock information is performed. It comprises calculating node failure-in-time based on the specification-based-logic-derating. | 06-16-2011 |
Michael Arthur Lamb, New Paltz, NY US
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20080250134 | Architecture for a Centralized Management System - An example of a solution provided here comprises: providing a logical design, including at least one hub containing central management tools, and a plurality of lower tiers containing local management tools; placing components according to the design; and providing, from the hub, one or more management functions. The lower tiers include one or more elements chosen from RIM's, spokes, and POD's. | 10-09-2008 |