Patent application number | Description | Published |
20090302954 | Temperature Compensation Circuit and Method - Disclosed are various embodiments of temperature-compensated relaxation oscillator circuits that may be fabricated using conventional CMOS manufacturing techniques. The relaxation oscillator circuits described herein exhibit superior low temperature coefficient performance characteristics, and do not require the use of expensive off-chip high precision resistors to effect temperature compensation. Positive and negative temperature coefficient resistors arranged in a resistor array offset one another to provide temperature compensation in the relaxation oscillator circuit. | 12-10-2009 |
20120056672 | Class-AB/B amplifier and quiescent control circuit for implementation with same - Disclosed is a Class-AB/B amplifier comprising a first output stage including a first plurality of amplification devices and a second output stage including a second plurality of amplification devices. According to one embodiment, the first output stage operates when the Class-AB/B amplifier is in a quiescent state and the second output stage operates when the Class-AB/B amplifier is in an active state. The Class-AB/B amplifier also comprises a level shifting circuit that adjusts a control voltage of the second output stage, where the level shifting circuit is adapted to activate the second output stage when the Class-AB/B amplifier enters the active state. Embodiments of the Class-AB/B amplifier may include a level shifting circuit that implements either a fixed or signal-dependent level shift, and a quiescent control circuit that substantially eliminates any systematic offset arising from the active feedback circuit inside the replica bias circuit. | 03-08-2012 |
20130063214 | Quiescent Control Circuit for Providing Control Current for an Amplifier - Disclosed is a Class-AB/B amplifier comprising a first output stage including a first plurality of amplification devices and a second output stage including a second plurality of amplification devices. According to one embodiment, the first output stage operates when the Class-AB/B amplifier is in a quiescent state and the second output stage operates when the Class-AB/B amplifier is in an active state. The Class-AB/B amplifier also comprises a level shifting circuit that adjusts a control voltage of the second output stage, where the level shifting circuit is adapted to activate the second output stage when the Class-AB/B amplifier enters the active state. Embodiments of the Class-AB/B amplifier may include a level shifting circuit that implements either a fixed or signal-dependent level shift, and a quiescent control circuit that substantially eliminates any systematic offset arising from the active feedback circuit inside the replica bias circuit. | 03-14-2013 |
20130064398 | Class-AB/B amplifier with quiescent control circuit - Disclosed is a Class-AB/B amplifier comprising a first output stage including a first plurality of amplification devices and a second output stage including a second plurality of amplification devices. According to one embodiment, the first output stage operates when the Class-AB/B amplifier is in a quiescent state and the second output stage operates when the Class-AB/B amplifier is in an active state. The Class-AB/B amplifier also comprises a level shifting circuit that adjusts a control voltage of the second output stage, where the level shifting circuit is adapted to activate the second output stage when the Class-AB/B amplifier enters the active state. Embodiments of the Class-AB/B amplifier may include a level shifting circuit that implements either a fixed or signal-dependent level shift, and a quiescent control circuit that substantially eliminates any systematic offset arising from the active feedback circuit inside the replica bias circuit. | 03-14-2013 |
20140254779 | Integrated CMOS Multi-mode Drivers - A multi-mode line driver circuit designed to be fabricated in a CMOS process and capable of supporting a plurality of operating modes corresponding, for example, to different profiles of communication standards such as xDSL standards. The line driver circuit incorporates integrated mode switches with a two-stage amplifier architecture to relax amplifier requirements by distributing the signal gain into two amplifier stages. Reconfigurable feedback loops are provided to permit design optimization for particular modes of operation (e.g., ADSL and VDSL compliant modes). In one embodiment implemented as a Class-H amplifier, lift amplifier(s) are provided between a first amplifier stage and a second amplifier stage for controlling voltage supply levels of the second amplifier stage. The lift amplifiers may be enabled by voltage threshold detection circuitry that monitors either the input or the output signals of the first amplifier stage depending on the operable transmission mode. | 09-11-2014 |
Patent application number | Description | Published |
20100094309 | Automated Intraocular Lens Injector Device - An intraocular lens injection device comprises a tubular housing with a plunger longitudinally disposed within the tubular housing. An electric drive system longitudinally translates the plunger so that its tip engages an insertion cartridge to fold and displace an intraocular lens disposed within and to inject the folded lens into the lens capsule of an eye. A control circuit is configured to start translation of the plunger, responsive to user input, to detect at least one fault condition based on a counter-electromotive force produced by the electric motor, and to stop translation of the plunger assembly responsive to the detected fault condition, which may comprise excessive resistance to forward or rearward translation of the plunger or insufficient resistance to forward translation of the plunger. | 04-15-2010 |
20110172676 | PLUNGER TIP COUPLING DEVICE FOR INTRAOCULAR LENS INJECTOR - The present disclosure is directed to devices, systems, and methods directed to mounting a plunger tip to a plunger of an IOL injection device. A plunger tip wrench that is operable to releasably retain a plunger tip may be coupled to a holder extending from an end of the IOL injection device to align the plunger tip with the plunger of the IOL injection device. In some instances, the IOL injection device may include a motor and use a back electromotive force (EMF) of the motor to detect a position of the plunger as it is extended to engage the plunger tip. The plunger tip may be positioned relative to the plunger such that the plunger will engage the plunger tip within the entire range of a negative error position and a positive error position. | 07-14-2011 |
20110257658 | Modular Intraocular Lens Injector Device - An intraocular lens (IOL) injection device is modularized to enable cleaning of internal components after surgery. The device includes first and second housing modules. These modules collectively define a passageway along which an injector rod moves between a retracted position and an extended position. The first module is further configured to accommodate a lens cartridge module. The cartridge module has disposed therein an IOL, in alignment with the passageway. Thus as the rod moves from the retracted position to the extended position, a front portion of the rod that is substantially surrounded by the first module in the retracted position moves into the cartridge module and displaces the IOL. This causes the front portion of the rod to accumulate on it viscoelastic substances. The first module, though, is configured to detach from the second module, to thereby expose the front portion of the rod in the retracted position for cleaning. | 10-20-2011 |
20130197531 | AUTOMATED INTRAOCULAR LENS INJECTOR DEVICE - An intraocular lens injection device comprises a tubular housing with a plunger longitudinally disposed within the tubular housing. An electric drive system longitudinally translates the plunger so that its tip engages an insertion cartridge to fold and displace an intraocular lens disposed within and to inject the folded lens into the lens capsule of an eye. A control circuit is configured to start translation of the plunger, responsive to user input, to detect at least one fault condition based on a counter-electromotive force produced by the electric motor, and to stop translation of the plunger assembly responsive to the detected fault condition, which may comprise excessive resistance to forward or rearward translation of the plunger or insufficient resistance to forward translation of the plunger. | 08-01-2013 |
20130197532 | AUTOMATED INTRAOCULAR LENS INJECTOR DEVICE - An intraocular lens injection device comprises a tubular housing with a plunger longitudinally disposed within the tubular housing. An electric drive system longitudinally translates the plunger so that its tip engages an insertion cartridge to fold and displace an intraocular lens disposed within and to inject the folded lens into the lens capsule of an eye. A control circuit is configured to start translation of the plunger, responsive to user input, to detect at least one fault condition based on a counter-electromotive force produced by the electric motor, and to stop translation of the plunger assembly responsive to the detected fault condition, which may comprise excessive resistance to forward or rearward translation of the plunger or insufficient resistance to forward translation of the plunger. | 08-01-2013 |
20140200590 | PLUNGER TIP COUPLING DEVICE FOR INTRAOCULAR LENS INJECTOR - The present disclosure is directed to devices, systems, and methods directed to mounting a plunger tip to a plunger of an IOL injection device. A plunger tip wrench that is operable to releasably retain a plunger tip may be coupled to a holder extending from an end of the IOL injection device to align the plunger tip with the plunger of the IOL injection device. In some instances, the IOL injection device may include a motor and use a back electromotive force (EMF) of the motor to detect a position of the plunger as it is extended to engage the plunger tip. The plunger tip may be positioned relative to the plunger such that the plunger will engage the plunger tip within the entire range of a negative error position and a positive error position. | 07-17-2014 |
Patent application number | Description | Published |
20120082272 | SELECTABLE INTERFERENCE CANCELLATION IN A COMMUNICATIONS RECEIVER - Method and apparatuses are disclosed to substantially compensate for various unwanted interferences and/or distortions within a communications receiver. Each of these apparatuses and methods estimate the various unwanted interferences and/or distortions within the communications receiver. Each of these apparatuses and methods remove the estimates of the various unwanted interferences and/or distortions within the communications receiver from one or more communications signals within the communications receiver to substantially compensate for the various unwanted interferences and/or distortions. | 04-05-2012 |
20120082276 | COMPENSATING FOR UNWANTED INTERFERENCE IN A COMMUNICATIONS RECEIVER - Method and apparatuses are disclosed to substantially compensate for various unwanted interferences and/or distortions within a communications receiver. Each of these apparatuses and methods estimate the various unwanted interferences and/or distortions within the communications receiver. Each of these apparatuses and methods remove the estimates of the various unwanted interferences and/or distortions within the communications receiver from one or more communications signals within the communications receiver to substantially compensate for the various unwanted interferences and/or distortions. | 04-05-2012 |
20120082277 | CONFIGURABLE ADAPTIVE FILTER - Method and apparatuses are disclosed to substantially compensate for various unwanted interferences and/or distortions within a communications receiver. Each of these apparatuses and methods estimate the various unwanted interferences and/or distortions within the communications receiver. Each of these apparatuses and methods remove the estimates of the various unwanted interferences and/or distortions within the communications receiver from one or more communications signals within the communications receiver to substantially compensate for the various unwanted interferences and/or distortions. | 04-05-2012 |
20120082278 | COMPENSATING FOR UNWANTED INTERFERENCE IN A COMMUNICATIONS RECEIVER - Method and apparatuses are disclosed to substantially compensate for various unwanted interferences and/or distortions within a communications receiver. Each of these apparatuses and methods estimate the various unwanted interferences and/or distortions within the communications receiver. Each of these apparatuses and methods remove the estimates of the various unwanted interferences and/or distortions within the communications receiver from one or more communications signals within the communications receiver to substantially compensate for the various unwanted interferences and/or distortions. | 04-05-2012 |
20120083235 | COMPENSATING FOR UNWANTED DISTORTION IN A COMMUNICATIONS RECEIVER - Method and apparatuses are disclosed to substantially compensate for various unwanted interferences and/or distortions within a communications receiver. Each of these apparatuses and methods estimate the various unwanted interferences and/or distortions within the communications receiver. Each of these apparatuses and methods remove the estimates of the various unwanted interferences and/or distortions within the communications receiver from one or more communications signals within the communications receiver to substantially compensate for the various unwanted interferences and/or distortions. | 04-05-2012 |
20140062738 | SUCCESSIVE EQUALIZER FOR ANALOG-TO-DIGITAL CONVERTER (ADC) ERROR CORRECTION - Various pipeline ADCs are disclosed that substantially compensate for interference or distortion that results from imperfections with various ADC modules of the pipeline ADCs. The pipeline ADCs include various ADC stages and various compensation stages that are coupled to the various ADC stages. The various ADC stages convert their corresponding analog inputs from an analog signal domain to a digital signal domain to provide various digital output signals and various analog residual signals to subsequent ADC stages. The various compensation stages compensate for interference or distortion that is impressed onto the various analog residual signals which results from imperfections within previous ADC stages. | 03-06-2014 |
20140369451 | DIRECT SAMPLING RECEIVER WITH CONTINUOUS-TIME MDAC - Methods and apparatuses are described for a direct sampling receiver having high dynamic range and low noise figure with a continuous-time (CT) multiplying digital-to-analog converter (MDAC) architecture. In a multipath architecture, the input signal is sampled in the quantizer path, but not the CT signal path. In the CT signal path, only a filtered residue signal is sampled. Coarse bits generated in the quantizer path and fine bits generated in the input signal path are digitally combined to reconstruct the analog input signal in the digital domain. Filtering, aperture error control and digital equalization remove sources of errors, resulting in high performance. Advantages include toleration of multiple blocker signals, simultaneous reception of multiple weak channels and/or strong and weak channels, operation with simplified gain control and reduced pre-amplification as well as operation without excessive power consumption, external filters and tunable local oscillator (LO). | 12-18-2014 |
Patent application number | Description | Published |
20080244246 | INTEGRATED MPE-FEC RAM FOR DVB-H RECEIVERS - A MPE-FEC memory chip and method for use in a DVB-H receiver, wherein the memory chip comprises a TS demux; a RS decoder; a system bus; and a RAM unit adapted to simultaneously interface to the TS demux, the RS decoder, and the system bus through time-multiplexing, wherein the RAM unit is adapted to (i) access multiple-words per clock cycle, and (ii) cache write and read accesses to reduce memory access from the TS demux and the system bus, and wherein the RAM unit is adapted to be clocked at a speed higher than an interfacing data-path to increase an effective throughput of the RAM unit. The RAM unit may comprise multiple RAM sub units, wherein while a first RAM sub unit is clock gated, the remaining multiple RAM sub units are accessible. | 10-02-2008 |
20080298394 | COMPACT MPE-FEC ERASURE LOCATION CACHE MEMORY FOR DVB-H RECEIVER - Location cache memory architectures that only require 32 Kbits or less per frame to store erasure information with simple address mapping to the main MPE-FEC RAM for easy column-wise and row-wise access. Alternative architectures are designed to greatly reduce the size and logic complexity of the MPE-FEC erasure cache memory. Two architectures reduce the erasure cache size down to 32 Kbits and 28 Kbits, correspondingly, without introducing additional erasure locations, while another architecture further reduces the required memory size down to 16K, 8K, 4K, or 2K bits with a slight increase in the total erasure locations. All architectures group the data in MPE-FEC frame memory into blocks of 2 | 12-04-2008 |
20090296843 | SEGMENTED-FRAME SYNCHRONIZATION FOR ISDB-T AND ISDB-TSB RECEIVER - A technique for segmented frame synchronization for Integrated Services Digital Broadcasting-Terrestrial (ISDB-T) and Integrated Services Digital Broadcasting-Terrestrial Sound Broadcasting (ISDB-TSB) systems, wherein the method comprises receiving a wireless digital signal comprising an Orthogonal Frequency Division Multiplexing (OFDM) frame, further comprising ODFM symbols, in a receiver and wherein the receiver comprises a time de-interleaver, a bit de-interleaver, and a descrambler; filling memory of time de-interleaver and bit de-interleaver by the received wireless digital signal; determining an OFDM segmented frame boundary when memory of the time de-interleaver and bit de-interleaver are full; decoding bits from time de-interleaver and bit de-interleaver using a Viterbi decoder; outputting the Viterbi decoding bits from time de-interleaver and bit de-interleaver when the OFDM segmented frame boundary is detected; obtaining a segmented multiplexing frame boundary upon receipt of the first bit from the Viterbi decoder; and synchronizing the OFDM frame based on the segmented multiplexing frame boundary. | 12-03-2009 |
20090300470 | MEMORY ARCHITECTURE FOR HIGH THROUGHPUT RS DECODING FOR MEDIAFLO RECEIVERS - A system and method for increasing the throughput of a RS decoder in MediaFLO™ receivers. A MAC de-interleaver RAM architecture allowing operation of parallel RS decoders comprises of four equal portioned memory banks, a codeword buffer for data correction, and a higher bit width RAM. The method of increasing throughput of RS decoder by minimizing RAM access and clock frequency includes increasing the bit width of the de-interleaver RAM, using parallel RS decoder cores for decoding received data, partitioning a 4-bank RAM and ECB allocation scheme, and correcting the data using intermediate buffers. The architecture enables on-chip implementation of the MAC de-interleaver RAM and RS decoders with reduced power consumption and provide higher RS decoder throughput. | 12-03-2009 |
20120063553 | Low Power, Multi-Chip Diversity Architecture - A multi-chip antenna diversity architecture includes a first receiver chip including a first tuner, and a first demodulator directly connected to the tuner. The first demodulator demodulates the first input signal received from the first tuner. A first power sequencer that controls the first receiver chip, and a first chip ID including a voltage source V | 03-15-2012 |
20120081608 | Multi-Chip Antenna Diversity Picture-in-Picture Architecture - A multi-chip antenna diversity architecture and method includes a first receiver chip that receives a first input signal from a first antenna. The first receiver chip includes a first tuner that amplifies the first input signal, a crystal operatively connected to a first crystal oscillator circuit, and a first crystal oscillator clock buffer that receives a clock signal from the first crystal oscillator circuit. A first demodulator demodulates the input signal received from the first tuner. A second receiver chip receives a second input signal from a second antenna. The second receiver chip includes a second crystal oscillator circuit, a second crystal oscillator clock buffer, a second tuner, and a second demodulator that receives diversity data from the first demodulator. The first crystal oscillator clock buffer drives the clock signal to the second crystal oscillator clock buffer, the second tuner, and the second demodulator of the second receiver chip. | 04-05-2012 |
Patent application number | Description | Published |
20080212665 | System for monitoring the quality of a communications channel with mirror receivers - A system is presented that monitors the quality of a communications channel with mirror receivers. A first receiver and a second receiver, coupled in parallel with the first receiver, receive a data signal transmitted over the communications channel. The second receiver generates an output signal. A signal integrity (SI) processor manipulates the output signal in order to determine the quality of the communications channel. The SI processor samples a phase-shifted version of the output signal, which has a phase shifted relative to a zero reference phase, and analyzes the phase-shifted version of the output signal for bit errors. In an embodiment, the SI processor manipulates the output signal to extract an eye diagram indicative of the quality of the communications channel. The SI processor non-intrusively determines the quality of the communications channel using the second receiver. | 09-04-2008 |
20100014573 | SEARCH ENGINE FOR A RECEIVE EQUALIZER - A search engine selects initial coefficients for a receive equalizer. The search engine may be incorporated into a communication receiver that includes a decision feedback equalizer and clock and data recovery circuit. Here, the search engine may initialize various adaptation loops that may control the operation of, for example, a decision feedback equalizer, a clock and data recovery circuit and a continuous time filter. The receiver may include an analog-to-digital converter that is used to generate soft decision data for some of the adaptation loops. | 01-21-2010 |
20100241925 | Forward Error Correction (FEC) scheme for communications - Forward error correction (FEC) scheme for communications. Appropriate selection/arrangement of bits of an information bit sequence undergo one or more types of subsequent encoding to generate a coded bit sequence that may subsequently undergo appropriate processing to generate a continuous time signal to be launched within a communication channel. In some embodiments, an information bit sequence, after being partitioning into a number of information bit groups, initially undergoes a first encoding within a first encoding module thereby generating a number of redundancy/parity bit groups (e.g., e.g., each redundancy/parity bit group corresponding to one of the information bit groups). Then, after performing any desired and appropriate selection/arrangement of bits within the redundancy/parity bit groups and the information bit groups, second encoding within a second encoding module is performed thereon to generate additional redundancy/parity bits. In addition, interleaving may be performing at various stages of the encoding processing. | 09-23-2010 |
20100241926 | Communication device employing binary product coding with selective additional Cyclic Redundancy Check (CRC) therein - Communication device employing binary product coding with selective additional cyclic redundancy check (CRC) therein. Product code encoding (e.g., employing row and column encoding of matrix formatted bits, selectively with interleaving and/or permutation of the bits therein) may be combined with additional error correction code (ECC) or forward error correction (FEC) coding thereby generating coded bits for use in generating a signal to be launched into a communication channel. Various ECCs/FECs may be employed including a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code, a Reed-Solomon (RS) code, an LDPC (Low Density Parity Check) code, etc. The redundancy of such coded signals as generated using the principles herein is in the range of approximately 7%, and hard decision decoding may be performed on such coded signals generated herein. In accordance with decoding such signals, various bit decisions (within certain iterations) may be selectively ignored and/or reverted back to previous bit decisions. | 09-23-2010 |
20110052216 | Electronic dispersion compensation within optical communications using reconstruction - Electronic dispersion compensation within optical communications using reconstruction. Within a communication system that includes any optical network portion, segment, or communication link, etc., that optical component/portion of the communication system is emulated within the electronic domain. For example, in a communication device having receiver functionality, deficiencies that may be incurred by the at least one optical portion of the communication system are compensated in the electronic domain of the communication device having the receiver functionality by employing reconstruction logic and/or circuitry therein. Multiple decision feedback equalizers (DFE) circuitries, implemented in the electronic domain, may be employed to provide feedback from different portions of the receiver functionality in accordance with performing compensation of optical incurred deficiencies (e.g., dispersion, non-linearity, inter-symbol interference (ISI), etc.). Within a communication device's receiver portion, equalization and compensation is performed in the electronic domain as adapted for high speed applications and higher order modulation schemes. | 03-03-2011 |
20120002713 | MULTI-PROTOCOL COMMUNICATIONS RECEIVER WITH SHARED ANALOG FRONT-END - According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol. | 01-05-2012 |
20120007640 | Multi-Channel Multi-Protocol Transceiver With Independent Channel Configuration Using Single Frequency Reference Clock Source - A circuit for producing one of a plurality of output clock frequencies from a single, constant input reference clock frequency. The circuit comprises a reference clock system and a phase lock loop. The reference clock system includes a bypass path, a divider path including a first integer divider, and a multiplexer. A divisor of the first integer divider is based on a selected communications protocol of a group of possible communications protocols. The multiplexer is configured to route the bypass path or the divider path based on the selected communications protocol. The phase lock loop includes a voltage controlled oscillator and a feedback path. The feedback path includes a second integer divider. A divisor of the second integer divider is based on the selected communications protocol. The reference clock system is configured to receive a constant reference clock frequency. The voltage controlled oscillator is configured to produce one of a plurality of output clock frequencies corresponding to the selected communications protocol. The selected output clock frequency is produced based on at least one of the routing of the multiplexer, the divisor of the first integer divider, and the divisor of the second integer divider. | 01-12-2012 |
20120179949 | METHOD AND SYSTEM FOR ENCODING FOR 100G-KR NETWORKING - In one embodiment, a coding method that uses certain forward error correcting codes based on a given transcoding method and delivers the codes according to burst interleaving. | 07-12-2012 |
20120219005 | AGGREGATING COMMUNICATION CHANNELS - Techniques, systems and apparatus are described for implementing an inter-channel ring interface in a communication device. A communication device can include communication channels to carry data at respective first data throughputs. An inter-channel ring interface connects at least some of the communication channels in a ring configuration to form an aggregated group of channels that operates as a single channel at a second data throughput. | 08-30-2012 |
20130243072 | MULTI-PROTOCOL COMMUNICATIONS RECEIVER WITH SHARED ANALOG FRONT-END - According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol. | 09-19-2013 |
20140053042 | Communication device employing binary product coding with selective additional Cyclic Redundancy Check (CRC) therein - Communication device employing binary product coding with selective additional cyclic redundancy check (CRC) therein. Product code encoding (e.g., employing row and column encoding of matrix formatted bits, selectively with interleaving and/or permutation of the bits therein) may be combined with additional error correction code (ECC) or forward error correction (FEC) coding thereby generating coded bits for use in generating a signal to be launched into a communication channel Various ECCs/FECs may be employed including a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code, a Reed-Solomon (RS) code, an LDPC (Low Density Parity Check) code, etc. The redundancy of such coded signals as generated using the principles herein is in the range of approximately 7%, and hard decision decoding may be performed on such coded signals generated herein. In accordance with decoding such signals, various bit decisions (within certain iterations) may be selectively ignored and/or reverted back to previous bit decisions. | 02-20-2014 |
20140122976 | METHOD AND APPARATUS FOR UMBRELLA CODING - A communication system and a method are disclosed. The communication system includes an encoder configured to encode source data and output an encoded frame including a mother code or a plurality of concatenated daughter codes based on an encoding option. The mother code and the plurality of concatenated daughter codes have a same number of coded data symbols. The mother code includes a first source number of source symbols and a first parity number of parity symbols. The daughter code includes fewer source symbols and fewer parity symbols than the mother code. | 05-01-2014 |
20140173384 | METHOD AND SYSTEM FOR ENCODING FOR 100G-KR NETWORKING - Aspects of a method and system for encoding in 100G-KR networking are described. In one example embodiment, a coding method uses certain forward error correcting codes based on a given transcoding method and delivers the codes according to burst interleaving. In another example, a coding method includes receiving source data from a plurality of physical lanes, combining data from the physical lanes to generate a block, transcoding the block, and encoding a data stream including the transcoded block. | 06-19-2014 |
Patent application number | Description | Published |
20110194981 | OZONE DEVICE FOR DEODORIZING DRESSES - An ozone device for deodorizing dresses within a closet, includes an ozone generator. The ozone generator includes a casing formed with first and second ventilation vents, an ozone producing element installed within the casing for generating ozone in order to deodorizing dresses within the closet, a circulating fan installed within the casing for circulating ozone generated by the ozone producing element, and a hanging unit projecting outward from the casing and adapted to be hung onto a suspension member. The closet is sleeved over and cooperates with the casing to define a sealed chamber so that dresses can be kept therein. | 08-11-2011 |
20110268625 | GARMENT BAG - A garment bag is sleeved over an ozone generator generating ozone therein. The garment bag includes a hollow bag body and an ozone filter unit. The ozone filter unit is disposed on the bag body. When the ozone in the bag body flows to the ozone filter unit, the ozone can be decomposed by the ozone filter unit. | 11-03-2011 |
20130331640 | OPTICAL THERAPEUTIC APPARATUS - An optical therapeutic apparatus includes an ear shield for covering a wearer's ear, which has a plurality of acupuncture points; a hanging member including a connection portion connected to the ear shield; and a plurality of light emitters disposed within an interior portion of the ear shield in array manner to face the plurality of acupuncture points respectively. The plurality of light emitters includes a plurality of acupoint-stimulation elements, each corresponding to a respective one of the acupuncture points, at least two sets of the acupoint-stimulation elements are capable of emitting stimulation light beams at different time intervals. | 12-12-2013 |
20140236269 | HAIR RESTORATION CARING DEVICE - A hair restoration caring device includes a treatment hood, a suspension member and a hair caring device. The treatment hood is to be disposed over a user's head. The suspension member is fastened to the treatment hood. The hair caring device is attached to the suspension member and is movable with respect to the user scalp. The hair caring device includes an outer casing mounted slidably on the suspension member, and has several downward combing projections and several light emitters installed above the combing projections respectively for radiating light waves. Each combing projection is aligned with a respective light emitter and is formed with an axial passage to permit past through of light waves of the respective light emitter. | 08-21-2014 |
Patent application number | Description | Published |
20080277782 | FLASH MEMORY CARD - A Flash memory card is disclosed comprising a substrate, a Flash memory die on top of the substrate, a controller die on top of the Flash memory die, and an interposer coupled to with the controller die and on top of the Flash memory die wherein the interposer results in substantial reduced wire bonding to the substrate. The interposer can surround or be placed side by side with the controller die. A system and method in accordance with the present invention achieves the following objectives: (1) takes advantage of as large of a Flash memory die as possible, to increase the density of the Flash card by reducing the number of wire bond pads on the substrate and enabling insertion of the largest die possible that can fit inside a given card interior boundary; (2) more efficiently stacks Flash memory dies to increase density of the Flash card; and (3) has a substantially less number of bonding wires to the substrate as possible, to improve production yield. | 11-13-2008 |
20090283313 | SMALL FORM FACTOR MOLDED MEMORY CARD AND A METHOD THEREOF - A shape-molding structure of a memory card comprises a circuit substrate, at least one chip, and an encapsulant covering. The upper and lower surfaces of the circuit substrate have a circuit layer and a plurality of electric contacts, respectively. The chip is located on the upper surface of the circuit substrate and electrically connected with the circuit layer. The encapsulant covering is formed by using a mold to press encapsulant entering at least one encapsulant inlet provided on at least one side surface of the circuit substrate. The encapsulant covering encapsulates all the above components with only the electric contacts exposed. A trace mark of the encapsulant inlet remaining on the encapsulant covering is then cut to obtain a shape-molding structure of memory card with an smooth and intact outer appearance. | 11-19-2009 |
20100133673 | FLASH MEMORY CARD - A Flash memory card is disclosed comprising a substrate, a Flash memory die on top of the substrate, a controller die on top of the Flash memory die, and an interposer coupled to with the controller die and on top of the Flash memory die wherein the interposer results in substantial reduced wire bonding to the substrate. The interposer can surround or be placed side by side with the controller die. A system and method in accordance with the present invention achieves the following objectives: (1) takes advantage of as large of a Flash memory die as possible, to increase the density of the Flash card by reducing the number of wire bond pads on the substrate and enabling insertion of the largest die possible that can fit inside a given card interior boundary; (2) more efficiently stacks Flash memory dies to increase density of the Flash card; and (3) has a substantially less number of bonding wires to the substrate as possible, to improve production yield. | 06-03-2010 |
20100268873 | FLASH MEMORY CONTROLLER UTILIZING MULTIPLE VOLTAGES AND A METHOD OF USE - A Flash memory controller is disclosed. The Flash memory controller comprises a host interface, a Flash memory interface, controller logic coupled between the host interface, the controller logic handling a plurality of voltages. The controller also includes a mechanism for allowing a multiple voltage host to interface with a high voltage or a multiple voltage Flash memory. A multiple voltage Flash memory controller in accordance with the present invention provides the following advantages over conventional Flash memory controllers: (1) a voltage host is allowed to interface with multiple Flash memory components that operate at different voltages in any combination; (2) power consumption efficiency is improved by integrating the programmable voltage regulator, and voltage comparator mechanism with the Flash memory controller; (3) External jumper selection is eliminated for power source configuration; and (4) Flash memory controller power source interface pin-outs are simplified. | 10-21-2010 |
Patent application number | Description | Published |
20100136105 | PHARMACEUTICAL COMPOSITIONS AND DOSAGE FORMS FOR ADMINISTRATION OF HYDROPHOBIC DRUGS - The present invention relates to pharmaceutical compositions and methods for improved solubilization of triglycerides and improved delivery of therapeutic agents. Compositions of the present invention include a carrier, where the carrier is formed from a combination of a triglyceride and at least two surfactants, at least one of which is hydrophilic. Upon dilution with an aqueous medium, the carrier forms a clear, aqueous dispersion of the triglyceride and surfactants. | 06-03-2010 |
20100137271 | PHARMACEUTICAL COMPOSITIONS AND DOSAGE FORMS FOR ADMINISTRATION OF HYDROPHOBIC DRUGS - Pharmaceutical compositions and dosage forms for administration of hydrophobic drugs are provided. The pharmaceutical compositions include a therapeutically effective amount of a hydrophobic drug, preferably a steroid; a solubilizer, and a surfactant. The synergistic effect between the hydrophobic drug and the solubilizer results in a pharmaceutical formulation with improved dispersion of both the active agent and the solubilizer. As a result of the improved dispersion, the pharmaceutical composition has improved bioavailability upon administration. Methods of improving the bioavailability of hydrophobic drugs administered to a patient are also provided. | 06-03-2010 |
20120101049 | Pharmaceutical Composition Of A Potent HCV Inhibitor For Oral Administration - A pharmaceutical composition of the following Compound (1), a potent hepatitis C viral (HCV) inhibitor, or a pharmaceutically acceptable salt thereof, for oral administration. | 04-26-2012 |
20140037719 | STABILIZED PHARMACEUTICAL FORMULATIONS OF A POTENT HCV INHIBITOR - Described are various methods for stabilizing pharmaceutical formulations of a specific Hepatitis C Viral (HCV) inhibitor against the formation of a particular genotoxic degradation product. Such methods include temperature control, moisture control, excipient control, capsule shell control, basification and a reconstitution approach. | 02-06-2014 |
20150038532 | Pharmaceutical Composition Of A Potent HCV Inhibitor For Oral Administration - A pharmaceutical composition of the following Compound (1), a potent hepatitis C viral (HCV) inhibitor, or a pharmaceutically acceptable salt thereof, for oral administration. | 02-05-2015 |
Patent application number | Description | Published |
20100205071 | METHODS AND SYSTEMS OF MAINTAINING AND MONITORING VEHICLE TRACKING DEVICE INVENTORIES - Systems and methods of tracking an installer's inventory of vehicle tracking devices performed by the supplier of the devices are provided. Inventory levels of the devices are checked based on activation and/or registration of a tracking device and a subsequent stock-out notification is sent to the installer based on the checked inventory level. | 08-12-2010 |
20120158211 | SYSTEMS AND METHODS FOR COLLECTING INFORMATION FROM VEHICLE DEVICES VIA A VEHICLE DATA BUS - Systems and methods in accordance with embodiments of the invention continuously collect information from vehicle devices via a vehicle data bus, store information in a database, and retrieve information from the database in response to requests from remote devices. One embodiment includes a vehicle position determining device, a wireless communications device, and a controller apart from at least one operable vehicle device, connected to the vehicle data bus so that the vehicle data bus extends from said controller to at least one operable vehicle device. Additionally, the controller is configured to query at least one vehicle device via the vehicle data bus and store information provided by at least one vehicle device in a database, receive requests for information from a remote device via the wireless communications device, query the database for the requested information, and send the requested information to the remote device via the wireless communications device. | 06-21-2012 |
20130287010 | Dynamic Beacon Rates and Fixed Ad Hoc Modes in Ad Hoc Networks - Systems and methods for dynamic beacon rates and fixed ad hoc modes in ad hoc networks in accordance with embodiments of the invention are disclosed. In one embodiment of the invention, an ad hoc wireless network includes a plurality of peers configured to form an ad hoc network, wherein the plurality of peers are configured to transmit and receive beacon frames, wherein one or more of the plurality of peers is configured to be fixed in a host mode, wherein one or more of the plurality of peers is configured to be fixed in a client mode, wherein the one or more peers in host mode are configured to transmit beacon frames, where the beacon frames identify an ad hoc wireless network, and wherein a peer not connected to an ad hoc wireless network does not transmit beacon frames when in client mode. | 10-31-2013 |
20140309843 | Systems and Methods for Collecting Information from Vehicle Devices Via a Vehicle Data Bus - Systems and methods in accordance with embodiments of the invention continuously collecting information via a vehicle data bus, store the information in a database, and retrieve the information in response to requests from remote devices. One embodiment includes a vehicle position determining device, a wireless communications device, and a controller spaced apart from the at least one operable vehicle device and connected to the vehicle data bus so that the vehicle data bus extends from said controller to the at least one operable vehicle device. The controller is configured to query the at least one vehicle device via the vehicle data bus and store the information provided in a database, and receive requests for information from a remote device via the wireless communications device, query the database for the requested information and send the requested information to the remote device via the wireless communications device. | 10-16-2014 |
Patent application number | Description | Published |
20120065729 | SYSTEMS AND METHODS FOR RAPIDLY DEPLOYING SURGICAL HEART VALVES - A quick-connect heart valve prosthesis that can be quickly and easily implanted during a surgical procedure is provided. The heart valve includes a substantially non-expandable, non-compressible prosthetic valve and a plastically-expandable frame, thereby enabling attachment to the annulus without sutures. A small number of guide sutures may be provided for aortic valve orientation. The prosthetic valve may be a commercially available valve with a sewing ring with the frame attached thereto. The frame may expand from a conical deployment shape to a conical expanded shape, and may include web-like struts connected between axially-extending posts. A system and method for deployment includes an integrated handle shaft and balloon catheter. A valve holder is stored with the heart valve and the handle shaft easily attaches thereto to improve valve preparation steps. | 03-15-2012 |
20130079873 | PROSTHETIC MITRAL VALVE WITH VENTRICULAR TETHERS AND METHODS FOR IMPLANTING SAME - A prosthetic valve assembly and method of implanting same is disclosed. The prosthetic valve assembly includes a prosthetic valve formed by support frame and valve leaflets, with one or more tethers each having a first end secured to the support frame and the second end attached to, or configured for attachment to, to papillary muscles or other ventricular tissue. The tether is configured and positioned so as to avoid contact or other interference with movement of the valve leaflets, while at the same time providing a tethering action between the support frame and the ventricular tissue. The valve leaflets may be flexible (e.g., so-called tissue or synthetic leaflets) or mechanical. | 03-28-2013 |
20130160512 | APPARATUS AND METHOD FOR STENT SHAPING - An apparatus for crimping a radially expandable stent includes a pressure vessel, shaping balloon, and mandrel. The mandrel is configured to slidingly receive a stent thereon, and to be slidingly advanced into the pressure vessel. The shaping balloon is inflated to radially compress the stent onto the form of the mandrel; such compression need not be uniform. Pressurization of the shaping balloon facilitates the expansion of the balloon to achieve compression of the stent, with depressurization of the shaping balloon causing the balloon to return to an unexpanded state. | 06-27-2013 |
20140188221 | SURGICAL HEART VALVES ADAPTED FOR POST-IMPLANT EXPANSION - A prosthetic heart valve configured to replace a native heart valve and having a support frame configured to be reshaped into an expanded form in order to receive and/or support an expandable prosthetic heart valve therein is disclosed, together with methods of using same. The prosthetic heart valve may be configured to have a generally rigid and/or expansion-resistant configuration when initially implanted to replace a native valve (or other prosthetic heart valve), but to assume a generally expanded form when subjected to an outward force such as that provided by a dilation balloon or other mechanical expander. | 07-03-2014 |
20140200661 | RAPIDLY DEPLOYABLE SURGICAL HEART VALVES - A quick-connect heart valve prosthesis that can be quickly and easily implanted during a surgical procedure is provided. The heart valve includes a substantially non-expandable, non-compressible prosthetic valve and a plastically-expandable frame, thereby enabling attachment to the annulus without sutures. A small number of guide sutures may be provided for aortic valve orientation. The prosthetic valve may be a commercially available valve with a sewing ring with the frame attached thereto. The frame may expand from a conical deployment shape to a conical expanded shape, and may include web-like struts connected between axially-extending posts. A system and method for deployment includes an integrated handle shaft and balloon catheter. A valve holder is stored with the heart valve and the handle shaft easily attaches thereto to improve valve preparation steps. | 07-17-2014 |
20150066137 | INTEGRATED BALLOON CATHETER INFLATION SYSTEM - An inflation system having two pressure vessels integrated into a balloon catheter. A pressurized chamber and a vacuum chamber are integrally attached to proximal end of the balloon catheter and activated by a common valve or switch. Pressure or vacuum is selectively transmitted to the balloon depending on the valve/switch position. The working fluid may be air, or a combination of air and saline with an intermediate piston/cylinder assembly. The balloon catheter may be a part of a heart valve delivery system with a balloon-expandable heart valve crimped onto the balloon. | 03-05-2015 |
Patent application number | Description | Published |
20080246080 | Shallow trench isolation (STI) based laterally diffused metal oxide semiconductor (LDMOS) - An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes a first heavily doped region to represent a source region. A second heavily doped region represents a drain region of the semiconductor device. A third heavily doped region represents a gate region of the semiconductor device. The semiconductor device further includes a shallow trench isolation (STI) region to increase the resistance from the drain region to the source region. The STI region includes a first side vertically aligned with a second side of the gate region. The STI region extends from the first side to a second side in contact with a second side of the drain region. The breakdown voltage of the n-type semiconductor device is directly proportional to a vertical length, or a depth, of the first side and/or the second side of the STI region. The horizontal length, or distance from the first side to the second side, of the STI region does not substantially contribute to the breakdown voltage of the semiconductor device. As a result, a conventional CMOS logic foundry technology may fabricate the STI region of the semiconductor device using a low operating voltage process minimum design rule. | 10-09-2008 |
20100284210 | One-time programmable memory cell - According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a cell transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The cell transistor has a source, a gate, and a body shorted together. A programming operation causes a punchthrough to occur between the source and a drain of the cell transistor in response to a programming voltage on the bitline and the wordline. A channel length of the cell transistor is substantially less than a channel length of the access transistor. In one embodiment, the access transistor is an NFET while the cell transistor is a PFET. In another embodiment, the access transistor is an NFET and the cell transistor is also an NFET. Various embodiments result in a reduction of the required programming voltage. | 11-11-2010 |
20100314691 | Method for selective gate halo implantation in a semiconductor die and related structure - According to one embodiment, a method for selective gate halo implantation includes forming at least one gate having a first orientation and at least one gate having a second orientation over a substrate. The method further includes performing a halo implant over the substrate. The first orientation allows a halo implanted area to be formed under the at least one gate having the first orientation and the second orientation prevents a halo implanted area from forming under the at least one gate having the second orientation. The halo implant is performed without forming a mask over the at least one gate having the first orientation or the at least one gate having the second orientation. The at least one gate having the first orientation can be used in a low voltage region of a substrate, while the at least one gate having the second orientation can be used in a high voltage region. | 12-16-2010 |
20110049620 | Method for fabricating a MOS transistor with source/well heterojunction and related structure - According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a gate stack over a well. The method further includes forming a recess in the well adjacent to a first sidewall of the gate stack. The method further includes forming a source region in the recess such that a heterojunction is formed between the source region and the well. The method further includes forming a drain region spaced apart from a second sidewall of the gate stack. In one embodiment, the source region can comprise silicon germanium and the well can comprise silicon. In another embodiment, the source region can comprise silicon carbide and the well can comprise silicon. | 03-03-2011 |
20110057271 | Semiconductor Device with Increased Breakdown Voltage - Optimization of the implantation structure of a metal oxide silicon field effect transistor (MOSFET) device fabricated using conventional complementary metal oxide silicon (CMOS) logic foundry technology to increase the breakdown voltage. The techniques used to optimize the implantation structure involve lightly implanting the gate region, displacing the drain region from the gate region, and implanting P-well and N-well regions adjacent to one another without an isolation region in between. | 03-10-2011 |
20110089490 | Method for fabricating a MOS transistor with reduced channel length variation and related structure - According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor. | 04-21-2011 |
20110169079 | Semiconductor device having an overlapping multi-well implant and method for fabricating same - According to one embodiment, a semiconductor device having an overlapping multi-well implant comprises an isolation structure formed in a semiconductor body, a first well implant formed in the semiconductor body surrounding the isolation structure, and a second well implant overlapping at least a portion of the first well implant. The disclosed semiconductor device, which may be an NMOS or PMOS device, can further comprise a gate formed over the semiconductor body adjacent to the isolation structure, wherein the first well implant extends a first lateral distance under the gate and the second well implant extends a second lateral distance under the gate, and wherein the first and second lateral distances may be different. In one embodiment, the disclosed semiconductor device is fabricated as part of an integrated circuit including a power management circuit or a power amplifier. | 07-14-2011 |
20130001687 | Transistor with Reduced Channel Length Variation - According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor. | 01-03-2013 |
20130017658 | Method for Fabricating a MOS Transistor with Reduced Channel Length Variation - According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor. | 01-17-2013 |
20130082351 | Method for Fabricating a MIM Capacitor Having a Local Interconnect Metal Electrode and Related Structure - According to one exemplary embodiment, a method for fabricating a metal-insulator-metal (MIM) capacitor in a semiconductor die comprises forming a bottom capacitor electrode over a device layer situated below a first metallization layer of the semiconductor die, and forming a top capacitor electrode over an interlayer barrier dielectric formed over the bottom capacitor electrode. The top capacitor electrode is formed from a local interconnect metal for connecting devices formed in the device layer. In one embodiment, the bottom capacitor electrode is formed from a gate metal. The method may further comprise forming a metal plate in the first metallization layer and over the top capacitor electrode, and connecting the metal plate to the bottom capacitor electrode to provide increased capacitance density. | 04-04-2013 |
20130087886 | MOM Capacitor Having Local Interconnect Metal Plates and Related Method - According to one exemplary embodiment, a metal-oxide-metal (MOM) capacitor in a semiconductor die comprises a first plurality of capacitor plates and a second plurality of capacitor plates sharing a plane parallel to and below a plane of a first metallization layer of the semiconductor die. The MOM capacitor further comprises a local interlayer dielectric between the first plurality of capacitor plates and the second plurality of capacitor plates. The first and second plurality of capacitor plates are made from a local interconnect metal for connecting devices formed in a device layer of the semiconductor die situated below the first metallization layer. | 04-11-2013 |
20140084368 | Semiconductor Device with Increased Breakdown Voltage - Optimization of the implantation structure of a metal oxide silicon field effect transistor (MOSFET) device fabricated using conventional complementary metal oxide silicon (CMOS) logic foundry technology to increase the breakdown voltage. The techniques used to optimize the implantation structure involve lightly implanting the gate region, displacing the drain region from the gate region, and implanting P-well and N-well regions adjacent to one another without an isolation region in between. | 03-27-2014 |
20140299964 | ON-CHIP INDUCTOR USING REDISTRIBUTION LAYER AND DUAL-LAYER PASSIVIATION - A system and method utilize a redistribution layer in a flip-chip or wirebond package, which is also used to route signals to bumps, as a layer for the construction of an on-chip inductor or a layer of a multiple-layer on-chip inductor. In one example, the redistribution layer is surrounded by dual-layer passivation to protect it, and the inductor formed thereby, from the environment and isolate it, and the inductor formed thereby, from the metal layer beneath it. | 10-09-2014 |
Patent application number | Description | Published |
20080215332 | Methods and apparatus for adapting speech coders to improve cochlear implant performance - Cochlear implant performance is improved by extracting pitch information and encoding such pitch information into the processor of a cochlear implant. One embodiment of the invention is to explicitly extract the pitch and deliver it to the cochlear implant by co-varying the stimulate site and rate. Another embodiment of the invention is to implicitly encode the pitch information via a code book that serves as the carrier of stimulation in the cochlear implant. | 09-04-2008 |
20090024184 | COCHLEAR IMPLANT UTILIZING MULTIPLE-RESOLUTION CURRENT SOURCES AND FLEXIBLE DATA ENCODING - A programmable cochlear implant system utilizes multiple-resolution current sources and flexible data-encoding scheme for transcutaneous transmission. In certain embodiments, the number of current sources may be equal to or greater than 2, but equal or less than N−1, where N is the number of electrodes. The multi-resolution current source may introduce offset currents to achieve perceptually-based multiple resolutions with high resolution at low amplitudes and low resolution at high amplitudes. The flexible data-encoding scheme may allow arbitrary waveforms in terms of phase polarity, phase duration, pseudo-analog-waveform, while producing high-rate and high-temporal-precision stimulation. In one embodiment, a 2-current-source system may support simultaneous and non-simultaneous stimulation as well as monopolar, bipolar, pseudo-tripolar, and tripolar electrode configurations. | 01-22-2009 |
20120083859 | Cochlear Implant Utilizing Mutliple-Resolution Current Sources and Flexible Data Encoding - A programmable cochlear implant system utilizes multiple-resolution current sources and flexible data-encoding scheme for transcutaneous transmission. In certain embodiments, the number of current sources may be equal to or greater than 2, but equal or less than N−1, where N is the number of electrodes. The multi-resolution current source may introduce offset currents to achieve perceptually-based multiple resolutions with high resolution at low amplitudes and low resolution at high amplitudes. The flexible data-encoding scheme may allow arbitrary waveforms in terms of phase polarity, phase duration, pseudo-analog-waveform, while producing high-rate and high-temporal-precision stimulation. In one embodiment, a 2-current-source system may support simultaneous and non-simultaneous stimulation as well as monopolar, bipolar, pseudo-tripolar, and tripolar electrode configurations. | 04-05-2012 |
Patent application number | Description | Published |
20080234334 | 1,4 DIAMINO BICYCLIC RETIGABINE ANALOGUES AS POTASSIUM CHANNEL MODULATORS - This invention is directed to compounds of formula I, | 09-25-2008 |
20080306063 | PHENYLAMINO ISOTHIAZOLE CARBOXAMIDINES AS MEK INHIBITORS - The invention concerns compounds which inhibit MEK and which have activity as anti-neoplastic agents. These compounds include N-substituted-3-hydroxy-5-arylamino-isothiazole-4-carboxamidines. Also included are the tautomeric isothiazol-3(2H)-ones. | 12-11-2008 |
20090029983 | NOVEL HETEROCYCLIC COMPOUNDS HAVING ANTI-HBV ACTIVITY - This application relates to novel fused tricyclic thienopyridines of Formulas I and II, which useful for treating Hepatitis B infection and other diseases. | 01-29-2009 |
20090137041 | 3-HYDROXYISOTHIAZOLE-4-CARBOXAMIDINE DERIVATIVES AS CHK2 INHIBITORS - This invention provides compounds of Formula I | 05-28-2009 |
20090137635 | DERIVATIVES OF 5-AMINO-4,6-DISUBSTITUTED INDOLE AND 5-AMINO-4,6-DISUBSTITUTED INDOLINE AS POTASSIUM CHANNEL MODULATORS - This invention provides compounds of formula I | 05-28-2009 |
20090326059 | BENZYLOXY ANILIDE DERIVATIVES USEFUL AS POTASSIUM CHANNEL MODULATORS - The present invention relates to benzyloxyanilide derivatives having the following structural formula: | 12-31-2009 |
20110003850 | DERIVATIVES OF 4-(N-AZACYCLOALKYL) ANILIDES AS POTASSIUM CHANNEL MODULATORS - This invention provides a compound of formula IA | 01-06-2011 |
20110118318 | DERIVATIVES OF 5-AMINO-4,6-DISUBSTITUTED INDOLE AND 5-AMINO-4,6-DISUBSTITUTED INDOLINE AS POTASSIUM CHANNEL MODULATORS - This invention provides compounds of formula I | 05-19-2011 |
20110166123 | NOVEL COMPOSITIONS AND METHODS OF USE - Described herein are novel enzyme inhibitors. In some embodiments the enzyme inhibitors are integrase inhibitors, particularly HIV integrase inhibitors. Also described herein are compositions containing them and methods of using them. Thus, the compounds and compositions described herein are useful for the in vitro and in vivo inhibition of HIV integrase as a method of treating or preventing HIV, AIDS or related disorders. | 07-07-2011 |
20110207812 | SUBSTITUTED ARYLAMINO-1,2,3,4-TETRAHYDRO NAPHTHALENES AND -2,3-DIHYDRO-1H-INDENES AS POTASSIUM CHANNEL MODULATORS - This invention provides compounds of formula I | 08-25-2011 |
20110269741 | NOVEL COMPOSITIONS AND METHODS OF USE - Described herein are novel enzyme inhibitors. In some embodiments the enzyme inhibitors are integrase inhibitors, particularly HIV integrase inhibitors. Also described herein are compositions containing them and methods of using them. Thus, the compounds and compositions described herein are useful for the in vitro and in vivo inhibition of HIV integrase as a method of treating or preventing HIV, AIDS or related disorders. | 11-03-2011 |
20120329869 | BENZYLOXY ANILIDE DERIVATIVES USEFUL AS POTASSIUM CHANNEL MODULATORS - The present invention relates to benzyloxyanilide derivatives having the following structural formula: | 12-27-2012 |
20140155389 | BICYCLIC INHIBITORS OF ALK - The present invention relates to compounds of formula (1) or pharmaceutical acceptable salts, wherein R | 06-05-2014 |
20140171429 | BICYCLIC INHIBITORS OF ALK - The present invention relates to compounds of formula (1) or pharmaceutical acceptable salts, Formula (1) wherein R | 06-19-2014 |
20140194418 | BICYCLIC CARBOXAMIDE INHIBITORS OF KINASES - Compounds of formula (I) or pharmaceutical acceptable salts are provided, wherein X | 07-10-2014 |
Patent application number | Description | Published |
20100041986 | ABLATION AND MONITORING SYSTEM INCLUDING A FIBER OPTIC IMAGING CATHETER AND AN OPTICAL COHERENCE TOMOGRAPHY SYSTEM - An ablation and monitoring system comprises a catheter, an optical coherence tomography (OCT) system, and an ablation generator. The catheter comprises one or more optical fibers to transmit a light beam to a tissue material and collect a reflected light from the tissue material. The OCT system is in optical communication with the catheter via the one or more optical fibers, providing the light beam to the one or more optical fibers and receiving the reflected light from the one or more optical fibers. The ablation generator is in electrical communication with the OCT system and with the catheter. The ablation generator provides radio frequency energy to the catheter for ablating the tissue material, monitors and assesses the ablation based on an information signal received from the OCT system. | 02-18-2010 |
20100286684 | IRRIGATED ABLATION CATHETER WITH MULTIPLE SEGMENTED ABLATION ELECTRODES - In one embodiment, an irrigated catheter ablation apparatus comprises an elongated body having a distal end, a proximal end, and at least one fluid lumen extending longitudinally therein; and a plurality of segmented ablation electrodes on a distal portion of the elongated body. The electrodes are spaced from the proximal end and from the distal end of the elongated body by electrically nonconductive segments. The electrodes are spaced from each other longitudinally by electrically nonconductive segments. For each electrode that is longitudinally disposed next to one of the nonconductive segments, an edge is formed between an electrode end of the electrode and a nonconductive segment end of the nonconductive segment. A plurality of elution holes are disposed adjacent to the edges. A plurality of ducts establish fluid communication between the elution holes and the fluid lumen. | 11-11-2010 |
20110137298 | ULTRASOUND ABLATION APPARATUS WITH DISCRETE STAGGERED ABLATION ZONES - An ablation apparatus comprises an ultrasonic transducer which includes a piezoelectric element having a cylindrical shape; a plurality of external electrodes disposed on the outer surface of the piezoelectric element; and at least one internal electrode disposed on the inner surface of the piezoelectric element. The at least one internal electrode provides corresponding internal electrode portions that are disposed opposite the external electrodes with respect to the piezoelectric element, the external electrodes and the at least one internal electrode to be energized to apply an electric field across the piezoelectric element. The ultrasonic ablation zones of the external electrodes are distributed in a staggered configuration so as to span one or more open arc segments around the longitudinal axis, and the ultrasound ablation zones of all external electrodes projected longitudinally onto any lateral plane which is perpendicular to the longitudinal axis span a substantially closed loop around the longitudinal axis. | 06-09-2011 |
20110201973 | ULTRASOUND COMPATIBLE RADIOFREQUENCY ABLATION ELECTRODE - Embodiments of the present invention are directed to an ultrasound compatible ablation electrode for use in ultrasound imaging guidance of ablation therapy using RF or the like. In one embodiment, an ultrasound compatible ablation catheter comprises a catheter body having a distal end and an ultrasonic transducer directing ultrasonic beams for imaging a target; and an ablation electrode connected to the catheter body, the ablation electrode having a plastic shell and a metallic coating on the plastic shell which are disposed in a path of the ultrasonic beams of the ultrasonic transducer between the ultrasonic transducer and the target, the metallic coating of the ablation electrode to be energized for ablation. | 08-18-2011 |
20110230797 | System and methods for locating and ablating arrhythomogenic tissues - The disclosure relates to a variety of systems and methods for sensing electrical events about a selected annulus region of the heart and for treating tissue in the selected annulus region. Wherein the system includes a first catheter that has an expandable member, an ablation element, and a lumen configured to allow a second catheter therethrough. The second catheter includes a distal section in a ring shape and a plurality of electrodes coupled around the ring. Optionally a second lumen can be included through the first catheter that allows for contrast media to be delivered to the distal end of the system. | 09-22-2011 |
20110282424 | PERCUTANEOUS LEAD WITH DISTAL FIXATION - A lead includes an elongated body and an anchor segment disposed between the distal end of the body and electrodes on a distal portion of the body. The anchor segment has lobes which are separated by slits and movable between a collapsed position and an expanded position. A positioning mechanism is disposed inside the hollow interior of the body and at least partially within the anchor segment. The positioning mechanism has a distal positioning portion attached to the distal end of the body and a proximal positioning portion. A control member is connected with the proximal positioning portion to control the positioning mechanism to pull the distal end toward the proximal end so as to move the lobes from the collapsed position to the expanded position and to push the distal end away from the proximal end so as to move the lobes from the expanded to the collapsed position. | 11-17-2011 |
20130237791 | System and methods for locating and ablating arrhythomogenic tissues - The disclosure relates to a variety of systems and methods for sensing electrical events about a selected annulus region of the heart and for treating tissue in the selected annulus region. Wherein the system includes a first catheter that has an expandable member, an ablation element, and a lumen configured to allow a second catheter therethrough. The second catheter includes a distal section in a ring shape and a plurality of electrodes coupled around the ring. Optionally a second lumen can be included through the first catheter that allows for contrast media to be delivered to the distal end of the system. | 09-12-2013 |
20140330269 | IRRIGATED FLEXIBLE ABLATION CATHETER - A flexible tip electrode for an ablation catheter is disclosed. The catheter includes a catheter body and a hollow elongate tip electrode disposed at a distal end of the catheter body. The electrode includes a sidewall provided with one or more elongate gaps extending therethrough. The one or more elongate gaps providing flexibility in the sidewall for bending movement of the tip electrode relative to a longitudinal axis of the catheter body. | 11-06-2014 |
Patent application number | Description | Published |
20110009741 | Endovascular Optical Coherence Tomography Device - An endovascular OCT probe is included in an endovascular access device for intravascular imaging. The probe includes a hollow coil wire defining an axial lumen of the endovascular access device. A single mode optical fiber for transmitting light is disposed in the axial lumen of the hollow coil wire so that translation and rotation of the hollow coil wire carrying the optical fiber within the endovascular access device is stabilized for scanning endovascular tissue with at least 5 microns resolution. An optic element directs light from and into the optical fiber at a distal tip of the optical fiber and is coupled to or fixed to the distal end of the optical fiber. The optic element and the distal end of the optical fiber is disposed within a glass ferule to protect it from damage. | 01-13-2011 |
20110009752 | ENDOSCOPIC LONG RANGE FOURIER DOMAIN OPTICAL COHERENCE TOMOGRAPHY (LR-FD-OCT) - An endoscopic swept-source Fourier Domain optical coherence tomographic system (FDOCT system) for imaging of tissue structure includes a Fourier Domain mode locked (FDML), high speed, narrow line-width, wavelength swept source, an OCT interferometer having a sample arm, a reference arm, a detection arm, and a source arm coupled to the swept source, an endoscopic probe coupled to the sample arm, and a data processing circuit coupled to the detection arm. The swept source includes a long optic fiber functioning as a cavity, a high optical gain lasing module, and a tunable narrow bandwidth bandpass filter for wavelength selection combined to form a unidirectional ring laser cavity, where the tunable narrow bandwidth bandpass filter is driven synchronously with the optical round-trip time of a propagating light wave in the cavity. | 01-13-2011 |
20110098572 | ULTRASOUND GUIDED OPTICAL COHERENCE TOMOGRAPHY, PHOTOACOUSTIC PROBE FOR BIOMEDICAL IMAGING - An imaging probe for a biological sample includes an OCT probe and an ultrasound probe combined with the OCT probe in an integral probe package capable of providing by a single scanning operation images from the OCT probe and ultrasound probe to simultaneously provide integrated optical coherence tomography (OCT) and ultrasound imaging of the same biological sample. A method to provide high resolution imaging of biomedical tissue includes the steps of finding an area of interest using the guidance of ultrasound imaging, and obtaining an OCT image and once the area of interest is identified where the combination of the two imaging modalities yields high resolution OCT and deep penetration depth ultrasound imaging. | 04-28-2011 |
20110282166 | System and Method for Efficient Coherence Anti-Stokes Raman Scattering Endoscopic and Intravascular Imaging and Multimodal Imaging - A fiber-delivered probe suitable for CARS imaging of thick tissues is practical. The disclosed design is based on two advances. First, a major problem in CARS probe design is the presence of a very strong anti-Stokes component in silica delivery fibers generated through a FWM process. Without proper spectral filtering, this component affects the CARS image from the tissue sample. The illustrated embodiments of the invention efficiently suppress this spurious anti-Stokes component through the use of a separate fiber for excitation delivery and for signal detection, which allows the incorporation of dichroic optics for anti-Stokes rejection. Second, the detection of backscattered CARS radiation from the sample is optimized by using a large core multi mode fiber in the detection channel. This scheme produces high quality CARS images free of detector aperture effects. Miniaturization of this fiber-delivered probe results in a practical handheld probe for clinical CARS imaging. | 11-17-2011 |
20140241596 | Apparatus and Method for Capturing a Vital Vascular Fingerprint - A method using optical coherence tomography to capture the microvascular network of the superficial layer of the finger skin for the purpose of fingerprint authentication and liveness detection. At the dermal papilla region, the vascular pattern follows the same pattern of the fingerprint and this vascular pattern forms a live vascular fingerprint. This live vascular fingerprint provides for ultrahigh security and a unique way for fingerprint-based personal verification. Because the system is based on blood flow, which only exists in a living person, the technique is robust against spoof attaching. After performing non-contact in-vivo imaging of a human fingertip, a three dimensional vasculature image is reconstructed from a plurality of vasculature tomography images and at least one vasculature fingerprint image which corresponds to the fingertip is extracted from the three dimensional vasculature image. This extracted image may then be compared to known fingerprint database for authentication or for liveness detection. | 08-28-2014 |