Patent application number | Description | Published |
20120023812 | METHOD FOR PRODUCING GAS OIL COMPOSITION - The present invention provides a gas oil composition that can achieve environment load reduction, low temperature properties and low fuel consumption all together and is suitably used in a winter season. The gas oil composition comprises an FT synthetic base oil in an amount of 60 percent by mass or more on the basis of the total mass of the composition and has a sulfur content of 5 ppm by mass or less, an aromatic content of 10 percent by volume or less, an oxygen content of 100 ppm or less, an end point of 360° C. or lower, an insoluble content after an oxidation stability test of 0.5 mg/100 mL or less, an HFRR wear scar diameter (WS1.4) of 400 μm or smaller and a specific relation in normal paraffin contents and the total content thereof. | 02-02-2012 |
20120096268 | ELECTRONIC FILE SENDING METHOD - An electronic file sending method is provided to securely and easily send en electronic file to a receiver. A receiving apparatus receives from a sending apparatus an electronic mail including an encrypted electronic file. The sending apparatus uses a public key of a management server to encrypt a decryption password that is necessary to decrypt the encrypted electronic file and sends the encrypted decryption password to the management server. In association with a file identifier of the electronic file, the management server stores the decryption password and an electronic mail address of a correct receiver, who is a receiver of the receiving apparatus. The receiving apparatus sends to the management server the file identifier of the electronic file and the electronic mail address of the receiver. The management server uses a public key of the receiving apparatus to encrypt the password and sends the encrypted password to the receiving apparatus. | 04-19-2012 |
20120167455 | METHOD FOR PRODUCING GAS OIL COMPOSITION - The present invention provides a gas oil composition that can achieve environment load reduction, low temperature properties and low fuel consumption all together and is suitably used in a winter season. The gas oil composition comprises an Ft synthetic base oil in an amount of 60 percent by mass or more on the basis of the total mass of the composition and has a sulfur content of 5 ppm by mass or less, an aromatic content of 10 percent by volume or less, an oxygen content of 100 ppm or less, an end point of 360° C. or lower, an insoluble content after an oxidation stability test of 0.5 mg/100 mL or less, an HFRR wear scar diameter (WS1.4) of 400 μm or smaller and a specific relation in normal paraffin contents and the total content thereof. | 07-05-2012 |
20120240453 | GAS OIL COMPOSITION PRODUCTION METHOD - The present invention provides a gas oil composition that can achieve environment load reduction, low temperature properties and low fuel consumption all together and is suitably used in a winter season. The gas oil composition comprises an Ft synthetic base oil in an amount of 60 percent by mass or more on the basis of the total mass of the composition and has a sulfur content of 5 ppm by mass or less, an aromatic content of 10 percent by volume or less, an oxygen content of 100 ppm or less, an end point of 360° C. or lower, an insoluble content after an oxidation stability test of 0.5 mg/100 mL or less, an HFRR wear scar diameter (WS1.4) of 400 μm or smaller and a specific relation in normal paraffin contents and the total content thereof. | 09-27-2012 |
20130309587 | DESULFURIZATION SYSTEM FOR FUEL CELL, HYDROGEN PRODUCTION SYSTEM FOR FUEL CELL, FUEL CELL SYSTEM, DESULFURIZATION METHOD FOR HYDROCARBON FUEL, AND METHOD FOR PRODUCING HYDROGEN - A desulfurization system for a fuel cell of the invention includes a fuel supply unit that supplies a hydrocarbon fuel, which contains sulfur compounds, contains oxygen at a volume concentration of 1 ppm to 4%, and has a Wobbe index of 12 kWh/m | 11-21-2013 |
20140052990 | ELECTRONIC FILE SENDING METHOD - An electronic file sending method is provided to securely and easily send en electronic file to a receiver. A receiving apparatus receives from a sending apparatus an electronic mail including an encrypted electronic file. The sending apparatus uses a public key of a management server to encrypt a decryption password that is necessary to decrypt the encrypted electronic file and sends the encrypted decryption password to the management server. In association with a file identifier of the electronic file, the management server stores the decryption password and an electronic mail address of a correct receiver, who is a receiver of the receiving apparatus. The receiving apparatus sends to the management server the file identifier of the electronic file and the electronic mail address of the receiver. The management server uses a public key of the receiving apparatus to encrypt the password and sends the encrypted password to the receiving apparatus. | 02-20-2014 |
Patent application number | Description | Published |
20110150530 | IMAGE FORMING APPARATUS - An image forming apparatus including, a photosensitive body for carrying toner images, a transfer section for nipping the recording sheet at a position facing the photosensitive body and transferring the toner images carried on the photosensitive body onto a recording sheet, a driving section for driving the photosensitive body, and a control section for giving instructions to the driving section to conduct a velocity control to rotate the photosensitive body at a predetermined velocity, wherein the control section sets a gain of velocity control to be greater than normal condition, at a time which is at least one of a time when the recording sheet enters the transfer section, or a time when the recording sheet separates from the transfer section. | 06-23-2011 |
20110222922 | FIXING APPARATUS AND IMAGE FORMING APPARATUS INCORPORATING THE SAME - Disclosed is a fixing device, which makes it possible to prevent the air blasting section from deterioration, caused by heat transferred from the duct to the air blasting section. The fixing device includes a fixing section to fix the toner image onto the paper sheet; a heat source; and a separating section to separate the paper sheet from the pair of fixing members. On the other hand, the separating section includes: a gas blasting section to blast a gas; and a duct to guide the gas towards the pair of fixing members, and that is provided with a duct wall serving as a heat receiving surface to receive radiation heat irradiated from the fixing section, and at least one of the gas blasting section and the duct is provided with such a connection structure that suppresses heat transferring action from the duct to the gas blasting section. | 09-15-2011 |
20110280603 | FIXING DEVICE AND IMAGE FORMING APPARATUS - In order that the air surrounding a fixing member is prevented from entering a blowing section for blowing separation air, a wind speed setting section is provided with switchable control modes, namely, a first control mode (control mode for operating the blower fan at a wind speed for separation) and a second control mode (control mode for operating the blower fan at a low speed). This structure allows the blower fan to be controlled in conformity to any one of these first and second control modes. | 11-17-2011 |
20110305492 | FIXING DEVICE AND IMAGE FORMING APPARATUS - A fixing device includes: a fixing section which passes a sheet through a fixing nip portion formed by a pair of fixing members and thereby fixes a toner image on the sheet by heating; a blowing section which separates the sheet from the fixing members by blowing separation wind from a sheet discharge side of the fixing nip portion to the fixing members; an opening setting section which is provided with an opening region in which an opening width in a sheet width direction is adjustable, and adjusts a blowing range in the sheet width direction of the separation wind blown through the opening range from the blowing section to the fixing members; a temperature detection sensor for detecting temperature of the fixing members; and a control section which controls the opening width of the opening setting section based on the temperature detected of the fixing members. | 12-15-2011 |
20120027443 | IMAGE FORMING APPARATUS - An image forming apparatus including: a photoreceptor for bearing a toner image; a transfer body onto which the toner image borne by the photoreceptor is transferred; a drive section for driving the photoreceptor and transfer body respectively, and a control section for controlling the drive section so as to drive the photoreceptor and transfer body at a predetermined driving speed, wherein the control section, under a state in which the control section controls to drive the transfer body at the predetermined driving speed, controls to: a) drive the photoreceptor while changing the driving speed of the photoreceptor within a range of driving speeds between low speed and high speed, including the predetermined driving speed, b) extract torque characteristics under the control which includes the change of driving speed of the photoreceptor, and c) determine the driving speed of the photoreceptor based on the extracted torque characteristics. | 02-02-2012 |
20120098917 | IMAGE FORMING APPARATUS - Provided is an image forming apparatus to form an image by scanning with a light beam through a polygon mirror, having a motor drive section to rotate and drive the polygon mirror based on a polygon drive clock pulse and an image processing section capable of adjusting image magnification through image processing, and a control section to control that at least image magnification adjustment by changing revolution of the polygon mirror or image magnification adjustment through the image processing in the image processing section is selected in accordance with an output form of the image when the image magnification is adjusted. | 04-26-2012 |
20120127520 | OPERATION PANEL AND IMAGE FORMING APPARATUS - Provided is an operation panel using a touch panel method disposed on an image forming apparatus, wherein a CPU judges whether the same coordinate of an input section is in a pressurization when the operation panel is turned on and whether the first time period has elapsed while the above pressurization continues at the same coordinate, makes a display section to display a massage that the input section is unusable and a message to prompt a user to switch the input section to a substitution device, judges whether the pressurization continues after the second time period and the first time period have elapsed and makes the display section to display a warning to indicate that a malfunction occurs at the input section of the operation panel in case the input section is judged to be in the pressurization after the second time period elapsed. | 05-24-2012 |
20120147115 | IMAGE FORMING APPARATUS - An image forming apparatus including; an exposure section provided with, a light emitting element, a polygon mirror to receive light beams from the light emitting element, and to expose an image carrier using light beam via the polygon minor based on image data; an image processing section to adjust image magnification by image processing of the image data; and, a control section configured to select at least either of a first magnification adjustment to change a rotation speed of the polygon mirror and a second magnification adjustment to carry out image processing of the image data by the image processing section, based on comparison results between a paper interval time during recording paper conveyance in image formation and the first magnification adjustment time required to stabilize polygon mirror rotation in the first magnification adjustment, when adjusting image magnification with respect to recording paper. | 06-14-2012 |
20120189329 | IMAGE FORMING APPARATUS - Provided is an image forming apparatus having a first sheet dimension sensor at a conveyance path in a reverse conveyance section | 07-26-2012 |
20120200025 | IMAGE FORMING APPARATUS - Provided is an image forming apparatus which enables quick removal of remaining sheets in the image forming apparatus via an orthogonal reverse section in case a jam occurs inside the image forming apparatus. The image forming apparatus includes a main conveyance section to convey a sheet in the image forming apparatus and to convey the sheet to an ejected sheet section; an orthogonal reverse section to receive the sheet from the main conveyance section and turn over the sheet without swapping a front edge for a rear edge of the sheet by conveying the sheet in a direction perpendicular to a sheet conveyance direction of the main conveyance section and a sheet ejection section to eject the sheet in the orthogonal reverse section outside the orthogonal reverse section along a direction to turn over the sheet by the orthogonal reverse section. | 08-09-2012 |
20120217698 | SHEET REVERSING APPARATUS, IMAGE FORMING APPARATUS AND SHEET REVERSING METHOD - A sheet reversing apparatus including: a right angle reversing conveyance section which reverses front/back sides of a sheet while changing a conveyance direction of the sheet, being conveyed in a first conveyance direction, to a second conveyance direction perpendicular to the first conveyance direction; a sheet skew sensor which detects a sheet skew of the sheet being conveyed by the right angle reversing conveyance section; and a sheet skew correction mechanism which corrects the sheet skew of the sheet while the sheet is being conveyed by the right angle reversing conveyance section. | 08-30-2012 |
Patent application number | Description | Published |
20090001548 | Semiconductor package - A semiconductor package which includes: a semiconductor chip which includes a signal terminal for inputting and outputting electrical signals and a ground terminal; and a package substrate which includes a semiconductor chip mounting surface on which the semiconductor chip is mounted, and a terminal electrode forming surface on which a signal terminal electrode electrically connected to the signal terminal and a ground terminal electrode electrically connected to the ground terminal are arranged in an array pattern, wherein: on the semiconductor chip mounting surface, there is provided a first signal wiring connected to the signal terminal, a ground wiring connected to the ground terminal, and a ground conductive layer connected to the ground wiring and is provided in a planar pattern in an area excluding the forming area of the first signal wiring; on the terminal electrode forming surface, there is provided a second signal wiring connected to the signal terminal electrode, and a ground fine wiring connected to the ground terminal electrode; and the first signal wiring and the second signal wiring are connected via a conductor filled in a signal through hole penetrating the package substrate, and the ground conductive layer and the ground fine wiring are connected via a conductor filled in a ground through hole penetrating the package substrate. | 01-01-2009 |
20090086522 | ADDRESS LINE WIRING STRUCTURE AND PRINTED WIRING BOARD HAVING SAME - An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL | 04-02-2009 |
20090140766 | Signal transmission circuit and characteristic adjustment method thereof, memory module, and manufacturing method of circuit board - A signal transmission circuit comprising: first and second transmission lines connected to each other; a first impedance storage circuit storing an impedance of the first transmission line; and a control circuit that outputs match information between an impedance of the second transmission line and the impedance stored in the first impedance storage circuit. | 06-04-2009 |
20090219745 | MEMORY MODULE AND MEMORY DEVICE - In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip. | 09-03-2009 |
20100309706 | Load reduced memory module and memory system including the same - A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate. | 12-09-2010 |
20100312925 | Load reduced memory module - A memory module includes a plurality of data connectors provided along a long side of a module substrate, a plurality of memory chips and a plurality of data register buffers mounted on the module substrate, a data line that connects the data connectors and the data register buffers, and data lines that connect the data register buffers and the memory chips. Each of the data register buffers and a plurality of data connectors and a plurality of memory chips corresponding to the data register buffer are arranged side by side in a direction of a short side of the module substrate. According to the present invention, because each line length of the data lines is considerably shortened, it is possible to realize a considerably high data transfer rate. | 12-09-2010 |
20100312956 | Load reduced memory module - A memory module includes a plurality of memory chips and a plurality of data register buffers mounted on the module substrate. At least two memory chips are allocated to each of the data register buffers. Each of the data register buffers includes M input/output terminals (M is a positive integer equal to or larger than 1) that are connected to the data connectors via a first data line and N input/output terminals (N is a positive integer equal to or larger than 2M) that are connected to corresponding memory chips via second and third data lines, so that the number of the second and third data lines is N/M times the number of the first data lines. According to the present invention, because the load capacities of the second and third data lines are reduced by a considerable amount, it is possible to realize a considerably high data transfer rate. | 12-09-2010 |
20110141789 | MEMORY MODULE AND MEMORY SYSTEM - In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip. | 06-16-2011 |
20120127675 | APPARATUS HAVING A WIRING BOARD AND MEMORY DEVICES - An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL | 05-24-2012 |
20120250264 | MEMORY MODULE HAVING MEMORY CHIP AND REGISTER BUFFER - Disclosed herein is a memory module that includes a register buffer and a memory chip each mounted on a module substrate. Each of the command address output terminals belonging to the first group provided on the register buffer is connected to an associated one of the command address input terminals belonging to the first group provided on the memory chip through associated ones of the plurality of contact plugs and the first wiring layer. Each of the command address output terminals belonging to the second group provided on the register buffer is connected to an associated one of the command address input terminals belonging to the second group provided on the memory chip through associated ones of the plurality of contact plugs and the second wiring layer. | 10-04-2012 |
20120262974 | MEMORY MODULE AND MEMORY SYSTEM - In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip. | 10-18-2012 |
20130135916 | MEMORY MODULE INCLUDING PLURAL MEMORY DEVICES AND DATA REGISTER BUFFER - Disclosed herein is a memory module that includes a module substrate, data connectors, memory devices, and data register buffers. A first main surface of the module substrate has first and second memory mounting areas. One of the first and second main surfaces of the module substrate has a register mounting area located between the first and second memory mounting areas in a planner view. The memory devices include a plurality of first memory devices that are mounted on the first memory mounting area and a plurality of second memory devices that are mounted on the second memory mounting area. The data register buffers are mounted on the register mounting area. The data register buffers transfers write data supplied from the data connectors to the memory devices, and transfers read data supplied from the memory devices to the data connectors. | 05-30-2013 |
20130138898 | MEMORY MODULE INCLUDING PLURAL MEMORY DEVICES AND COMMAND ADDRESS REGISTER BUFFER - Disclosed herein is a memory module that includes a plurality of command address connectors formed on the module substrate, a plurality of memory devices mounted on the module substrate, and a plurality of command address register buffers mounted on the module substrate. The command address connectors receive a command address signal from outside. The memory devices include a plurality of first memory devices and a plurality of second memory devices. The command address register buffers include a first command address register buffer that supplies the command address signal to the first memory devices and a second command address register buffer that supplies the command address signal to the second memory devices. | 05-30-2013 |
20130163353 | SEMICONDUCTOR DEVICE HAVING ODT FUNCTION - Disclosed herein is a device that includes: a data strobe terminal; a data terminal; a first output driver coupled to the data strobe terminal; a second output driver coupled to the data terminal; and a data control circuit configured to enable the first and second output drivers to function as termination resistors in different timings from each other. | 06-27-2013 |
20130215659 | LOAD REDUCED MEMORY MODULE AND MEMORY SYSTEM INCLUDING THE SAME - A device includes a printed circuit board, a clock connector provided on the printed circuit board and configured to be supplied with a first clock signal, a first register buffer provided on the printed circuit board, coupled to the clock connector and, including a first clock generator that produces a second clock signal in response to the first clock signal, a plurality of data connectors, provided on the printed circuit board, a plurality of memory chips each provided on the printed circuit board and including a first data terminal, and a plurality of second register buffers each provided on the printed circuit board independently of the first register buffer. | 08-22-2013 |
20140001639 | SEMICONDUCTOR DEVICE HAVING SILICON INTERPOSER ON WHICH SEMICONDUCTOR CHIP IS MOUNTED | 01-02-2014 |
20140369148 | MEMORY MODULE AND MEMORY SYSTEM - In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip. | 12-18-2014 |