Patent application number | Description | Published |
20090108291 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device including a gate structure, two doped regions, and two buffer layers is provided. The gate structure is disposed on a substrate. The two doped regions are made of boron doped silicon germanium (SiGeB) and are disposed in the substrate at both sides of the gate structure. The two buffer layers are made of carbon doped silicon germanium (SiGeC) and are respectively disposed between the two doped regions and the substrate. | 04-30-2009 |
20100032715 | MOS TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating a MOS transistor is disclosed. First, a semiconductor substrate having a gate thereon is provided. A spacer is then formed on the sidewall of the gate, and two recesses are formed adjacent to the spacer and within the semiconductor substrate. Next, the spacer is thinned, and epitaxial layer is grown in each of the two recesses. By thinning the spacer before the epitaxial layer is formed, the present invention could stop the epitaxial layer to grow against the sidewall of the spacer, thereby preventing problem such as Ion degradation. | 02-11-2010 |
20110086479 | METHOD FOR SELECTIVE FORMATION OF TRENCH - A method for selective formation of trenches is disclosed. First, a substrate is provided. The substrate includes a first semiconductor element and a second semiconductor element. The first semiconductor element has a dopant. Second, a wet etching procedure is carried out to selectively form a pair of trenches in the substrate around the second semiconductor element, a first source/drain ion implantation is selectively carried out on the first semiconductor element, or a second source/drain ion implantation is selectively carried out on the second semiconductor element. | 04-14-2011 |
Patent application number | Description | Published |
20100041194 | SEMICONDUCTOR DEVICE WITH SPLIT GATE MEMORY CELL AND FABRICATION METHOD THEREOF - A split gate memory cell. First and second well regions of respectively first and second conductivity types are formed in the substrate. A floating gate is disposed on a junction of the first and second well regions and insulated from the substrate. A control gate is disposed over the sidewall of the floating gate and insulated from the substrate and the floating gate and partially extends to the upper surface of the floating gate. A doping region of the first conductivity type is formed in the second well region. The first well region and the doping region respectively serve as source and drain regions of the split gate memory cell. | 02-18-2010 |
20130076335 | INTEGRATED CIRCUIT INCLUDING A VOLTAGE DIVIDER AND METHODS OF OPERATING THE SAME - An integrated circuit includes at least one FLASH memory array and at least one capacitor array disposed over a substrate. The at least one capacitor array includes a plurality of capacitor cell structures. The capacitor cell structures each includes a first capacitor electrode disposed over the substrate. A second capacitor electrode is disposed over the first capacitor electrode. A third capacitor electrode is disposed adjacent to first sidewalls of the first and second capacitor electrodes. A fourth capacitor electrode is disposed adjacent to second sidewalls of the first and second capacitor electrodes. | 03-28-2013 |
20140021584 | PROCESS-COMPATIBLE DECOUPLING CAPACITOR AND METHOD FOR MAKING THE SAME - Provided is decoupling capacitor device. The decoupling capacitor device includes a first dielectric layer portion that is deposited in a deposition process that also deposits a second dielectric layer portion for a non-volatile memory cell. Both portions are patterned using a single mask. A system-on-chip (SOC) device is also provided, the SOC include an RRAM cell and a decoupling capacitor situated in a single inter-metal dielectric layer. Also a method for forming a process-compatible decoupling capacitor is provided. The method includes patterning a top electrode layer, an insulating layer, and a bottom electrode layer to form a non-volatile memory element and a decoupling capacitor. | 01-23-2014 |
20140307510 | INTEGRATED CIRCUIT INCLUDING A VOLTAGE DIVIDER AND METHODS OF OPERATING THE SAME - An integrated circuit includes at least one memory array and at least one capacitor array over a substrate. The at least one capacitor array includes a plurality of capacitor cell structures. The capacitor cell structures of the plurality of cell structures comprise a first capacitor electrode over the substrate. A second capacitor electrode is over the first capacitor electrode. A third capacitor electrode is adjacent to first sidewalls of the first and second capacitor electrodes. A fourth capacitor electrode is adjacent to second sidewalls of the first and second capacitor electrodes. A fifth capacitor electrode is over the substrate and adjacent to the fourth capacitor electrode. | 10-16-2014 |