Patent application number | Description | Published |
20130173974 | COMPUTER MEMORY TEST STRUCTURE - A method and apparatus for a computer memory test structure. An embodiment of a method for testing of a memory board includes testing a memory of the memory board, where testing the memory including use of a built-in self-test structure to provide a first test pattern for the memory. The method further includes testing an IO (input output) interface of the memory with a host, where testing of the IO interface includes use of the built-in self-test structure to provide a second test pattern for the IO interface. | 07-04-2013 |
20140026006 | MULTI-SITE TESTING OF COMPUTER MEMORY DEVICES AND SERIAL IO PORTS - A method and apparatus for multi-site testing of computer memory devices. An embodiment of a method of testing computer memory devices includes coupling multiple memory devices, each memory device having a serializer output and a deserializer input, wherein the serializer output of a first memory device is coupled with a deserializer input of one or more of the memory devices of the plurality of memory devices. The method further includes producing test signal patterns using a test generator of each memory device, serializing the test signal pattern at each memory device, and transmitting the serialized test pattern for testing of the memory devices, wherein testing of the memory devices includes a first test mode and a second test mode. | 01-23-2014 |
20140062606 | TEST SOLUTION FOR RING OSCILLATORS - A method and apparatus is disclosed herein for testing of multiple ring oscillators. In one embodiment, the apparatus comprises at least one ring oscillator structure having a ring oscillator having an inverter chain with an odd number of inverters connected back-to-back and operable to produce an oscillatory output, and a test structure coupled to provide either an observability chain input or a test input to the ring oscillator and to receive the oscillatory output as a feedback from the ring oscillator. | 03-06-2014 |
20140115414 | COMPUTER MEMORY TEST STRUCTURE - A method and apparatus for a computer memory test structure. An embodiment of a method for testing of a memory board includes testing a memory of the memory board, where testing the memory including use of a built-in self-test structure to provide a first test pattern for the memory. The method further includes testing an IO (input output) interface of the memory with a host, where testing of the IO interface includes use of the built-in self-test structure to provide a second test pattern for the IO interface. | 04-24-2014 |
20140191813 | Test Solution for a Random Number Generator - A random number generator and method for testing the same are described. In one embodiment, the random number generator comprises one or more ring oscillator structures, each of the one or more ring oscillator structures having a ring oscillator for use in generating random numbers and having a test structure to reconfigure the ring oscillator into a testable structure. | 07-10-2014 |
Patent application number | Description | Published |
20080222471 | CIRCUITRY TO PREVENT PEAK POWER PROBLEMS DURING SCAN SHIFT - In some embodiments, a chip includes first and second scan chain segments each including registers and multiplexers to provide to the registers scan input signals during scan input periods and captured output signals during a capture periods. The chip also includes circuitry to provide first and second test clock signals to the registers of the first and second scan chain segments, respectively, wherein the second test clock signal is provided by a different signal path in the circuitry during the scan input periods than during the capture periods, and during the scan input periods the second test clock signal is skewed with respect to the first test clock signal. Other embodiments are described and claimed. | 09-11-2008 |
20100188097 | FAULT TESTING FOR INTERCONNECTIONS - Embodiments of the invention are generally directed to fault testing for interconnections. An embodiment of a fault analysis apparatus includes a test pattern source to provide a test pattern for an interconnection between a transmitter and a receiver, the interconnection having a transmitter end and a receiver end, the interconnection including a first wire and a second wire, the transmitter transmitting the test pattern on the first wire to the receiver. The apparatus further includes a first switch to open and close a first connection for the first wire, and a second switch to open and close a second connection for the second wire. The first switch and the second switch are to be set according to a configuration to set at least a portion of a test path for the detection of one or more faults in the interconnection. | 07-29-2010 |
20110004793 | COMPUTER MEMORY TEST STRUCTURE - A method and apparatus for a computer memory test structure. An embodiment of a method for testing of a memory board includes testing a memory of the memory board, where testing the memory including use of a built-in self-test structure to provide a first test pattern for the memory. The method further includes testing an IO (input output) interface of the memory with a host, where testing of the IO interface includes use of the built-in self-test structure to provide a second test pattern for the IO interface. | 01-06-2011 |
20110167308 | MULTI-SITE TESTING OF COMPUTER MEMORY DEVICES AND SERIAL IO PORTS - A method and apparatus for multi-site testing of computer memory devices. An embodiment of a method of testing computer memory devices includes coupling multiple memory devices, each memory device having a serializer output and a deserializer input, wherein the serializer output of a first memory device is coupled with a deserializer input of one or more of the memory devices of the plurality of memory devices. The method further includes producing test signal patterns using a test generator of each memory device, serializing the test signal pattern at each memory device, and transmitting the serialized test pattern for testing of the memory devices, wherein testing of the memory devices includes a first test mode and a second test mode. | 07-07-2011 |
20120081138 | TESTING OF HIGH-SPEED INPUT-OUTPUT DEVICES - Embodiments of the invention are generally directed to testing of high-speed input-output devices. An embodiment of a high-speed input-output apparatus includes a transmitter and a receiver, and a loop-back connection from an output of the transmitter to an input of the receiver, the loop-back connection including a first connector and a second connector for transmission of differential signals. The apparatus further includes a first inductor having a first terminal and a second terminal and second inductor having a first terminal and a second terminal, the first terminal of the first inductor being connected to the first connector and the first terminal of the second inductor being connected to the second connector, the second terminal of the first inductor and the second terminal of the second inductor providing a test access port for direct current testing of the apparatus. | 04-05-2012 |
20120158346 | IDDQ TESTING OF CMOS DEVICES - IDDQ testing of CMOS devices. An embodiment of a method includes applying a test pattern of inputs to a device, the device including one or more CMOS (Complementary Metal-Oxide Semiconductor) transistors, and obtaining current measurements for the device, each of the current measurements being a measurement of a current after applying an input of the test pattern to the device. A filter function is applied to the current measurements, applying the filter function including separating defect current values from the current measurements. The method further includes determining whether a defect is present in the device based at least in part on a comparison of the defect current values with a threshold value. | 06-21-2012 |
Patent application number | Description | Published |
20110275699 | Treatment For Obesity And Diabetes - The present disclosure relates to strategies aimed at treating/preventing obesity and diabetes. In particular, obesity is a major public health problem, associated with detrimental metabolic consequences such as diabetes, cardiovascular disease, stroke, osteoarthritis and even some types of cancer. Thus, application of DNA-PK inhibitors, that has been connected to the signaling pathway involved in the formation of fat from carbohydrate in the liver, could potentially be a pharmacological target for regulation of obesity and diabetes due to a diet high in carbohydrates. Therefore, the invention finds application in the fields of obesity, diabetes, and lipogenesis research and therapy. | 11-10-2011 |
20140147431 | Compositions and Methods for Modulating Desnutrin-Mediated Adipocyte Lipolysis - The present disclosure provides methods of converting white adipose tissue to brown adipose tissue in an individual, generally involving modulating desnutrin-mediated lipolysis in adipocytes in the individual. The present disclosure further provides methods for treating obesity. The present disclosure further provides methods of identifying an agent that increases the level and/or activity of desnutrin in an adipocyte. | 05-29-2014 |
Patent application number | Description | Published |
20100041025 | Compositons, methods and kits for real-time nucleic acid analysis in live cells - The present invention includes compositions, methods and kits for the real-time detection of transcription and translation in live cells, tissues and organisms. The present invention further provides method for the rapid sequencing of nucleic acids without using conventional sequencing techniques or reactions. | 02-18-2010 |
20100203629 | Cytoplasmic BKca Channel Intron-Containing mRNAs Contribute to the Intrinsic Excitability of Hippocampal Neurons - The invention relates to a method of modulating neuronal function by modulating the cytoplasmic level in a neuron of an intron-containing mRNA. The methods are useful in diagnostic, research and therapeutic applications. | 08-12-2010 |
20100216652 | Low Level Fluorescence Detection at the Light Microscopic Level - The present invention discloses methods of removing unwanted fluorescence from a sample by photobleaching said sample to enhance detection of proteins and fragments thereof, polynucleotides and fragments thereof, and biomolecules and fragments thereof in a sample by contacting said proteins, polynucleotides and biomolecules with a fluorescent reporter, wherein said fluorescent reported comprises a fluorescent semiconductor crystal or SCN, wherein said SCN further comprises a targeting moiety. | 08-26-2010 |
20110033934 | Transcriptome Transfer Produces Cellular Phenotype Conversion - The present invention includes methods for effecting phenotype conversion in a cell by transfecting the cell with phenotype-converting nucleic acid. Expression of the nucleic acids results in a phenotype conversion in the transfected cell. Preferably the phenotype-converting nucleic acid is a transcriptome, and more preferably an mRNA transcriptome. | 02-10-2011 |
20120135493 | Methods for Phototransfecting Nucleic Acids Into Live Cells - The present invention includes methods for transferring a multigenic phenotype to a cell by transfecting, preferably by phototransfection, and locally transfecting a cell or a cellular process with a laser while the cell is bathed in a fluid medium comprising two or more nucleic acids, thereby introducing the nucleic acid into the interior of the cell. Expression of the nucleic acids results in a multigenic phenotype in the tranfected cell. | 05-31-2012 |
20120178167 | Methods for Transfecting Nucleic Acid Into Live Cells - The present invention includes methods for transferring a multigenic phenotype to a cell by transfecting, preferably by phototransfection, and locally transfecting a cell or a cellular process with a laser while the cell is bathed in a fluid medium comprising two or more nucleic acids, thereby introducing the nucleic acid into the interior of the cell. Expression of the nucleic acids results in a multigenic phenotype in the tranfected cell. | 07-12-2012 |
20140206059 | Transcriptome Transfer Produces Cellular Phenotype Conversion - The present invention includes methods for effecting phenotype conversion in a cell by transfecting the cell with phenotype-converting nucleic acid. Expression of the nucleic acids results in a phenotype conversion in the transfected cell. Preferably the phenotype-converting nucleic acid is a transcriptome, and more preferably an mRNA transcriptome. | 07-24-2014 |