Patent application number | Description | Published |
20100040169 | CODING METHODS AND SYSTEMS FOR IMPROVED ERROR MARGINS - Each symbol in a sequence of codewords is expressed as a voltage level representative of a one or zero, and each codeword includes both levels. Sense amplifiers at the receiver compare all pairs of symbols in each codeword. Comparisons based upon like symbol values provide mid-range sensed voltages, and comparisons based upon disparate symbols values provide relatively higher or lower sensed voltages. Sampling the high and low voltages produces determinate sample values, whereas sampling the midrange voltage produces indeterminate sample values. Sampling the sensed voltages thus produces a mix of indeterminate and determinate values for each codeword. Codewords are selected such that the number and placement of the determinate sample values identify each codeword, and subsequent codewords are selected so the nodes supporting the high and low sensed voltages sampled to obtain the determinate sample values transitioned to their current voltage from either the intermediate voltage or did not transition. | 02-18-2010 |
20100265109 | ENCODING AND DECODING TECHNIQUES FOR BANDWIDTH-EFFICIENT COMMUNICATION - An encoder encodes data into parallel codewords. Each codeword is expressed as a set of logic 0s and a set of logic 1s on two sets of output nodes. The encoder selects a current codeword which differs from the immediately preceding codeword by a fixed number of zero-to-one transitions on the first set of nodes and a fixed number of one-to-zero transitions on the second set of nodes. The current codeword is selected such that the first and second sets of nodes are different than additional nodes that contain transitions between the immediately preceding codeword and a bi-preceding codeword, and that logic values on additional nodes are unchanged between immediately preceding codeword and current codeword. A decoder decodes the codewords by comparing symbols on node pairs other than those for which transitions were expressed in the preceding code word, and decoding the results of those comparisons. | 10-21-2010 |
20110018599 | Partial Response Receiver And Related Method - A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal. | 01-27-2011 |
20110025533 | ENCODING DATA WITH MINIMUM HAMMING WEIGHT VARIATION - M-bit data are encoded into n-bit data such that the encoded n-bit data has a sufficient number of encoded data patterns enough to encode the number (2 | 02-03-2011 |
20110029801 | Method and System for Balancing Receive-Side Supply Load - Described are digital communication systems that transmit and receive parallel sets of data symbols. Differences between successive sets of symbols induce changes in the current used to express the symbol sets, and thus introduce supply ripple. A receiver adds compensation current to reduce supply ripple. The compensation current is calculated based upon prior data samples rather than the current symbols, and consequently increases the maximum instantaneous current fluctuations between adjacent symbol sets as compared with circuits that do not include the compensation. The frequency response of the power-distribution network filters out the increased data dependence of the local supply current, however, and consequently reduces the fluctuations of total supply current. Some embodiments provide compensation currents for both transmitted and received symbols. | 02-03-2011 |
20110228864 | RESONANCE MITIGATION FOR HIGH-SPEED SIGNALING - The frequency response of a first component signal path of a differential signaling link is adjusted to off-set a notch in the frequency response from a corresponding notch in the frequency response of a second component signal path of the differential signaling link. | 09-22-2011 |
20110239084 | CODE-ASSISTED ERROR-DETECTION TECHNIQUE - Embodiments of a circuit are described. In this circuit, an encoder circuit encodes a set of N symbols as a given codeword in a code space, where the given codeword includes a set of M symbols. M drivers are coupled to the encoder circuit and are coupled to M links in a channel, where a given driver outputs a given symbol in the set of M symbols onto a given link. Moreover, an error-detection circuit, which is coupled to the encoder circuit, generates and stores error-detection information associated with the set of M symbols, where the error-detection information facilitates subsequent probabilistic determination of a type of error during communication of the set of M symbols to another circuit. Additionally, a receiver circuit receives feedback information from the other circuit. This feedback information includes error information about detection of another type of error in the set of M symbols based on characteristics of the code space. Furthermore, control logic performs remedial action based on the feedback information. | 09-29-2011 |
20120131244 | Encoding Data Using Combined Data Mask and Data Bus Inversion - A data encoding scheme for transmission of data from one circuit to another circuit combines DBI encoding and non-DBI encoding and uses a data mask signal to indicate the type of encoding used. The data mask signal in a first state indicates that the data transmitted from one circuit to said another circuit is to be ignored, and the data mask signal in a second state indicates that the data transmitted from one circuit to said another circuit is not to be ignored. If the data mask signal is in the second state, a first subset of the data is encoded with data bus inversion and a second subset of the data is encoded differently from data bus inversion. Such encoding has the advantage that SSO noise is dramatically reduced when the encoded data is transmitted from one circuit to another circuit. | 05-24-2012 |
20120206280 | Multiple Word Data Bus Inversion - A data encoding scheme for transmission of data from one circuit to another circuit considers the Hamming Weight of combined multiple words to determine whether to invert or not invert an individual word to be transmitted. The multi-word data encoding scheme performs DBI encoding with data inversion conducted based on the total HW in the combined multiple words. The decision to invert or not invert each of the multiple words is made based on the sum of the individual Hamming Weights of each of the words. Such encoding has the advantage that SSO noise is dramatically reduced when the encoded data has a large number of words transmitted from one circuit to another circuit over a wide parallel bus. | 08-16-2012 |
20130051162 | CODED DIFFERENTIAL INTERSYMBOL INTERFERENCE REDUCTION - Encoder and decoder circuits that encode and decode a series of data words to/from a series of code words. The data words include L symbols. The code words include M symbols, where M is larger than L. A set of tightly coupled M links to convey respective symbols in each of the series of code words. The code words are selected such that between every two consecutive code words in a series of code words, an equal number of transitions from low to high and high to low occur on a subset of the M-links. | 02-28-2013 |
20130300482 | PARTIAL RESPONSE RECEIVER AND RELATED METHOD - A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal. | 11-14-2013 |
20140247911 | Partial Response Receiver And Related Method - A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal. | 09-04-2014 |