Guo, San Jose
Chen Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20150188313 | TIE-OFF CIRCUIT WITH OUTPUT NODE ISOLATION FOR PROTECTION FROM ELECTROSTATIC DISCHARGE (ESD) DAMAGE - Embodiments relate to electrostatic discharge (ESD) protection. One embodiment includes a tie-off circuit including a multiple field effect transistors (FETs), a first internal node, a second internal node, a first output node and a second output node. A node isolation circuit is connected to the first output node and the second output node of the tie-off circuit. The node isolation circuit includes a first FET with a third output node and a second FET with a fourth output node. The third output node and the fourth output node are electrically isolated from the first internal node and the second internal node. | 07-02-2015 |
20150363205 | IMPLEMENTING OUT OF ORDER PROCESSOR INSTRUCTION ISSUE QUEUE - A method and apparatus are provided for implementing an enhanced out of order processor instruction issue queue in a computer system. Instructions are selectively accepted into an instruction issue queue and ages are assigned to the accepted queue entry instructions using a queue counter. The queue entry instructions are issued based upon resources being ready and ages of the instructions. Ages of the queue entry instructions and the queue counter are selectively decremented, responsive to issuing instructions. | 12-17-2015 |
20150363206 | IMPLEMENTING OUT OF ORDER PROCESSOR INSTRUCTION ISSUE QUEUE - A method and apparatus are provided for implementing an enhanced out of order processor instruction issue queue in a computer system. Instructions are selectively accepted into an instruction issue queue and ages are assigned to the accepted queue entry instructions using a queue counter. The queue entry instructions are issued based upon resources being ready and ages of the instructions. Ages of the queue entry instructions and the queue counter are selectively decremented, responsive to issuing instructions. | 12-17-2015 |
Fei Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20150301843 | Content-Based Swap Candidate Selection - Techniques for building a list of swap candidate pages for host swapping are provided. In one embodiment, a host system can determine a swap target virtual machine (VM) and a target number of swap candidate pages. The host system can further select a memory page from a memory space of the swap target VM and can check whether the memory page is sharable or compressible. If the memory page is sharable or compressible, the host system can add the memory page to the list of swap candidate pages. | 10-22-2015 |
20150301946 | Page Compressibility Checker - Techniques for checking the compressibility of a memory page that is allocated to a virtual machine (VM) running on a host system are provided. In one embodiment, the host system can determine a compression ratio for the memory page by compressing the memory page using a first compression algorithm. The host system can then compare the compression ratio to a threshold. If the compression ratio does not exceed the threshold, the host system can predict that the memory page is compressible by a second compression algorithm that is distinct from the first compression algorithm. On average, the second compression algorithm can be slower, but achieve a lower compression ratio, than the first compression algorithm. | 10-22-2015 |
Frank Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20150117119 | MEMORY CIRCUITRY WITH WRITE ASSIST - Memory circuitry is provided with write assist circuitry for generating a lower power supply voltage during write operations. The write assist circuitry includes a plurality of series connected switches including a header switch and a footer switch. Header bias circuitry generates a header bias voltage and footer bias circuitry generates a footer bias voltage. The header bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. The footer bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. During write operation target bit cells to be written are supplied with the power via a current path through the header switch while these are respectively controlled by the header bias voltage and the footer bias voltage. | 04-30-2015 |
Haitao Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20090168898 | VIDEO CODING SYSTEM PROVIDING SEPARATE CODING CHAINS FOR DYNAMICALLY SELECTED SMALL-SIZE OR FULL-SIZE PLAYBACK - Embodiments of the present invention provide a coding system that codes data according to a pair of coding chains. A first coding chain generates coded video data that can be decoded by itself to represent a source video sequence of a small size, such as a size sufficient to support the real time playback and display features of a video editing application. The second coding chain generates coded video data representing supplementary data, which when decoded in conjunction with the coded video data of the first coding chain, yields the source video sequence for full-size display. The output of the first coding chain may be stored in memory in a file structure that can be accessed independently of the second chain's output and, therefore, it facilitates real time decoding and playback. | 07-02-2009 |
20090169124 | VIDEO CODING SYSTEM PROVIDING SEPARATE CODING CHAINS FOR DYNAMICALLY SELECTED SMALL-SIZE OR FULL-SIZE PLAYBACK - Embodiments of the present invention provide a coding system that codes data according to a pair of coding chains. A first coding chain generates coded video data that can be decoded by itself to represent a source video sequence of a small size, such as a size sufficient to support the real time playback and display features of a video editing application. The second coding chain generates coded video data representing supplementary data, which when decoded in conjunction with the coded video data of the first coding chain, yields the source video sequence for full-size display. The output of the first coding chain may be stored in memory in a file structure that can be accessed independently of the second chain's output and, therefore, it facilitates real time decoding and playback. | 07-02-2009 |
20090257507 | SYSTEM AND METHOD FOR MASKING VISUAL COMPRESSION ARTIFACTS IN DECODED VIDEO STREAMS - A technique is provided for processing decoded video data to mask visual compression artifacts resulting from video compression. In accordance with this technique, a hardware block is provided for generating and adding random noise to the decoded video stream. In one embodiment, a random number is generated for each pixel of the decoded video data and compared against one or more threshold values to determine a threshold range. In such an embodiment, a noise addend value is selected based upon the threshold comparison and summed with the current pixel. While the present technique may not eliminate the compression artifacts, the addition of random noise renders the compression artifacts less noticeable to the human eye and, therefore, more aesthetically pleasing to a viewer. | 10-15-2009 |
20100039530 | Apparatus and Method for Compensating for Variations in Digital Cameras - A method of manufacturing a digital video camera is provided. The method comprises acquiring video images of colored light, and measuring a light intensity response of the video camera to the colored light. The method further comprises comparing the intensity of the measured response to a desired colored light intensity for determining a color intensity bias and storing the intensity bias for the colored light in the camera so that the bias can be applied when the camera is operating at an arbitrary lighting condition. | 02-18-2010 |
20100238176 | SYSTEMS, METHODS, AND DEVICES FOR FLASH EXPOSURE CONTROL USING PREFLASH STATISTICS - Techniques for accomplishing transitions between graphical data representations (e.g., charts, graphs, and so forth) are disclosed. In accordance with these techniques, each object in such a graphical data representation is individually manipulable during transitions. In certain embodiments, the presence of an object in both the outgoing and incoming graphical data representation may be taken into account during a transition. In such embodiments, differences between the objects in the outgoing and incoming graphical data representation may be addressed by the respective transition. | 09-23-2010 |
20100309321 | IMAGE CAPTURING DEVICES USING ORIENTATION DETECTORS TO IMPLEMENT AUTOMATIC EXPOSURE MECHANISMS - Several methods and apparatuses for implementing automatic exposure mechanisms for image capturing devices are described. In one embodiment, an orientation detector located in the device determines orientation data for the device. The automatic exposure mechanism projects an orientation vector into an image plane of an image sensor. Next, the automatic exposure mechanism adjusts an initial position of a metering area used for automatic exposure towards a target position based on the projected orientation vector. The automatic exposure mechanism optionally dampens the adjustment of the metering area. | 12-09-2010 |
20110249075 | Remote Control Operations in a Video Conference - Some embodiments provide a method for allowing a first device that is in a video conference with a second mobile device to remotely control the second mobile device. The method sends images captured by a camera of the first device to the second device. The method receives images captured by a camera of the second device. The method sends a command through a communication channel of a real-time communication session to the second device. The command is for instructing the second device to perform an operation that modifies the images captured by the camera of the second device. | 10-13-2011 |
20110249086 | Image Processing for a Dual Camera Mobile Device - Some embodiments provide a method of processing images for a first camera and a second camera of a mobile device using a shared pipeline. A method receives a first set of images captured by the first camera of the mobile device. The method processes the first set of images using a first configuration of the shared pipeline. The method also receives a second set of images captured by the second camera of the mobile device, and processes the second set of images using a second configuration of the shared pipeline different from the first configuration. | 10-13-2011 |
20110298933 | DUAL PROCESSING OF RAW IMAGE DATA - Systems, methods, and devices for dual processing of raw image data by main image processing and alternative image processing capabilities of an electronic device are provided. According to an embodiment, alternative image processing may analyze a first copy of a frame of raw image data before a second copy of the frame of raw image data is processed by main image processing. Thereafter, the main image processing may process the second copy of the frame of raw image. The main image processing may be calibrated based at least in part on the analysis of the first copy of the frame of raw image data. | 12-08-2011 |
20110298944 | ADAPTIVE LENS SHADING CORRECTION - Systems, methods, and devices for applying lens shading correction to image data captured by an image sensor are provided. In one embodiment, multiple lens shading adaptation functions, each modeled based on the response of a color channel to a reference illuminant, are provided. An image frame from the image data may be analyzed to select a lens shading adaptation function corresponding to a reference illuminant that most closely matches a current illuminant. The selected lens shading function may then be used to adjust a set of lens shading parameters. | 12-08-2011 |
20110298945 | COMPENSATION FOR BLACK LEVEL CHANGES - A technique for applying black level compensation to image data is provided. In one embodiment, an image processing system includes a first image processing pipeline configured to receive frames of image data generated by an image sensor and to alter the frames of image data to compensate for black level shift. The image processing system may also include a feed-forward loop having a second image processing pipeline configured to receive at least one of the frames of image data, to process the at least one frame, and to adjust a black level compensation parameter of the first image processing pipeline. Additional methods, systems, and devices relating to black level compensation are also disclosed. | 12-08-2011 |
20110298947 | SYSTEMS, METHODS, AND DEVICES FOR FLASH EXPOSURE CONTROL USING PREFLASH STATISTICS - Systems, methods, and devices for obtaining a properly exposed strobe-illuminated image are provided. One method for doing so may include, for example, gathering image capture statistics during a first period when a strobe is not emitting light and during a second period when the strobe emits a preflash. These image capture statistics may include distinct image capture control statistics and luma values associated with the periods. Final image capture control statistics then may be determined based at least in part on the first luma value normalized to the first image capture control statistics and the second luma value normalized to the second image capture control statistics. Thereafter, the final image capture control statistics may be used to capture a properly exposed strobe-illuminated image when the strobe emits a main flash. | 12-08-2011 |
20120188402 | APPARATUS AND METHOD FOR COMPENSATING FOR VARIATIONS IN DIGITAL CAMERAS - A method of manufacturing a digital video camera is provided. The method comprises acquiring video images of colored light, and measuring a light intensity response of the video camera to the colored light. The method further comprises comparing the intensity of the measured response to a desired colored light intensity for determining a color intensity bias and storing the intensity bias for the colored light in the camera so that the bias can be applied when the camera is operating at an arbitrary lighting condition. | 07-26-2012 |
20130039432 | SYSTEM AND METHOD FOR MASKING VISUAL COMPRESSION ARTIFACTS IN DECODED VIDEO STREAMS - A technique is provided for processing decoded video data to mask visual compression artifacts resulting from video compression. In accordance with this technique, a hardware block is provided for generating and adding random noise to the decoded video stream. In one embodiment, a random number is generated for each pixel of the decoded video data and compared against one or more threshold values to determine a threshold range. In such an embodiment, a noise addend value is selected based upon the threshold comparison and summed with the current pixel. While the present technique may not eliminate the compression artifacts, the addition of random noise renders the compression artifacts less noticeable to the human eye and, therefore, more aesthetically pleasing to a viewer. | 02-14-2013 |
20130222608 | IMAGING SENSOR ANOMALOUS PIXEL COLUMN DETECTION AND CALIBRATION - An imaging sensor is signaled to capture a digital image of a dark scene. For each of the pixel columns in the image, a respective column value is computed that represents at least some of the pixels in the column. For each of the pixel columns in the image, a respective comparison is made between the respective column value of the pixel column and a reference value. A respective column score is computed, for each of the pixel columns, based on the respective comparison. An indication that identifies one or more of the pixel columns as anomalous is stored, when the respective column score of the one or more the pixel columns does not meet a criterion. Other embodiments are also described and claimed. | 08-29-2013 |
20130300884 | IMAGE CAPTURING DEVICES USING ORIENTATION DETECTORS TO IMPLEMENT AUTOMATIC EXPOSURE MECHANISMS - Several methods and apparatuses for implementing automatic exposure mechanisms for image capturing devices are described. In one embodiment, an orientation detector located in the device determines orientation data for the device, The automatic exposure mechanism projects an orientation vector into an image plane of an image sensor, Next, the automatic exposure mechanism adjusts an initial position of a metering area used for automatic exposure towards a target position based on the projected orientation vector. The automatic exposure mechanism optionally dampens the adjustment of the metering area. | 11-14-2013 |
20130301740 | VIDEO NOISE INJECTION SYSTEM AND METHOD - A technique is provided for processing decoded video data to mask visual compression artifacts resulting from video compression. In accordance with this technique, a hardware block is provided for generating and adding random noise to the decoded video stream. In one embodiment, a random number is generated for each pixel of the decoded video data and compared against one or more threshold values to determine a threshold range. In such an embodiment, a noise addend value is selected based upon the threshold comparison and summed with the current pixel. While the present technique may not eliminate the compression artifacts, the addition of random noise renders the compression artifacts less noticeable to the human eye and, therefore, more aesthetically pleasing to a viewer. | 11-14-2013 |
20130321671 | SYSTEMS AND METHOD FOR REDUCING FIXED PATTERN NOISE IN IMAGE DATA - The present disclosure generally relates to systems and methods for image data processing. In certain embodiments, an image processing pipeline may be configured to receive a frame of the image data having a plurality of pixels acquired using a digital image sensor. The image processing pipeline may then be configured to determine a first plurality of correction factors that may correct each pixel in the plurality of pixels for fixed pattern noise. The first plurality of correction factors may be determined based at least in part on fixed pattern noise statistics that correspond to the frame of the image data. After determining the first plurality of correction factors, the image processing pipeline may be configured to configured to apply the first plurality of correction factors to the plurality of pixels, thereby reducing the fixed pattern noise present in the plurality of pixels. | 12-05-2013 |
20130321672 | SYSTEMS AND METHODS FOR COLLECTING FIXED PATTERN NOISE STATISTICS OF IMAGE DATA - The present disclosure generally relates to systems and methods for image data processing. In certain embodiments, an image processing pipeline may collect statistics associated with fixed pattern noise of image data by receiving a first frame of the image data comprising a plurality of pixels. The image processing pipeline may then determine a sum of a first plurality of pixel values that correspond to at least a first portion of the plurality of pixels such that each pixel in at least the first portion of the plurality of pixels is disposed along a first axis within the frame of the image data. After determining the sum of the first plurality of pixel values, the image processing pipeline may store the sum of the first plurality of pixel values in a memory such that the sum of the first plurality of pixel values represent the statistics. | 12-05-2013 |
20130329075 | DYNAMIC CAMERA MODE SWITCHING - A method for automatic image capture control and digital imaging is described. An image buffer is initialized to store a digital image produced by an image sensor, through allocation of a region in memory for the buffer that is large enough to store a full resolution frame from the image sensor. While non-binning streaming frames, from the sensor and in the buffer, are being displayed in preview, the sensor is reconfigured into binning mode, and then binned streaming frames are processed in the buffer, but without allocating a smaller region in memory for the buffer. Other embodiments are also described and claimed. | 12-12-2013 |
20130329135 | REAL TIME DENOISING OF VIDEO - A video enhancement processing system improves perceptual quality of video data with limited processing complexity. The system may perform spatial denoising using filter weights that may vary based on estimated noise of an input image. Specifically, estimated noise of the input image may alter a search neighborhood over which the denoising filter operates, may alter a profile of weights to be applied based on pixel distances and may alter a profile of weights to be applied based on similarity of pixels for denoising processes. As such, the system finds application in consumer devices that perform such enhancement techniques in real time using general purpose processors such as CPUs or GPUs. | 12-12-2013 |
20130329809 | SYNC FRAME RECOVERY IN REAL TIME VIDEO TRANSMISSION SYSTEM - An error recovery method may be engaged by an encoder to recover from misalignment between reference picture caches at the encoder and decoder. When a communication error is detected between a coder and a decoder, a number of non-acknowledged reference frames present in the decoder's reference picture cache may be estimated. Thereafter, frames may be coded as reference frames in a number greater or equal to the number of non-acknowledged reference frames that are estimated to be present in the decoder's reference picture cache. Thereafter, ordinary coding operations may resume. Typically, a final reference frame that is coded in the error recovery mode will be coded as a synchronization frame that has high coding quality. The coded reference frames that precede it may be coded at low quality (or may be coded as SKIP-coded frames). On reception and decoding, the preceding frames may cause the decoder to flush from its reference picture cache any non-acknowledged reference frames that otherwise might collide with the new synchronization frame. In this manner, alignment between the encoder and decoder may be restored. | 12-12-2013 |
20130342739 | Dual Processing of Raw Image Data - Systems, methods, and devices for dual processing of raw image data by main image processing and alternative image processing capabilities of an electronic device are provided. According to an embodiment, alternative image processing may analyze a first copy of a frame of raw image data before a second copy of the frame of raw image data is processed by main image processing. Thereafter, the main image processing may process the second copy of the frame of raw image. The main image processing may be calibrated based at least in part on the analysis of the first copy of the frame of raw image data. | 12-26-2013 |
20140285709 | SYSTEMS, METHODS, AND DEVICES FOR FLASH EXPOSURE CONTROL USING PREFLASH STATISTICS - Systems, methods, and devices for obtaining a properly exposed strobe-illuminated image are provided. One method for doing so may include, for example, gathering image capture statistics during a first period when a strobe is not emitting light and during a second period when the strobe emits a preflash. These image capture statistics may include distinct image capture control statistics and luma values associated with the periods. Final image capture control statistics then may be determined based at least in part on the first luma value normalized to the first image capture control statistics and the second luma value normalized to the second image capture control statistics. Thereafter, the final image capture control statistics may be used to capture a properly exposed strobe-illuminated image when the strobe emits a main flash. | 09-25-2014 |
20150245004 | USER INTERFACE AND GRAPHICS COMPOSITION WITH HIGH DYNAMIC RANGE VIDEO - A method and system for adaptively mixing video components with graphics/UI components, where the video components and graphics/UI components may be of different types, e.g., different dynamic ranges (such as HDR, SDR) and/or color gamut (such as WCG). The mixing may result in a frame optimized for a display device's color space, ambient conditions, viewing distance and angle, etc., while accounting for characteristics of the received data. The methods include receiving video and graphics/UI elements, converting the video to HDR and/or WCG, performing statistical analysis of received data and any additional applicable rendering information, and assembling a video frame with the received components based on the statistical analysis. The assembled video frame may be matched to a color space and displayed. The video data and graphics/UI data may have or be adjusted to have the same white point and/or primaries. | 08-27-2015 |
Haitao (harry) Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20100309975 | IMAGE ACQUISITION AND TRANSCODING SYSTEM - A method and system are provided to encode a video sequence into a compressed bitstream. An encoder receives a video sequence from an image-capture device, together with metadata associated with the video sequence, and codes the video sequence into a first compressed bitstream using the metadata to select or revise a coding parameter associated with a coding operation. Optionally, the video sequence may be conditioned for coding by a preprocessor, which also may use the metadata to select or revise a preprocessing parameter associated with a preprocessing operation. The encoder may itself generate metadata associated with the first compressed bitstream, which may be used together with any metadata received by the encoder, to transcode the first compressed bitstream into a second compressed bitstream. The compressed bitstreams may be decoded by a decoder to generate recovered video data, and the recovered video data may be conditioned for viewing by a postprocessor, which may use the metadata to select or revise a postprocessing parameter associated with a postprocessing operation. | 12-09-2010 |
20100309987 | IMAGE ACQUISITION AND ENCODING SYSTEM - A method and system are provided to encode a video sequence into a compressed bitstream. An encoder receives a video sequence from an image-capture device, together with metadata associated with the video sequence, and codes the video sequence into a first compressed bitstream using the metadata to select or revise a coding parameter associated with a coding operation. Optionally, the video sequence may be conditioned for coding by a preprocessor, which also may use the metadata to select or revise a preprocessing parameter associated with a preprocessing operation. The encoder may itself generate metadata associated with the first compressed bitstream, which may be used together with any metadata received by the encoder, to transcode the first compressed bitstream into a second compressed bitstream. The compressed bitstreams may be decoded by a decoder to generate recovered video data, and the recovered video data may be conditioned for viewing by a postprocessor, which may use the metadata to select or revise a postprocessing parameter associated with a postprocessing operation. | 12-09-2010 |
Harry Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20130242145 | VIDEO ACQUISITION WITH INTEGRATED GPU PROCESSING - Systems and techniques for processing sequences of video images involve receiving, on a computer, data corresponding to a sequence of video images detected by an image sensor. The received data is processed using a graphics processor to adjust one or more visual characteristics of the video images corresponding to the received data. The received data can include video data defining pixel values and ancillary data relating to settings on the image sensor. The video data can be processed in accordance with ancillary data to adjust the visual characteristics, which can include filtering the images, blending images, and/or other processing operations. | 09-19-2013 |
Henry Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20090245343 | MULTIPLEXER BASED TRANSMITTER EQUALIZATION - In general, in one aspect, the disclosure describes a digital signal equalizer that includes a plurality of multiplexers. The number of multiplexers defines resolution of equalization. The plurality of multiplexers are configured in groups. The number of groups is based on number of taps, and the number of multiplexers associated with a particular group is based on equalization range for the group. The multiplexers in each group select a digital value associated with the cursor or a non-cursor tap associated with the group. | 10-01-2009 |
Jason Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20100039864 | METHODS OF ERASE VERIFICATION FOR A FLASH MEMORY DEVICE - Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification. | 02-18-2010 |
20110032761 | METHODS OF ERASE VERIFICATION FOR A FLASH MEMORY DEVICE - Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification. | 02-10-2011 |
20140293704 | Auto-Suspend and Auto-Resume Operations for a Multi-Die NAND Memory Device - A method and apparatus that controls a peak-current condition in a multi-die memory, such as a solid-state drive, by determining by at least one die of the multi-die memory whether a subsequent memory operation is a high-current memory operation, such as an operation to enable a charge pump of the die, an operation to charge a bit line of the die, or a program/erase loop operation, or a combination thereof. The die enters a suspended-operation mode if the subsequent memory operation is determined to be a high current memory operation. Operation is resumed by the die in response to a resume operation event, such as, but not limited to, a command specifically address to the die, an indication from another die that a high-current memory operation is complete. Once operation is resumed, the die performs the high-current memory operation. | 10-02-2014 |
Lei Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20100030766 | SYSTEMS AND METHODS FOR DETERMINING A TAG MATCH RATIO - The present invention is directed towards systems and methods for determining a tag match ratio. The method according to one embodiment of the present invention comprises selecting a content item, identifying one or more tags that are associated with the content item and determining a weight for each of the one or more tags associated with the content item. The method further comprises extracting one or more keywords from the content item. A tag match ratio for the one or more tags associated with the content item is then calculated and stored. | 02-04-2010 |
Meng Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20150213610 | IDENTIFYING REGIONS OF FREE SPACE WITHIN AN IMAGE - A digital magazine server presents content, which may include images, retrieved from various sources to a user. To improve presentation of images while allowing modification of images, the digital magazine server identifies feature points in an image and identifies regions of the image including the feature points. Groups of regions are generated based at least on the number of feature points in each region and the location of each region. Based on information associated with the groups, such as the location of various groups and the aspect ratio of various groups, one or more groups are selected and associated with the image. The selected groups may identify regions of the image including an object or not including an object, providing information for modifying the image without obscuring objects in the image. | 07-30-2015 |
Scott Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20090177940 | APPARATUS AND METHOD FOR ERROR CORRECTION IN MOBILE WIRELESS APPLICATIONS INCORPORATING ERASURE TABLE DATA - A receiver ( | 07-09-2009 |
20090259920 | APPARATUS AND METHOD FOR ERROR CORRECTION IN MOBILE WIRELESS APPLICATIONS INCORPORATING MULTI-LEVEL AND ADAPTIVE ERASURE DATA - A receiver ( | 10-15-2009 |
20100030941 | METHOD AND SYSTEM FOR CONNECTING MULTIPLE IDE DEVICES TO A USB APPARATUS USING A SINGLE USB-TO-IDE ADAPTER - A single USB-to-IDE adapter ( | 02-04-2010 |
20110013703 | MOBILE DISPLAY INTERFACE - An apparatus for encoding video display data comprises a transmitter that is configured to accept an RGB data signal from a source and a receiver that is configured to accept the RGB data signal from the transmitter. The RGB data signal comprises redundant synchronization information. Methods of using the apparatus are also provided. | 01-20-2011 |
20120027098 | APPARATUS AND METHOD FOR ERROR CORRECTION IN MOBILE WIRELESS APPLICATIONS INCORPORATING CORRECTION BYPASS | 02-02-2012 |
Shaori Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20100050052 | PIPELINED ERROR DETERMINATION IN AN ERROR-CORRECTING COMMUNICATION SYSTEM - A sequence of data packets is received within an integrated circuit device and stored within a first memory thereof. Error descriptor values are updated within a second memory of the integrated circuit device based on error information associated with the sequence of data packets. The error descriptor values each include an address field to specify a corresponding storage region of the first memory and an error field to specify an error status of data values stored within the storage region. A sequence of multiple-bit error values are generated based, at least in part, on the error fields and address fields within respective subsets of the error descriptor values. Concurrently with generation of at least one of the multiple-bit error values the state of one or more bits of the data values stored in the first memory based are changed based on a previously-generated one of the multiple-bit error values. | 02-25-2010 |
20100080305 | Devices and Methods of Digital Video and/or Audio Reception and/or Output having Error Detection and/or Concealment Circuitry and Techniques - A device to output video and/or audio data (for example, corresponding to a selected channel which is one of a plurality of channels of a broadcast spectrum), the device comprising (i) baseband processor circuitry to demodulate a baseband signal into a data stream (for example, MPEG type data stream, such as an MPEG-2 transport or program data stream) having a plurality of packets including a plurality of video and/or audio packets wherein each video and/or audio packet includes video and/or audio payload, (ii) de-multiplexer circuitry, coupled to the baseband processor circuitry, to: (a) de-multiplex the data stream to obtain the video and/or audio payload of the plurality of video and/or audio packets, (b) detect and locate one or more errors in one or more of the video and/or audio packets, and (c) generate error characterization data (for example, information which is representative of the type of error and/or the location of the error in the video and/or audio payload) which is representative of or characterizes one or more errors in the one or more of the video and/or audio packets; and (iii) decoder circuitry, coupled to the de-multiplexer circuitry, to: (a) receive the video and/or audio payload and the error characterization data, and (b) conceal the one or more errors in the video and/or audio payload using the error characterization data. | 04-01-2010 |
20110099330 | MEMORY OPTIMIZATION FOR VIDEO PROCESSING - Memory storage requirements for digital signal processing operations, for example, motion-compensated video scan rate conversion, that produce intermediate output data, which is then used as an input to the operation, are reduced by reordering operations and organizing memory allocations in a special manner to allow intermediate output at a particular execution time, to substantially share the same memory space as the intermediate output of a previous execution time. Such a reduction in the amount of memory required for processing operations advantageously reduces cost and power consumption. | 04-28-2011 |
20120033139 | FAST-BOOTING BROADCAST TELEVISION RECEIVER - Boot-up delay within a television receiver IC is substantially reduced by loading a portion of an operating program into the television receiver IC to enable execution of time-consuming receiver initialization operations, and then executing the receiver initialization operations concurrently with loading the remainder of the operating program into the television receiver IC. By this operation, the time required to execute the receiver initialization operations may be at least partly hidden under the time required to load the operating program, thereby substantially reducing the boot-up delay. | 02-09-2012 |
20120320966 | ADAPTIVE VIDEO DECODING CIRCUITRY AND TECHNIQUES - A method and circuitry for decoding an encoded video data stream which corresponds to a selected channel which is one of a plurality of channels of a broadcast spectrum. In one aspect, the method comprises determining one or more characteristics of the encoded video data stream, decoding the encoded video data stream to generate video data, wherein: (i) in response to determining the encoded video data stream includes a first characteristic, the encoded video data stream is decoded using a first decoding mode wherein, in response to decoding the encoded video data stream using the first decoding mode, the video data includes a first spatial resolution and a first temporal resolution, and (ii) in response to determining the encoded video data stream includes a second characteristic, the encoded video data stream is decoded using a second decoding mode wherein, in response to decoding the encoded video data stream using the second decoding mode, the video data includes a second spatial resolution and a second temporal resolution, wherein the first spatial resolution is different from the second spatial resolution and/or the first temporal resolution is different from the second temporal resolution. | 12-20-2012 |
20130031444 | PIPELINED ERROR DETERMINATION IN AN ERROR-CORRECTING COMMUNICATION SYSTEM - A sequence of data packets is received within an integrated circuit device and stored within a first memory thereof Error descriptor values are updated within a second memory of the integrated circuit device based on error information associated with the sequence of data packets. The error descriptor values each include an address field to specify a corresponding storage region of the first memory and an error field to specify an error status of data values stored within the storage region. A sequence of multiple-bit error values are generated based, at least in part, on the error fields and address fields within respective subsets of the error descriptor values. Concurrently with generation of at least one of the multiple-bit error values the state of one or more bits of the data values stored in the first memory based are changed based on a previously-generated one of the multiple-bit error values. | 01-31-2013 |
20140365731 | Systems and Methods for Cache Management for Universal Serial Bus Systems - Systems and methods are provided for cache management. An example system includes a cache and a cache-management component. The cache includes a plurality of cache lines corresponding to a plurality of device endpoints, a device endpoint including a portion of a universal-serial-bus (USB) device. The cache-management component is configured to receive first transfer request blocks (TRBs) for data transfer involving a first device endpoint and determine whether a cache line in the cache is assigned to the first device endpoint. The cache-management component is further configured to, in response to no cache line in the cache being assigned to the first device endpoint, determine whether the cache includes an empty cache line that contains no valid TRBs, and in response to the cache including an empty cache line, assign the empty cache line to the first device endpoint and store the first TRBs to the empty cache line. | 12-11-2014 |
Shengbo Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20150020086 | SYSTEMS AND METHODS FOR OBTAINING USER FEEDBACK TO MEDIA CONTENT - Techniques for obtaining user feedback related to media content are provided. Sensor data including motion data captured by a motion sensor while media content is played on a media content terminal device may be received. The sensor data may be analyzed for an indication of one or more personal states of one or more users. The indication of a first personal state may be determined based on the motion data. User preferences may be derived from the user feedback. For example, parts of the media content (e.g., specific video frames or scenes) may be analyzed and various entities or features extracted. The entities or features may be matched against user feedback to derive user preferences at a more granular level. | 01-15-2015 |
Sherry Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20100270178 | Method And Apparatus For Rapid Electrochemical Analysis - Methods and apparatus for electrochemically determining an analyte concentration value in a physiological sample are disclosed. The methods include using a test strip in which two time-current transients are measured by a meter electrically connected to an electrochemical test strip. Integrative current values are derived from the time-current transients and used in the calculation of analyte concentration. | 10-28-2010 |
Sherry Xuan Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20140255451 | Implantable Medical Device Comprising A Macrocyclic Triene Lactone Drug And Minimal Antioxidant Stabilizer And Method Of Fabrication - The present invention relates to an oxygen-sensitive macrocyclic triene lactone that is protected by addition of an appropriate amount of an antioxidant stabilizer during fabrication of an implantable medical device comprising the macrocyclic triene lactone, wherein the amount of the antioxidant stabilizer has been reduced to a minimal, preferably, non-detect, level in the final packaged product. | 09-11-2014 |
Shuang Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20100114559 | SHORT TEXT LANGUAGE DETECTION USING GEOGRAPHIC INFORMATION - A content-providing entity receives a relatively short text from a user and attempts to determine, automatically, based on that short text (and on other available clues), a language that the user can read and understand. The content-providing entity may then provide, to the user, documents that are written in the determined language. The content-providing entity may determine a language of the input text based on several factors in combination: (a) the service provider's “market,” which is determined based on at least a portion of the URL of the Internet site to which the user directed his browser; (b) the user's “region,” which is determined based on the source Internet Protocol (IP) address of the IP packets that the user sends to the Internet site; (c) the “script” in which the short user-entered text is written; and (d) a statistical analysis of the frequency of the characters present in the short user-entered text. | 05-06-2010 |
20120117059 | Ranking Authors in Social Media Systems - The author ranking technique described herein is a technique to rank authors in social media systems along various dimensions, using a variety of statistical methods for utilizing those dimensions. More particularly, the technique ranks authors in social media systems through a combination of statistical techniques that leverage usage metrics, and social and topical graph characteristics. In various exemplary embodiments, the technique can rank author authority by the following: 1) temporal analysis of link sharing in which authority is computed based on a user's propensity to provide early links to web pages that subsequently become popular; 2) topical authority based on the author's links and content updates in specific topic areas; and 3) popularity and influence based on nodal properties of authors. | 05-10-2012 |
Shuo Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20130227048 | Method for Collaborative Caching for Content-Oriented Networks - A content router comprising a plurality of interfaces configured to receive and forward a plurality of interests for content and content data in a content oriented network (CON), a cache configured to store content data, and a memory component configured to maintain a forward information base (FIB) that associates content with one or more interfaces on which the interests and content data are received and forwarded, and an availability FIB (AFIB) that associates content data with one or more corresponding collaborative caching routers in the CON that cache the content data. | 08-29-2013 |
Xiaojiang Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20140258619 | APPARATUSES AND METHODS FOR A MEMORY DIE ARCHITECTURE - Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. One of the plurality of memories may be coupled to an external data bus. The one of the plurality of memories may be configured to provide program data to the internal data bus when the command comprises a program command and another of the plurality of memories is a target memory of the program command and may be configured to provide read data to the external data bus when the command comprises a read command and the another of the plurality of memories is a target memory of the read command. | 09-11-2014 |
20150357031 | PROGRAMMING MEMORIES WITH STEPPED PROGRAMMING PULSES - Memories and methods for programming memories with multi-step programming pulses are provided. One method includes applying a plurality of programming pulses to cells of the memory device to be programmed, with each programming pulse of the plurality of programming pulses being configured to contribute towards programming a cell of the plurality of cells to each data state of a plurality of programmed data states. A first portion of each programming pulse is used to program certain cells towards a target data state associated with a first threshold voltage level, and a later portion of each programming pulse is used to program other cells towards a target data state associated with a second threshold voltage level that is lower than the first threshold voltage level. | 12-10-2015 |
Yan Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20090039966 | Multi-Stage RF Amplifier Including MMICs and Discrete Transistor Amplifiers in a Single Package - A MMIC amplifier stage and a discrete transistor amplifier stage are housed in a single package. In one aspect, a multi-stage RF amplifier includes a package with an RF input lead and an RF output lead. The signal path from the RF input lead to the RF output lead includes one or more MMIC amplifier stages followed by one or more discrete transistor amplifier stages. Each MMIC amplifier stage includes a MMIC with at least one amplifier, and each discrete transistor amplifier stage includes at least one discrete transistor amplifier. All of the MMIC amplifier stages and discrete transistor amplifier stages are housed in the same package. | 02-12-2009 |
Yanchuan Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20150280560 | MULTI-PHASE SMPS WITH LOOP PHASE CLOCKS AND CONTROL METHOD THEREOF - A multi-phase SMPS has N switching circuits; a setting signal generator generating a setting signal based on an output signal of the SMPS; a clock signal generator generating a system clock signal; and a controller receiving the setting signal and the system clock signal, the controller generating N shifted phase clock signals according to the system clock signal, and the N shifted phase clock signals forming loop phase clocks, and the controller further generates N switching control signals based on the setting signal and the N shifted phase clock signals. | 10-01-2015 |
Yinni Guo, San Jose, CA US
Yu Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20090240770 | Establishing a Remotely Hosted Conference Initiated with One Button Push - A method includes registering with a first remote conference manager operated by a first entity and a request to enable conferencing with a second entity. The method also includes querying the first remote conference manager for at least one conference room hosted by the second entity and updating a directory of conference rooms comprising at least one local conference room to further comprise the at least one remote conference room. The method further includes receiving a request to schedule a conference. Upon determining at least one remote conference room is to be used for the scheduled conference, the method also includes transmitting the request to the first remote conference manager. Upon the second remote conference manager transmitting an acceptance of the conference, the method also includes receiving details from the first remote conference manager for establishing a connection for use with the conference and transmitting the details to the at least one local conference room. | 09-24-2009 |
Yuanhung Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20130287529 | METHOD AND APPARATUS FOR INDEPENDENT WAFER HANDLING - A substrate processing system with independent substrate placement capability to two or more substrate support assemblies is provided. Two different sets of fixed-length lift pins are disposed on two or more substrate support lift pin assemblies of two or more process chambers, where the length of each lift pin in one process chamber is different from the length of each lift pin in another process chamber. The substrate processing system includes simplified mechanical substrate support lift pin mechanisms and minimum accessory parts cooperating with a substrate transfer mechanism (e.g., a transfer robot) for efficient and independent loading, unloading, and transfer of one or more substrates between two or more processing regions in a twin chamber or between two or more process chambers. A method for positioning one or more substrates to be loaded, unloaded, or processed independently or simultaneously in two or more processing regions or process chambers is provided. | 10-31-2013 |
Yu H. Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20140192817 | Virtual link aggregation using state machine - Physical links between an access switch and a pair aggregation switches are aggregated into a virtual link aggregation group (vLAG). Each aggregation switch is a local switch to itself and a remote switch to the other aggregation switch. Each aggregation switch maintains a state machine including initialization, local-up, remote-up, and formed states. In the initialization state, the physical link between the access switch and each aggregation switch is down, and the vLAG is down. In the local-up state, just the physical link between the access switch and the local switch is up, and the vLAG is down. In the remote-up state, just the physical link between the access switch and the remote switch is up, and the vLAG is down. In the formed state, the physical link between the access switch and each aggregation switch is up, and the vLAG is up. | 07-10-2014 |
Zhendong Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20140118077 | INVERTER CELL FOR A RING OSCILLATOR - An inverter cell for a ring oscillator. The inverter cell includes a first transistor, a second transistor, a first resistor, a second resistor, and a capacitor. A voltage input terminal is connected to gates of the first transistor and the second transistor. A voltage output terminal is connected drains of the first transistor and the second transistor. The first resistor is connected to the source of the first transistor and a first voltage potential. The second resistor is connected to the source of the second transistor and a second voltage potential. The capacitor has a first end directly connected to the source of the first transistor and the first end of the first resistor and a second end directly connected to the source of the second transistor and the first end of the second resistor. | 05-01-2014 |
Zheng Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20150094090 | CACHING OF LOCATIONS ON A DEVICE - Various devices, systems and methods for obtaining a location from a cache on a device are described. In various embodiments, the obtained location is based on data generated at the mobile device. Additional embodiments relate to cache hit determination techniques and techniques for sharing, managing and prepropagating the cache. | 04-02-2015 |
Zhi Guo, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20150055481 | CONTEXT-AWARE PATTERN MATCHING ACCELERATOR - Methods and systems for improving accuracy, speed, and efficiency of context-aware pattern matching are provided. According to one embodiment, a packet stream is received and pre-matched by an acceleration device with one or more conditions to identify packets meeting the one or more conditions. The acceleration device then correlates at least one identified packet based on the one or more conditions to generate matching tokens of the packet that meet the one or more conditions and sends, to one or more processors of the acceleration device, the matching tokens along with identifiers of the one or more conditions so that the processors can process the matching tokens and the identifiers of the one or more conditions based on one or more of context aware string matching, regular expression matching, and packet field value matching to extract packets that match context of the one or more conditions. | 02-26-2015 |
20150326534 | CONTEXT-AWARE PATTERN MATCHING ACCELERATOR - Methods and systems for improving accuracy, speed, and efficiency of context-aware pattern matching are provided. According to one embodiment, a packet stream is received by a first stage of a CPMP hardware accelerator of a network device. A pre-matching process is performed by the first stage to identify a candidate packet that matches a string or over-flow pattern associated with IPS or ADC rules. A candidate rule is identified based on a correlation of results of the pre-matching process. The candidate packet is tokened to produce matching tokens and corresponding locations. A full-match process is performed on the candidate packet by a second stage of the CPMP hardware accelerator to determine whether it satisfies the candidate rule by performing one or more of (i) context-aware pattern matching, (ii) context-aware string matching and (iii) regular expression matching based on contextual information, the matching tokens and the corresponding locations. | 11-12-2015 |