Mclachlan, GB
Alan Mclachlan, Hampshire GB
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20080301075 | METHOD OF TRAINING A NEURAL NETWORK AND A NEURAL NETWORK TRAINED ACCORDING TO THE METHOD - A neural network comprises trained interconnected neurons. The neural network is configured to constrain the relationship between one or more inputs and one or more outputs of the neural network so the relationships between them are consistent with expectations of the relationships; and/or the neural network is trained by creating a set of data comprising input data and associated outputs that represent archetypal results and providing real exemplary input data and associated output data and the created data to neural network. The real exemplary output data and the created associated output data is compared to the actual output of the neural network, which is adjusted to create a best fit to the real exemplary data and the created data. | 12-04-2008 |
Andrew James Mclachlan, London GB
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20150049631 | TOPOLOGY AWARE PROVISIONING IN A SOFTWARE-DEFINED NETWORKING ENVIRONMENT - An example method for topology aware provisioning in a software-defined network environment is provided and includes receiving, at a provider edge device (PE), access network topology information associated with a customer edge device in a network environment, synthesizing the access network topology information and a local router information associated with the PE into a topology message, and publishing the topology message to a central controller in the network environment. The synthesizing can include aggregating the access network topology information and the local router information, modeling the aggregated information in a representation-independent format and encoding the representation-independent formatted aggregated information in standardized machine-parsable format. | 02-19-2015 |
Angus Mclachlan, Midlothian GB
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20100238071 | PHASED ARRAY ANTENNA - This invention relates to utilising a larger number of lower power transmit/receive modules in a phased antenna array in order to utilise cheaper and simpler transmit/receive modules whilst retaining comparable power per unit area as can be achieved through using conventional high powered transmit/receive modules. The advantage of this arrangement is that cheaper antenna arrays can be constructed without limiting the capability and/or performance of a system incorporating such an array when compared to a conventional solution. | 09-23-2010 |
Angus David Mclachlan, Midlothian GB
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20100201601 | ANTENNA - A phased array antenna is disclosed where the transmit/receive modules are replaced by a series of separately packaged components. The components include, for example, a vector control component, a high power amplifier component, a low noise amplifier component, a transmit/receive duplexing component and ancillary supporting components. An advantage of this arrangement is that cheaper antenna arrays can be constructed without limiting the capability and/or performance of a system incorporating such an array when compared to known solutions. | 08-12-2010 |
Charles Mclachlan, Cambridge GB
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20090092333 | Digital signal processing with improved mapping - A method of performing a signal enhancement operation on a digital input signal is described. The method produces a best estimate of a true signal which the digital input signal is assumed to represent. The method involves deriving a plurality of candidate mappings, each defining a mapping between the signal domain of the digital input signal and an alternative optimisation domain, each signal in the signal domain corresponding to a set of optimisation parameters in the optimisation domain. For each candidate mapping, an indicator of the quality of the candidate mapping is calculated an a set of optimisation parameters in the optimisation domain of the candidate mapping is generated, the set of optimisation parameters re resenting an enhanced signal in that domain. The highest-quality mapping is then selected in dependence on the calculated indicators, and the set of optimisation parameters generated for the selected mapping is selected. The selected mapping is applied to the selected set of optimisation parameters to produce an enhanced digital signal. The method finds application in a variety of signal processing fields including image processing, and is applicable for exmple, to image processing tasks such as image enhancement or image reconstruction. | 04-09-2009 |
Fiona Mclachlan, London GB
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20110054111 | ENCAPSULATED TINTERS - The invention provides a tinter dosage unit comprising water borne tinter encapsulated in a water soluble pouch where the water activity of the tinter and the combined water activity and plasticizer activity of the pouch are such that the pouch remains intact in normal use. | 03-03-2011 |
20130125790 | LOW VOC COLORANT COMPOSITIONS - An aqueous liquid colorant composition having a volatile organic content up to 50 g/l and suitable for colouring aqueous or solventborne architectural coatings and basepaints comprising based on the total weight of the composition, i) from 0 to 26% of non-volatile organic liquid having a vapour pressure up to 1.3 N/m | 05-23-2013 |
Ian Mclachlan, Ayton Berwickshire GB
Janice Mclachlan, Dundee GB
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20090137572 | 2-substituted-4-heteroaryl-pyrimidines useful for the treatment of proliferative disorders - The present invention relates to selected substituted pyrimidines their preparation, pharmaceutical compositions containing them and their use as inhibitors of one or more protein kinases, and hence their use in the treatment of proliferative disorders, viral disorders and/or other disorders. | 05-28-2009 |
Janice Mclachlan, Dudee GB
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20100035870 | Pyrimidin-4-yl-3, 4-Dihydro-2H-Pyrrolo[1,2A] Pyrazin-1-one Compounds - The present invention relates to compounds of formula (I), or pharmaceutically acceptable salts thereof, wherein Z is NR | 02-11-2010 |
Martyn A. Mclachlan, London GB
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20160141537 | NANOSTRUCTURED ANODE-CATHODE ARRAY FOR OPTOELECTRONIC DEVICES - The nanostructured anode-cathode array for optoelectronic devices is an interdigitated electrode assembly for organic optoelectronic devices. The electrode assembly provides efficiency enhancement in metal oxide (ZnO) and metal (Ag) electrodes for organic optoelectronic devices. The assembly has vertically orientated nanorods in a range of patterns, configurations and volume fractions. The rods have lateral dimensions in the range of 1 nm-500 nm and lengths of 1 nm-10,000 nm. The anode-cathode array can be tuned by altering the dimensions of the individual electrodes and/or modifying the center-to-center distance of anode-anode, cathode-cathode or anode-cathode pairs. | 05-19-2016 |
Matthew Murdoch Woodhead Mclachlan, Bracknell GB
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20100004128 | HERBICIDAL ISOXAZOLINE COMPOUNDS - Novel compounds of formula (I): wherein R | 01-07-2010 |
Roderick Mclachlan, Edinburgh GB
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20100315277 | DIGITAL TO ANALOG CONVERTERS HAVING CIRCUIT ARCHITECTURES TO OVERCOME SWITCH LOSSES - A digital to analog converter (DAC) includes a pair of operational amplifiers each having a first input coupled to a respective high or low reference voltage. The DAC includes a plurality of switch-controlled cells, each of which includes a resistor and two force/sense switch pairs. Within each cell, all four switches are coupled to the resistor. A first force switch is coupled to an output of a first op amp and an associated sense switch is coupled to an inverting input of the first op amp. A second force switch is coupled to an output of a second op amp and an associated sense switch is coupled to an inverting input of the second op amp. Thus, the force switches provide selectively conductive paths to permit either op amp to drive a given cell. When an op amp drives particular cells, sense switches generate multiple a feedback paths to the driving op amp, which permits the op amp to drive the selected cell resistors at voltages that overcomes any voltage losses induces by associated force switches, and cancels the effect of any variation in the voltage losses induced by different force switches. The switch-controlled cells find application in a variety of DAC architectures, including binary weighted R2R architectures, equally-weighted segmented architectures or hybrid architectures that blend principles of R2R and segmented architectures. | 12-16-2010 |
20110037630 | VOLTAGE MODE DAC WITH CALIBRATION CIRCUIT USING CURRENT MODE DAC AND ROM LOOKUP - The invention is a novel scheme of calibrating a voltage-mode digital to analog converter using a current-mode digital to analog converter. A DAC system is comprised of a voltage-mode DAC with an R-2R architecture structure and includes a ROM lookup table where calibration codes associated with each of a plurality of input codes are stored. A reference current is scaled with the calibration codes to output a calibration current that induces adjustments in an output voltage to counteract non-linearities that may be induced by resistor mismatch. | 02-17-2011 |
20120013492 | PROGRAMMABLE LINEARITY CORRECTION CIRCUIT FOR DIGITAL-TO- ANALOG CONVERTER - The invention provides a systematic error correction network coupled to a converter. The converter may display a systematic non-linearity error, and the systematic error correction network shapes a correction transform function that acts like counter distortion function for the non-linearity error. The systematic error correction network then scales the correction transform function according to a reference variable, where the magnitude of non-linearity error is related to the reference variable. The scaled correction transform function is then applied to the converter path in order to generate a corrected analog output signal. | 01-19-2012 |
20140232580 | VOLTAGE GENERATOR, SWITCH AND DATA CONVERTER CIRCUITS - A data converter can include a resistor network, a switch network connected to the resistor network and having a plurality of switch circuits, each with an NMOS and a PMOS switch transistor, and a voltage generator to generate a drive voltage for driving a gate of at least one of the NMOS or PMOS switch transistors of at least one of the switch circuits. The voltage generator can include first and second pairs of transistors, each pair having connected control terminals and being connected to a second NMOS or PMOS transistor, a first or second resistor, and the other pair of transistors. The first and second resistors can have substantially equal resistance values. A ratio of width-to-length ratios of the second NMOS to PMOS transistors can be substantially equal to such a ratio of the switch circuit NMOS to PMOS transistors. | 08-21-2014 |
20150097712 | DIGITAL-TO-ANALOG CONVERTER AND A METHOD OF OPERATING A DIGITAL-TO-ANALOG CONVERTER - A digital-to-analog converter (DAC) comprising a first section having a first plurality of current flow paths forming binary weighted values in the DAC; and a second section connected to the first section and having a second plurality of current flow paths, wherein each of the first and second plurality of current flow paths are switchable between first and second nodes, and wherein weights of one or more of the second plurality of current flow paths are notionally equal to weights of one or more of the first plurality of current flow paths so as to provide redundancy in the first section. | 04-09-2015 |