Patent application number | Description | Published |
20100034192 | WIRELESS COMMUNICATION DEVICE, INTEGRATED CIRCUIT AND METHOD OF TIMING SYNCHRONISATION - A wireless communication device comprises a first sub-system arranged to pass data to a second sub-system comprising timing synchronisation logic operably coupled to a counter, such that data is sampled by the timing synchronisation logic when passed to the second sub-system from the first sub-system wherein the wireless communication device is characterised in that the timing synchronisation logic is arranged to determine a position of a first data frame and in response thereto initiate a counting process of the counter and determine a position of a second data frame and in response thereto determine a count value from the counting process of the counter and in response to the count value determine whether to initiate a timing advance or timing retard operation on the data being passed to the second sub-system. In this manner, the inventive concept provides the wireless communication device with a mechanism to achieve timing synchronisation. In particular, the inventive concept may allow a radio frequency integrated circuit to implement timing synchronisation by advancing or retarding an ‘actual’ signal sent from digital baseband circuits in a 3G DigRF wireless communication device. | 02-11-2010 |
20100086016 | METHOD AND APPARATUS FOR VARYING A DYNAMIC RANGE - A communications device comprises a receiver for receiving an input signal operably coupled to analogue to digital converter logic. The analogue to digital converter logic is operably coupled to control logic via a signal analyser arranged to analyse a converted received input signal, output from the analogue to digital converter logic to determine at least one characteristic of the received signal. The control logic is arranged to vary a dynamic range of the analogue to digital converter logic depending on the at least one determined characteristic of the received input signal. | 04-08-2010 |
20100117824 | METHOD AND APPARATUS TO RECEIVE LOCATION INFORMATION IN A DIVERSITY ENABLED RECEIVER - A method of processing location information on a mobile device which includes a primary receiver for receiving a primary signal; a diversity receiver for receiving a diversity signal or location information; a diversity combiner which can combine primary and diversity signals to form a combined signal; and a first processing unit for processing the combined signal; the method comprising the steps of: identifying whether the device is in a location mode or a diversity mode; if the device is in location mode, disabling the diversity combiner; passing the output from the primary receiver directly to the first processing unit; and passing location information from the diversity receiver to a location processing unit. | 05-13-2010 |
20100167674 | INTEGRATED CIRCUIT, WIRELESS COMMUNICATION UNIT AND METHOD FOR DETERMINING QUADRATURE IMBALANCE - An integrated circuit comprising processing logic for operably coupling to radio frequency (RF) receiver circuitry arranged to receive a wireless network signal. The receiver circuitry generates in-phase and quadrature digital baseband representations of the wireless network signal. The processing logic determines quadrature (I/Q) imbalance of the RF receiver circuitry based on the in-phase and quadrature digital baseband representations of the wireless network signal. | 07-01-2010 |
20100173601 | VERY LOW INTERMEDIATE FREQUENCY (VLIF) RECEIVER - A very low intermediate frequency (VLIF) receiver comprising a first and second mixer circuits, characterised in that receiver comprises a means of estimating the energy in a desired signal band; a means of estimating the energy in a band of frequencies comprising the desired signal band; and a means of altering a VLIF of the receiver according to the ratio of the energy in a desired signal band and the energy in the band of frequencies comprising the desired signal band. | 07-08-2010 |
20100234060 | PROLONGING INTERNAL POWER SUPPLY LIFE IN A MOBILE COMMUNICATION DEVICE - A method of communicating between a mobile communication device including a power supply, and a base station. The mobile device has first and second alternative communication modes, the first communication mode having higher quality of service and higher power consumption than the second communication mode. The second communication mode is adopted in response to a characteristic of the mobile device power supply indicative of a reduced reserve of power in the power supply, and a state indication is transmitted from the mobile device to the base station. The base station can respond to the state indication from the mobile device by modifying a communication characteristic of the base station with the mobile device, whereby to tend to compensate for the mobile device switching between the first and second communication modes. | 09-16-2010 |
20100298035 | WIRELESS COMMUNICATION UNIT, INTEGRATED CIRCUIT AND METHOD OF POWER CONTROL THEREIN - A wireless communication unit comprises a transmitter having a power amplifier and a feedback path operably coupled to the power amplifier. The feedback path comprises a coupler for feeding back a portion of a signal to be transmitted and a detector for detecting a power level of the fed back signal. A controller provides a ramp signal to the power amplifier that controls an amplitude characteristic of the signal to be transmitted. Averaging logic is operably coupled to the detector and arranged to average the detected power level over a first period. Comparison logic is operably coupled to the averaging logic and arranged to compare the average detected power level with a reference value. The controller is operably coupled to the comparison logic and arranged to scale a ramp signal applied to the power amplifier in response to the comparison. | 11-25-2010 |
20110007847 | DC COMPENSATION FOR VLIF SIGNALS - Receiver circuitry for processing a received Very Low Intermediate Frequency signal wherein the receiver circuitry comprises a main processing path. The main processing path comprises mixing circuitry arranged to mix a received VLIF signal with a frequency down conversion signal to produce a main path signal. The receiver circuitry further comprises a direct current cancellation path comprising mixing circuitry arranged to mix a DC element of the received VLIF signal with the frequency down conversion signal to produce a DC cancellation signal. The receiver circuitry still further comprises signal summing circuitry arranged to add the DC cancellation signal in anti-phase with the main path signal. | 01-13-2011 |
20110012663 | CLOCK SIGNAL GENERATING ARRANGEMENT FOR A COMMUNICATION DEVICE - A clock signal generating arrangement for a communication device generates a system clock signal at an output for use as a timing reference. The clock signal generating arrangement comprises a reference clock generator for generating a reference clock signal, a main clock generator for generating a main clock signal having a greater accuracy than the reference clock signal, a clock adjust circuit coupled to the reference clock generator for generating a compensated reference clock signal to compensate for error in the reference clock signal and a clock signal selector coupled to the reference clock generator the main clock generator and the clock adjust circuit. The clock signal selector selectively provides to the output of the clock signal generating arrangement as the system clock signal the compensated reference clock signal when an error in the reference clock signal reaches a first predetermined threshold and until the error in the reference clock signal has been compensated and otherwise the reference clock signal when the communication device is operating in an idle mode or the main clock signal when the communication device is operating in an active mode. | 01-20-2011 |
20110116577 | SEMICONDUCTOR DEVICE WIRELESS COMMUNICATION UNIT AND METHOD FOR RECEIVING A SIGNAL - A semiconductor device comprising receiver circuitry arranged to receive a dual carrier RF signal comprising a first wanted component and a second wanted component. The receiver circuitry is arranged to down convert the received dual carrier RF signal to create a Very Low Intermediate Frequency, VLIF signal whereby the first wanted component of the received dual carrier signal is subsequently located at a positive VLIF offset with respect to DC, zero hertz, and the second wanted component of the received dual carrier signal is subsequently located at a negative VLIF offset with respect to DC. The semiconductor device further comprises a signal processing logic module arranged to receive the VLIF signal and to separate the first and second wanted components of the received signal. | 05-19-2011 |
20110121872 | SEMICONDUCTOR DEVICE, WIRELESS COMMUNICATION DEVICE AND METHOD FOR GENERATING A SYNTHESIZED FREQUENCY SIGNAL - A semiconductor device comprises synthesized frequency generation logic arranged to receive a reference signal, and to generate a synthesized frequency signal from the reference signal. The synthesized frequency generation logic comprises programmable divider logic arranged to receive the reference signal and to generate a divided signal comprising a frequency with a period substantially equal to N times that of the reference signal, where N comprises a programmable integer value. The synthesizer frequency generation logic is arranged to generate the synthesized frequency signal comprising a frequency with a period substantially equal to 1/M that of the divided signal, where M comprises a further programmable integer value. | 05-26-2011 |
20110151804 | SEMICONDUCTOR DEVICE, WIRELESS COMMUNICATION DEVICE AND METHOD FOR GENERATING A SYNTHESIZED FREQUENCY SIGNAL - A semiconductor device comprises synthesized frequency generation logic arranged to receive a reference signal, and to provide an output frequency signal. The synthesized frequency generation logic comprises divider logic arranged to receive the reference signal and to generate a divided signal comprising a frequency with a period equal to N times that of the reference signal. The synthesized frequency generation logic is further arranged to generate the synthesized frequency signal comprising a frequency with a period equal to 1/M that of the divided signal. The synthesized frequency generation logic comprises or is operably coupled to decision logic module and comprises or is operably coupled to a switching logic module such that the decision logic module is arranged to determine whether a near-integer spur arises in using the synthesized frequency signal, and configures the switching logic module to select the synthesized frequency signal in response thereto. | 06-23-2011 |