Patent application number | Description | Published |
20080205156 | Method of operating nonvolatile memory device - Provided is a method of operating a nonvolatile memory device to perform an erase operation. The method includes applying a composite pulse including a direct current (DC) pulse and a DC perturbation pulse to the nonvolatile memory device to perform the erase operation. | 08-28-2008 |
20080205157 | Method of operating nonvolatile memory device - Provided is a method of operating a nonvolatile memory device to perform a programming operation or an erase operation. The method includes applying a composite pulse including a direct current (DC) pulse and an AC perturbation pulse to the nonvolatile memory device to perform the programming operation or the erase operation. | 08-28-2008 |
20080217681 | Charge trap memory device and method of manufacturing the same - Provided are a charge trap memory device and method of manufacturing the same. A charge trap memory device may include a tunnel insulating layer on a substrate, a charge trap layer on the tunnel insulating layer, and a blocking insulating layer formed of a material including Gd or a smaller lanthanide element on the charge trap layer. | 09-11-2008 |
20080296739 | Method of forming a thin film structure and stack structure comprising the thin film - Provided is a method of forming a thin film structure and a stack structure comprising the thin film. The method may include forming a crystalline Al | 12-04-2008 |
20080316820 | Method of programming memory device - Provided is a method of programming a memory device. The method includes performing a program voltage applying operation; and performing a verifying operation, wherein a plurality of verifying operations are consecutively performed after a program voltage applying operation. | 12-25-2008 |
20090021979 | Gate stack, capacitorless dynamic random access memory including the gate stack and methods of manufacturing and operating the same - Provided are a gate stack, a capacitorless dynamic random access memory (DRAM) including the gate stack and methods of manufacturing and operating the same. The gate stack for a capacitorless DRAM may include a tunnel insulating layer on a substrate, a first charge trapping layer on the tunnel insulating layer, an interlayer insulating layer on the first charge trapping layer, a second charge trapping layer on the interlayer insulating layer, a blocking insulating layer on the second charge trapping layer, and a gate electrode on the blocking insulating layer. The capacitorless DRAM may include the gate stack on the substrate, and a source and a drain in the substrate on both sides of the gate stack. | 01-22-2009 |
20090027961 | Non-volatile memory cell programming method - A non-volatile memory cell programming method is provided. A memory cell programming method of programming 2-bit data in a memory cell having 4 threshold voltage distributions may comprise: a first program operation of programming a first bit of the 2-bit data in the memory cell by applying a first programming voltage to the memory cell; a second program operation of programming a second bit of the 2-bit data in the memory cell by applying a second programming voltage to the memory cell; and a stabilization operation of applying a stabilization voltage having an electric field opposite in polarity to an electric field formed by the first and second programming voltages to the memory cell after one of the first and second program operations that corresponds to a higher one of the first and second programming voltages is performed. | 01-29-2009 |
20090045455 | Nonvolatile memory device and method of fabricating the same - Example embodiments relate to nonvolatile semiconductor memory devices using an electric charge storing layer as a storage node and fabrication methods thereof. An electric charge trap type nonvolatile memory device may include a tunneling film, an electric charge storing layer, a blocking insulation film, and a gate electrode. The blocking insulation film may be an aluminum oxide having an energy band gap larger than that of a γ-phase aluminum oxide film. An α-phase crystalline aluminum oxide film as a blocking insulation film may have an energy band gap of about 7.0 eV or more along with fewer defects. The crystalline aluminum oxide film may be formed by providing a source film (e.g., AlF | 02-19-2009 |
20090050954 | Non-volatile memory device including charge trap layer and method of manufacturing the same - Provided are a non-volatile memory device and a method of manufacturing the non-volatile memory device. The non-volatile memory device includes a charge trap layer having a crystalline material. In the method, a tunneling insulating layer is formed on a substrate, and a crystalline charge trap layer is formed on the tunneling insulating layer. | 02-26-2009 |
20090071934 | Crystalline aluminum oxide layers having increased energy band gap, charge trap layer devices including crystalline aluminum oxide layers, and methods of manufacturing the same - Crystalline aluminum oxide layers having increased energy band gap, charge trap memory devices including crystalline aluminum oxide layers and methods of manufacturing the same are provided. A method of forming an aluminum oxide layer having an increased energy band gap includes forming an amorphous aluminum oxide layer on a lower film, introducing hydrogen (H) or hydroxyl group (OH) into the amorphous aluminum oxide layer, and crystallizing the amorphous aluminum oxide layer including the H or OH. | 03-19-2009 |
20090117697 | Nonvolatile memory device including nano dot and method of fabricating the same - A nonvolatile memory device including a nano dot and a method of fabricating the same are provided. The nonvolatile memory device may include a lower electrode, an oxide layer on the lower electrode, a nano dot in the oxide layer and an upper electrode on the oxide layer. In example embodiments, the current paths inside the oxide layer may be unified, thereby stabilizing the reset current. | 05-07-2009 |
20090256941 | Image sensor with sensing transistor having two gates and method of operating the same - Provided is an image sensor including a sensing transistor having two gates and a method of operating the image sensor. The image sensor may include a photoelectric conversion device, a sensing transistor which may have a first gate connected to a floating diffusion region in which charges generated from the photoelectric conversion region are stored and a second gate separated from the first gate, a reset transistor that may be connected to the floating diffusion region and may reset a potential of the floating diffusion region, a control voltage source that may supply a control applied to the second gate, and a column output line which may be connected to a source of the sensing transistor. | 10-15-2009 |
20100032737 | Nano-magnetic memory device and method of manufacturing the device - A nano-magnetic memory device capable of writing/reading multi data in the nano-magnetic memory cell by controlling an amount of an induced current which is formed after a magnetic nanodot is perturbed and rearranged according to a word line current flowing from the first electrode through a nanowire of the nano-magnetic memory device to the second electrode. Consequently, a size of the memory device is reduced and a density of the memory device may be improved by providing a simplified nano-magnetic memory device of which a cell size is smaller. | 02-11-2010 |
20100109074 | Gate structure, semiconductor memory device having the gate structure and methods of fabricating the same - A gate structure using nanodots as a trap site, a semiconductor device having the gate structure and methods of fabricating the same are provided. The gate structure may include a tunneling layer, a plurality of nanodots on the tunneling layer, and a control insulating layer including a high-k dielectric layer on the tunneling layer and the nanodots. A semiconductor memory device may further include a semiconductor substrate, the gate structure according to example embodiments on the semiconductor substrate and a first impurity region and a second impurity region in the semiconductor substrate, wherein the gate structure is in contact with the first and second impurity regions. | 05-06-2010 |
20110006358 | Al-doped charge trap layer, non-volatile memory device and methods of fabricating the same - Provided is an aluminum (Al) doped charge trap layer, a non-volatile memory device and methods of fabricating the same. The charge trap layer may include a plurality of silicon nano dots that trap charges and a silicon oxide layer that covers the silicon nano dots, wherein the charge trap layer is doped with aluminum (Al). The non-volatile memory device may include a substrate including a source and a drain on separate regions of the substrate, a tunneling film on the substrate contacting the source and the drain, the charge trap layer according to example embodiments, a blocking film on the charge trap layer, and a gate electrode on the blocking film. | 01-13-2011 |
20110164457 | Method of operating nonvolatile memory device - Provided is a method of operating a nonvolatile memory device to perform a programming operation or an erase operation. The method includes applying a composite pulse including a direct current (DC) pulse and an AC perturbation pulse to the nonvolatile memory device to perform the programming operation or the erase operation. | 07-07-2011 |