Patent application number | Description | Published |
20110093612 | DEVICE, METHOD AND COMPUTER READABLE MEDIUM FOR BGP ROUTE MONITORING - A BGP route monitoring device includes a routing information receiving unit configured to receive BGP routing information. The device also includes a first database storing a plurality of pieces of BGP routing information registered in an IRR server. The server also includes a routing failure detecting unit to classify the received BGP information into states by comparing the received BGP information with the first database and to determine whether the received BGP routing information is an invalid path based on the classified states. In this configuration, the plurality of states include a state where Prefix of the received BGP information matches Prefix of BGP routing information in the first database, the PrefixLength of the received BGP information is shorter than PrefixLength of the BGP routing information in the first database, and Origin AS number of the received BGP routing information matches Origin AS number of the BGP routing information in the first database. | 04-21-2011 |
20110211587 | Packet Relaying Device, Packet Relaying Method And Program - A packet relaying device, wherein a reception processing unit judges an interface used to receive an IP packet from a network, and records a reception interface identifier (RID) which is information for identifying the interface, in a packet transmission/reception management table, a route control unit records, in the packet transmission/reception management table, a transmission interface identifier (SID) which is information for identifying the transmission interface obtained by selection of a transmission path and the above described reception interface identifier (RID), in such a manner that the identifies are associated with each other. A transmission processing unit makes a comparison between the reception interface identifier (RID) and the transmission interface identifier (SID) recorded in the packet transmission/reception management table, and when the both identifiers are the interface identifier of the same virtual network interface, the transmission processing unit discards the IP packet to invalidate the transmission process. | 09-01-2011 |
Patent application number | Description | Published |
20080198658 | MEMORY CARD, SEMICONDUCTOR DEVICE, AND METHOD OF CONTROLLING MEMORY CARD - A semiconductor device includes a transfer section which receives, from an external source, a second program for modifying a function of a first program stored in a read-only memory (ROM) and information required in activation of the second program, and which writes the program and the information to a nonvolatile semiconductor memory, and a load section which activates the second program on the basis of the information written to the nonvolatile semiconductor memory to modify the function of the first program. | 08-21-2008 |
20100074019 | MEMORY CARD, SEMICONDUCTOR DEVICE, AND METHOD OF CONTROLLING MEMORY CARD - A semiconductor device includes a transfer section which receives, from an external source, a second program for modifying a function of a first program stored in a read-only memory (ROM) and information required in activation of the second program, and which writes the program and the information to a nonvolatile semiconductor memory, and a load section which activates the second program on the basis of the information written to the nonvolatile semiconductor memory to modify the function of the first program. | 03-25-2010 |
20100254187 | MEMORY SYSTEM AND CONTROL METHOD THEREOF - A memory system includes a cell array including a plurality of nonvolatile memory cells electrically connected to a common word line, each memory cell storing a plurality of bits including a plurality of potential ranks, and a controller measuring a potential of the memory cell for each potential rank and changing a lower limit and upper limit of the potential rank based on the measurement result. | 10-07-2010 |
Patent application number | Description | Published |
20090154280 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a nonvolatile memory and a controller unit for the nonvolatile memory. The nonvolatile memory and the controller unit include a first logic section and a second logic section, respectively. The nonvolatile memory includes a voltage detector configured to detect a power supply voltage externally supplied to the nonvolatile memory and the controller unit, and an output of the detection is supplied to the first logic section of the nonvolatile memory provided with the voltage detector, and also to the second logic section of the controller unit and/or a logic section of at least one added nonvolatile memory via a buffer amplifier, simultaneously. | 06-18-2009 |
20100162055 | MEMORY SYSTEM, TRANSFER CONTROLLER, AND MEMORY CONTROL METHOD - A memory system includes a nonvolatile memory, a volatile buffer memory connected to the nonvolatile memory, an error counting unit that detects, for each of divided areas formed by dividing a storage area of the volatile buffer memory into a plurality of areas, a parity error in inputting data to and outputting data from the divided areas and counts a number of times of accumulation of the parity error, and a control unit that sets the divided area, in which the number of times of accumulation of the parity error counted by the error counting unit exceeds a predetermined number of times, in a disabled state. | 06-24-2010 |
20100199025 | MEMORY SYSTEM AND INTERLEAVING CONTROL METHOD OF MEMORY SYSTEM - A memory system comprising: a plurality of nonvolatile memory areas capable of operating individually; and a memory controller connected to each of the memory areas individually via a ready/busy signal for interleaving an operation in the memory areas by changing a memory area as a target of an operation command, every time the operation command is transmitted, wherein the memory controller includes a priority-level managing unit that manages a level of selection priority for each memory area, so that after transmission of an operation command, the memory controller selects a memory area with a highest level of selection priority from memory areas in a ready state, to change the selected memory area to a target of a next operation command, and shifts the level of selection priority of the selected memory area at a time of next selection to a lowest level by the priority-level managing unit. | 08-05-2010 |
20110273939 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a nonvolatile memory and a controller unit for the nonvolatile memory. The nonvolatile memory and the controller unit include a first logic section and a second logic section, respectively. The nonvolatile memory includes a voltage detector configured to detect a power supply voltage externally supplied to the nonvolatile memory and the controller unit, and an output of the detection is supplied to the first logic section of the nonvolatile memory provided with the voltage detector, and also to the second logic section of the controller unit and/or a logic section of at least one added nonvolatile memory via a buffer amplifier, simultaneously. | 11-10-2011 |