Dahlstrom, US
David Dahlstrom, Hubbardston, MA US
Patent application number | Description | Published |
---|---|---|
20140266675 | METHOD FOR INSPECTING AND TESTING NOTIFICATION APPLIANCES IN ALARM SYSTEMS - A method for inspecting notification appliances in an alarm system. The method may include placing the alarm system in an inspection mode, whereby a verification indicium on each notification appliance being inspected is activated. The method may further include performing a physical inspection of a notification appliance, as well as actuating an input device on the notification appliance whereby the verification indicium on the notification appliance is deactivated. A first alternative method may include placing the alarm system in a test mode, whereby a verification indicium on each notification appliance being inspected and tested is activated. The first alternative method may further include performing a physical inspection of a notification appliance, as well as actuating an input device on the notification appliance whereby the verification indicium on the notification appliance is deactivated and a notification feature of the notification appliance is activated for a predefined amount of time. | 09-18-2014 |
20140266676 | METHOD FOR SELF-TESTING NOTIFICATION APPLIANCES IN ALARM SYSTEMS - A method for self-testing notification appliances in an alarm system by determining whether the performance of the notification appliances has degraded over time. The method may include the steps of measuring and recording initial output levels of notification features of the notification appliances at a first time, measuring test output levels of the notification features at a second time after the first time, and comparing the test output levels to respective threshold output levels that are derived from the initial output levels. The method may further include recording a pass result for notification appliances whose notification features produced test output levels that exceeded the respective threshold output levels, and recording a fail result for notification appliances whose notification features produced test output levels that did not exceed the respective threshold output levels. | 09-18-2014 |
20140266677 | METHOD FOR TESTING NOTIFICATION APPLIANCES IN ALARM SYSTEMS - A method for testing notification appliances in an alarm system and creating a record of such testing including the steps of placing an alarm system in a test mode, actuating an input device of a notification appliance in the alarm system a first time, whereby a notification feature of the notification appliance is activated for a test period, and automatically entering a waiting period after expiration of the test period. The method may further include actuating the input device of the notification appliance a second time during the waiting period, whereby a pass signal is transmitted from the notification appliance, and creating a record of the pass signal. The method may further include transmitting a fail signal from the notification appliance after expiration of the waiting period if the input device of the notification appliance was not actuated during the waiting period and creating a record of the fail signal. | 09-18-2014 |
20140340215 | METHOD FOR SELF-TESTING NOTIFICATION APPLIANCES IN ALARM SYSTEMS - A method for self-testing notification appliances in an alarm system, including the steps of measuring ambient noise at a notification appliance, comparing the measured ambient noise to a threshold ambient noise level, and performing a self-test of the notification appliance if the measured ambient noise does not exceed the threshold ambient noise level. The method may further include the step of recording a fail result for the notification appliance if the measured ambient noise exceeds the threshold ambient noise level. Performing the self-test of the notification appliance may include the steps of activating a notification feature of the notification appliance, measuring output of the notification feature, comparing the measured output to a predefined value, recording a pass result for the notification appliance if the measured output exceeds the predefined value, and recording a fail result for the notification appliance if the measured output does not exceed the predefined value. | 11-20-2014 |
20140375449 | SYSTEM AND METHOD FOR VERIFYING ASSOCIATIONS BETWEEN INTIATING DEVICES AND NOTIFICATIONS APPLICANCES IN ALARM SYSTEMS - A method for verifying associations between initiating devices and notification appliances in an alarm system. The method may include including actuating an initiating device of the alarm system, thereby activating one or more notification appliances that are associated with the initiating device. The method may further include deactivating each notification appliance that is expected to be associated with the actuated initiating device and, at an alarm panel, providing an indication of whether there are any notification appliances that are still active. | 12-25-2014 |
Erik M. Dahlstrom, Los Altos, CA US
Patent application number | Description | Published |
---|---|---|
20130313607 | Silicon Controlled Rectifier With Stress-Enhanced Adjustable Trigger Voltage - Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR. | 11-28-2013 |
Erik M. Dahlstrom US
Patent application number | Description | Published |
---|---|---|
20120221987 | VERTICAL HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE - Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening. | 08-30-2012 |
Erik M. Dahlstrom, Los Alto, CA US
Patent application number | Description | Published |
---|---|---|
20140030861 | STRESS ENHANCED LDMOS TRANSISTOR TO MINIMIZE ON-RESISTANCE AND MAINTAIN HIGH BREAKDOWN VOLTAGE - A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate. | 01-30-2014 |
Erik M. Dahlstrom, Burlington, VT US
Patent application number | Description | Published |
---|---|---|
20080204068 | METHOD FOR ESTIMATING DEFECTS IN AN NPN TRANSISTOR ARRAY - A method for testing bipolar transistors in an integrated circuit includes first measuring first conductances of leakage paths between collectors and emitters of a first plurality of bipolar transistors with a known number of defects, calculating a per defect conductance value using the measured first conductances and the known number of defects to derive the linear relation. The method then measures second conductances of leakage path between collectors and emitters of a second plurality of bipolar transistors under test and having an unknown number of defects. Using the measured leakage path current from the second conductances and the linear relation, the number of defects related to the second plurality of bipolar transistors under test may be accurately determined. | 08-28-2008 |
20090101887 | SILICON GERMANIUM HETEROSTRUCTURE BARRIER VARACTOR - Methods and heterostructure barrier varactor (HBV) diodes optimized for application with frequency multipliers at providing outputs at submillimeter wave frequencies and above. The HBV diodes include a silicon-containing substrate, an electrode over the silicon-containing substrate, and one or more heterojunction quantum wells of alternating layers of Si and SiGe of one or more electrodes of the diode. Each SiGe quantum well preferably has a floating SiGe layer between adjacent SiGe gradients followed by adjacent Si layers, such that, a single homogeneous structure is provided characterized by having no distinct separations. The plurality of Si/SiGe heterojunction quantum wells may be symmetric or asymmetric. | 04-23-2009 |
20100093148 | SILICON GERMANIUM HETEROSTRUCTURE BARRIER VARACTOR - Methods and heterostructure barrier varactor (HBV) diodes optimized for application with frequency multipliers at providing outputs at submillimeter wave frequencies and above. The HBV diodes include a silicon-containing substrate, an electrode over the silicon-containing substrate, and one or more heterojunction quantum wells of alternating layers of Si and SiGe of one or more electrodes of the diode. Each SiGe quantum well preferably has a floating SiGe layer between adjacent SiGe gradients followed by adjacent Si layers, such that, a single homogeneous structure is provided characterized by having no distinct separations. The plurality of Si/SiGe heterojunction quantum wells may be symmetric or asymmetric. | 04-15-2010 |
20120112244 | VERTICAL HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE - Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening. | 05-10-2012 |
20120126292 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE RESISTANCE - Heterojunction bipolar transistors with reduced base resistance, as well as fabrication methods for heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The heterojunction bipolar transistor includes a conductive layer between the intrinsic base and the extrinsic base. The conductive layer is comprised of a conductive material, such as a silicide, having a lower resistivity than the materials forming the intrinsic base and the extrinsic base. | 05-24-2012 |
20120228611 | BIPOLAR JUNCTION TRANSISTOR WITH A SELF-ALIGNED EMITTER AND BASE - Methods for fabricating bipolar junction transistors with self-aligned emitter and extrinsic base, bipolar junction transistors made by the methods, and design structures for a BiCMOS integrated circuit. The bipolar junction transistor is fabricated using a sacrificial emitter pedestal that provides a sacrificial mandrel promoting self-alignment between the emitter and the extrinsic base. The sacrificial emitter pedestal is subsequently removed to open an emitter window extending to the intrinsic base. An emitter is formed in the emitter window that lands on the intrinsic base. | 09-13-2012 |
20120326766 | Silicon Controlled Rectifier with Stress-Enhanced Adjustable Trigger Voltage - Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR. | 12-27-2012 |
20130062668 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE RESISTANCE - Heterojunction bipolar transistors with reduced base resistance, as well as fabrication methods for heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The heterojunction bipolar transistor includes a conductive layer between the intrinsic base and the extrinsic base. The conductive layer is comprised of a conductive material, such as a silicide, having a lower resistivity than the materials forming the intrinsic base and the extrinsic base. | 03-14-2013 |
Erik M. Dahlstrom, Santa Clara, CA US
Patent application number | Description | Published |
---|---|---|
20130140566 | BIPOLAR JUNCTION TRANSISTOR WITH A SELF-ALIGNED EMITTER AND BASE - Methods for fabricating bipolar junction transistors with self-aligned emitter and extrinsic base, bipolar junction transistors made by the methods, and design structures for a BiCMOS integrated circuit. The bipolar junction transistor is fabricated using a sacrificial emitter pedestal that provides a sacrificial mandrel promoting self-alignment between the emitter and the extrinsic base. The sacrificial emitter pedestal is subsequently removed to open an emitter window extending to the intrinsic base. An emitter is formed in the emitter window that lands on the intrinsic base. | 06-06-2013 |
Erik Mattias Dahlstrom, Burlington, VT US
Patent application number | Description | Published |
---|---|---|
20120306014 | STRESS ENHANCED LDMOS TRANSISTOR TO MINIMIZE ON-RESISTANCE AND MAINTAIN HIGH BREAKDOWN VOLTAGE - A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate. | 12-06-2012 |
Greg Dahlstrom, Post Falls, ID US
Patent application number | Description | Published |
---|---|---|
20110232546 | Fluidized bed - A fluidized bed is described and which includes a multiplicity of fluidizing manifolds positioned in spaced relation one relative to the others; an enclosure positioned in gravity receiving relation relative to the multiplicity of fluidizing manifolds and which has an intake and a discharge end, and wherein particulate matter received in the fluidized bed moves under the influence of gravity from the intake end to the discharge end, and a moveable gate is mounted on the second discharge end of the enclosure and which is operable to selectively occlude a discharge aperture and which further facilitates the selective removal of particulate matter and waste material entrained with same, and which moves under the influence of gravity to the discharge end thereof. | 09-29-2011 |
Jacob A. Dahlstrom, Cottage Grove, MN US
Patent application number | Description | Published |
---|---|---|
20100282167 | Linear Deposition Source - A deposition source includes a crucible for containing deposition material and a body comprising a conductance channel. An input of the conductance channel is coupled to an output of the crucible. A heater heats the crucible so that the crucible evaporates the deposition material into the conductance channel. A heat shield comprising a plurality of heat resistant material layers is positioned around at least one of the heater and the body. A plurality of nozzles is coupled to an output of the conductance channel so that evaporated deposition material is transported from the crucible through the conductance channel to the plurality of nozzles where the evaporated deposition material is ejected from the plurality of nozzles to form a deposition flux. | 11-11-2010 |
20100285218 | Linear Deposition Source - A deposition source includes at least one crucible for containing deposition material. A body includes a conductance channel with an input coupled to an output of the crucible. A heater increases a temperature of the crucible so that the crucible evaporates the deposition material into the conductance channel. A plurality of nozzles is coupled to an output of the conductance channel so that evaporated deposition material is transported from the crucible through the conductance channel to the plurality of nozzles where the evaporated deposition material is ejected from the plurality of nozzles to form a deposition flux. At least one of the plurality of nozzles includes a tube that is positioned proximate to the conductance channel so that the tube restricts an amount of deposition material supplied to the nozzle including the tube. | 11-11-2010 |
Jacob Allan Dahlstrom, Cottage Grove, MN US
Patent application number | Description | Published |
---|---|---|
20100159132 | Linear Deposition Source - A deposition source includes a plurality of crucibles that each contains a deposition material. A heat shield provides at least partial thermal isolation for at least one of the plurality of crucibles. A body is included with a plurality of conductance channels. An input of each of the plurality of conductance channels is coupled to an output of a respective one of the plurality of crucibles. A heater increases a temperature of the plurality of crucibles so that each crucible evaporates the deposition material into the plurality of conductance channels. An input of each of a plurality of nozzles is coupled to an output of one of the plurality of conductance channels. Evaporated deposition materials are transported from the crucibles through the conductance channels to the nozzles where the evaporated deposition material is ejected from the plurality of nozzles to form a deposition flux. | 06-24-2010 |
Jonathan Dahlstrom, Highland, MI US
Patent application number | Description | Published |
---|---|---|
20130322041 | PRINTED CIRCUIT BOARD ASSEMBLY AND SOLDER VALIDATION METHOD - A solder validation method for a printed circuit board (PCB) having a pin hole extending through the PCB, an electrically conductive trace on a surface of the PCB, and an electrically conductive pin inserted through the pin hole includes the following. An electrically non-conductive portion is provided on the surface of the PCB between the pin hole and the trace such that the non-conductive portion electrically isolates the pin from the trace. After a soldering process intended to solder the pin and the trace together, a soldered connection between the pin and the trace is detected as being absent when no electrical continuity is between the pin and the trace as a soldered connection between the pin and the trace has to be present to provide the electrical continuity due to the pin and the trace otherwise being electrically isolated from one another by the non-conductive portion. | 12-05-2013 |
20140154898 | ELECTRICAL CENTER AND CONNECTOR ASSEMBLY SYSTEM - An electrical junction box has a connector retainer assembly with a first contact surface, as well as a connector housing assembly with a pivotal lever arm. The lever arm has a first engagement surface. The connector retainer assembly and the connector housing assembly configured so that when the lever arm is moved in a single direction relative to the connector housing assembly, the first engagement surface engages the first contact surface and the connector housing assembly moves relative to the connector retainer assembly from a pre-staged position to an assembled position. | 06-05-2014 |
J. Reeves Dahlstrom, Arvada, CO US
Patent application number | Description | Published |
---|---|---|
20090092718 | Ultra-high temperature oven for processing fish and seafood - An oven and method of processing products such as fish and shellfish are disclosed. The oven may include a chamber that may be heated to ultra-high temperatures, such as within a range of about 600-2500° F. (315-1371° C.). A burner may heat the chamber from an exterior of the chamber such that the chamber may provide a uniform radiant heat inside the chamber. The products may be carried through the chamber on a conveyor belt to heat a surface of the products to brown and denature the surface, destroy microorganisms, and place grill marks on the products. The products may then be packaged in a microwavable package or boil-in-the-bag film such that the products may be cooked at a later time in a microwave oven or boiling water bath. | 04-09-2009 |
Karl Louis Dahlstrom, Celina, TX US
Patent application number | Description | Published |
---|---|---|
20160032821 | Six Stroke Internal-Combustion Engine - A method for modification and improvement in internal combustion engine systems utilizing six strokes (1. an intake stroke, 2. a compression stroke, 3. a power stroke, 4. an exhaust stroke, 5. an intake-cooling stroke and 6. an exhaust-cooling stroke) and incorporating changes to the camshaft lobes and valve train timing providing for a 3:1 camshaft to crankshaft ratio allowing for higher revolutions per minute, lower idling speeds, reduced valve float and smoother operation. The system provides for more efficient fuel combustion during the power stroke, which extends past bottom dead center thus increasing power, fuel efficiency, and greatly reduces harmful emissions. The additional fifth and sixth strokes provide for intake and exhaust cooling. The system demonstrates increased reliability, efficiency, and a cooler operating environment while operating with various fuels. | 02-04-2016 |
Kurt Dahlstrom, Emeryville, CA US
Patent application number | Description | Published |
---|---|---|
20150100979 | SYSTEM AND METHOD FOR CREATING CONTEXTUAL MESSAGES FOR VIDEOS - Described herein are techniques for creating contextual messages for videos. In one example, there is provided a method operable by a network entity, involving receiving a request to create a video clip of a media broadcast. The network entity may identify a video segment of the media broadcast then determines a context identifier for the video segment. The network entity may create a contextual message to accompany the video segment based on the context identifier and may provide the contextual message along with the video segment to a clip viewer. | 04-09-2015 |
Mary Ann Dahlstrom, Katy, TX US
Patent application number | Description | Published |
---|---|---|
20110232169 | FUEL COMPOSITIONS - A fuel composition having an enhanced thermal stability in a diesel fuel application is provided comprising a base fuel containing: | 09-29-2011 |
20130102817 | PROCESS TO PREPARE JET FUELS AND ITS PRODUCTS - A jet fuel containing a major amount of a synthetic paraffinic kerosene fuel component is provided by: | 04-25-2013 |
20130240404 | DIESEL FUEL AND A METHOD OF OPERATING A DIESEL ENGINE - A diesel fuel based on a blend of a diesel fuel derived from a Fischer-Tropsch process, and a mineral oil based diesel fuel having a sulfur content of less than 100 ppmw; and a method of operating a diesel engine, which method involves combusting such diesel fuel in the diesel engine. | 09-19-2013 |
20150315507 | FISCHER-TROPSCH DERIVED FUEL COMPOSITIONS - A fuel composition comprising a Fischer-Tropsch derived middle distillate fuel and a middle distillate flow improver, the remainder being another fuel component or mixture of fuel components. The other fuel component is selected from petroleum derived middle distillate fuel, hydrogenated vegetable oil, fatty acid methyl esters, and other Fischer Tropsch products. The Fischer-Tropsch derived middle distillate fuel is more than 80% v/v of the total composition; the maximum weight content in the carbon number distribution of the n-paraffins in the Fischer-Tropsch derived middle distillate fuel is below C16 and the weight ratio of iso to normal paraffins in the Fischer-Tropsch derived middle distillate fuel is 3.5:1 or higher. The middle distillate flow improver is a substituted ethylene polymer. | 11-05-2015 |
Mattias E. Dahlstrom, Los Alto, CA US
Patent application number | Description | Published |
---|---|---|
20150044862 | PHASE CHANGING ON-CHIP THERMAL HEAT SINK - A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip. | 02-12-2015 |
20150048494 | PHASE CHANGING ON-CHIP THERMAL HEAT SINK - A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip. | 02-19-2015 |
20150054131 | PHASE CHANGING ON-CHIP THERMAL HEAT SINK - A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip. | 02-26-2015 |
20150056777 | DEVICE ISOLATION WITH IMPROVED THERMAL CONDUCTIVITY - A method of making a semiconductor structure includes forming a trench through a shallow trench isolation (STI) structure and into a substrate, and forming a liner including an electrical insulator material on sidewalls of the trench. The method also includes forming a core including a high thermal conductivity material in the trench and on the liner, and forming a cap in the trench and on the core. | 02-26-2015 |
20150243529 | PHASE CHANGING ON-CHIP THERMAL HEAT SINK - A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip. | 08-27-2015 |
Mattias E. Dahlstrom, Burlington, VT US
Patent application number | Description | Published |
---|---|---|
20110309471 | TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE STRUCTURE - Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance C | 12-22-2011 |
20120146098 | DEVICE ISOLATION WITH IMPROVED THERMAL CONDUCTIVITY - A method of making a semiconductor structure includes forming a trench through a shallow trench isolation (STI) structure and into a substrate, and forming a liner including an electrical insulator material on sidewalls of the trench. The method also includes forming a core including a high thermal conductivity material in the trench and on the liner, and forming a cap in the trench and on the core. | 06-14-2012 |
20140183699 | PHASE CHANGING ON-CHIP THERMAL HEAT SINK - A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip. | 07-03-2014 |
Mattias E. Dahlstrom, Essex Junction, VT US
Patent application number | Description | Published |
---|---|---|
20100320571 | BIPOLAR TRANSISTOR STRUCTURE AND METHOD INCLUDING EMITTER-BASE INTERFACE IMPURITY - A bipolar transistor structure and a method for fabricating the bipolar transistor structure include: (1) a collector structure located at least in-part within a semiconductor substrate; (2) a base structure contacting the collector structure; and (3) an emitter structure contacting the base structure. The interface of the emitter structure and the base structure includes an oxygen impurity and at least one impurity selected from the group consisting of a fluorine impurity and a carbon impurity, to enhance performance of a bipolar transistor within the bipolar transistor structure. The impurities may be introduced into the interface by plasma etch treatment, or alternatively a thermal treatment followed by an anhydrous ammonia and hydrogen fluoride treatment, of a base material from which is comprised the base structure. | 12-23-2010 |
Paul Dahlstrom, Hollis, NH US
Patent application number | Description | Published |
---|---|---|
20130280024 | APPARATUS AND METHODS FOR DISPENSING SAMPLE HOLDERS - An apparatus and methods for dispensing sample holders for use in an automated sample analyzer is disclosed herein. The apparatus for dispensing sample holders includes a rotating carousel for housing stack of sample holders. Stacks of sample holders from the rotating carousel are fed into a chute where sample holders contact a set of rotating members having helical threads thereon. The helically threaded rotating members engage the sample containers and separate each sample holder from the remaining sample holders in the stack by rotation of the helically threaded rotating members. The sample holder can then be transferred for use in an automated sample analyzer. | 10-24-2013 |
Paul C. Dahlstrom, Hollis, NH US
Patent application number | Description | Published |
---|---|---|
20090129988 | Reagent Container Pack - A reagent container pack for storing, preserving, and automatically unsealing and resealing a plurality of reagent containers in a reagent container pack on-board an automated clinical sample analyzer for analyzing analytes in a body fluid. | 05-21-2009 |
20100196202 | APPARATUS AND METHODS FOR DISPENSING SAMPLE HOLDERS - An apparatus and methods for dispensing sample holders for use in an automated sample analyzer is disclosed herein. The apparatus for dispensing sample holders includes a rotating carousel for housing stack of sample holders. Stacks of sample holders from the rotating carousel are fed into a chute where sample holders contact a set of rotating members having helical threads thereon. The helically threaded rotating members engage the sample containers and separate each sample holder from the remaining sample holders in the stack by rotation of the helically threaded rotating members. The sample holder can then be transferred for use in an automated sample analyzer. | 08-05-2010 |
20140287525 | Reagent Container Pack - A reagent container pack for storing, preserving, and automatically unsealing and resealing a plurality of reagent containers in a reagent container pack on-board an automated clinical sample analyzer for analyzing analytes in a body fluid. | 09-25-2014 |
20140322098 | MAGNETIC PARTICLE WASHING STATION - Embodiments of the invention relate to a clinical instrument analyzer system for the automatic analysis of patient samples. In one embodiment, the analyzer may be used to analyze bodily fluid samples, such as blood, plasma, serum, urine or cerebrospinal fluid, for example. Embodiments of the invention relate to an apparatus and method, for example, an immunoassay method, for separating out target molecules in a magnetic field and then analyzing those target molecules with a luminometer. | 10-30-2014 |
Philip Robert Dahlstrom, Cleveland, OH US
Patent application number | Description | Published |
---|---|---|
20090014482 | Feeder Element for Metal Casting - The present invention discloses a feeder element for use in metal casting, said feeder element comprising: (i) a first end for mounting on a mould pattern; (ii) an opposite second end for receiving a feeder sleeve,—and (iii) a bore between—the first and second ends defined by a stepped sidewall; said feeder element being compressible in use whereby to reduce the distance between the first and second ends, wherein the stepped sidewall has a first sidewall region defining the second end of the element and a mounting surface ( | 01-15-2009 |
Robert L. Dahlstrom, Jacksonville, FL US
Patent application number | Description | Published |
---|---|---|
20150274294 | Indoor and Outdoor Aerial Vehicles for Painting and Related Applications - An aerial operations system for performing various tasks such as painting is provided. The modular aerial operations system includes an aerial vehicle capable of vertically taking off and landing, hovering and precisely maneuvering near walls and other structures. The aerial vehicle may be a rotorcraft such as a multicopter. In an aspect, as aerial vehicle paints one or more designated surfaces using detachable arms and equipment. The system may paint the designated surface in one of several available techniques using paint provided in a container such as an attached reservoir, a base station, a paint can, or the like. The aerial operations system provided may also be configured to perform a variety of other tasks. | 10-01-2015 |
20150344136 | MOBILE COMPUTING DEVICE-BASED GUIDANCE NAVIGATION AND CONTROL FOR UNMANNED AERIAL VEHICLES AND ROBOTIC SYSTEMS - A system is disclosed including an aerial vehicle to perform a task to an object, while in an aerial mode that includes at least one of a hover mode or a slow movement mode during a predominant phase of the task being performed, the aerial vehicle has a command and control system, a removable mobile computing device that when attached to the aerial vehicle assists in control of the aerial vehicle and when detached assists in control of the aerial vehicle with user intervention through the mobile device, wherein assist in control is further performed through the command and control system and at least one attachment attachable to the aerial vehicle for facilitating the task performed to the object by the aerial vehicle while the aerial vehicle is in the aerial mode, the at least one attachment is controlled by the removable mobile computing device. Methods are also disclosed. | 12-03-2015 |
Robert Lawrence Dahlstrom, Cottage Grove, MN US
Patent application number | Description | Published |
---|---|---|
20100031940 | Aerosol Separator; Components; and, Methods - Arrangements for use in crankcase ventilation are described and shown. Included are serviceable crankcase ventilation filter cartridges which include a media pack axial drain arrangement, for preferred, efficient, operation. A crankcase ventilation filter arrangements including a housing and such a serviceable cartridge is shown. Also shown and described are methods of assembly, operation and use. | 02-11-2010 |