Chia-Jen
Chia-Jen Chang, Taoyuan County TW
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20130051495 | INTERACTIVE DIGITAL DUTY CYCLE COMPENSATION CIRCUIT FOR RECEIVER - A receiver circuit. A receiving stage is coupled to a first supply voltage and an input signal, and operative to generate a first intermediate signal from the input signal based on the first supply voltage. A compensation stage is coupled to a second supply voltage and the first intermediate signal, and operative to generate a second intermediate signal by adjusting duty cycle of the first intermediate signal upon detecting changes in the first supply voltage to compensate for the changes in the first supply voltage. An outputting stage is coupled to the second supply voltage and operative to generate an output signal based on the second supply voltage upon receiving the second intermediate signal. A voltage of the output signal is adjusted to a level of the second supply voltage and the output signal has a 50% duty cycle. | 02-28-2013 |
Chia-Jen Chang, Hsinchu City TW
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20130075728 | ARRAY SUBSTRATE AND DISPLAY APPARATUS USING THE SAME - An array substrate includes scan lines and data lines defining pixel structures. Each pixel structure includes a first TFT, a second TFT and a pixel electrode. The first TFT includes a first gate connected to the scan line, a first source disposed above and partially overlapping the first gate, and a first drain disposed above the first gate. An end of the first source is connected to the data line. The first drain has at least one first concavity in which the first source is disposed partially. The second TFT includes a second gate connected to the scan line, a second source disposed above the second gate and connected to the first drain, and a second drain disposed above and partially overlapping the second gate. The second source has at least one second concavity in which the second drain is disposed partially. The pixel electrode connects to the second drain. | 03-28-2013 |
Chia-Jen Chang, Hsinchu TW
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20120221876 | LOW POWER CONSUMPTION CIRCUIT AND METHOD FOR REDUCING POWER CONSUMPTION - An exemplary low power consumption circuit includes a microprocessor, a power supply switch module and a main circuit module. The microprocessor is capable of outputting a power control signal and changing a pulse characteristic of the power control signal when the microprocessor switches from a first working mode to a second working mode. The power supply switch module is capable of outputting a power supply signal. The power supply switch module is electrically coupled to the microprocessor to receive the power control signal and thereby modulates a duty cycle of the power supply signal according to a change of the pulse characteristic of the power control signal. The main circuit module is electrically coupled to the power supply switch module to receive the power supply signal and operative with energy provided by the power supply signal. Moreover, a method for reducing power consumption is also provided. | 08-30-2012 |
Chia-Jen Chen, Chiayi TW
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20130119487 | Structure and Method for MOSFETS with High-K and Metal Gate Structure - The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; and a gate stack disposed on the semiconductor substrate. The gate stack includes a high k dielectric material layer, a capping layer disposed on the high k dielectric material layer, and a metal layer disposed on the capping layer. The capping layer and the high k dielectric material layer have a footing structure. | 05-16-2013 |
20130187235 | COMPOSITE DUMMY GATE WITH CONFORMAL POLYSILICON LAYER FOR FINFET DEVICE - The present disclosure involves a FinFET. The FinFET includes a fin structure formed over a substrate. A gate dielectric layer is least partially wrapped around a segment of the fin structure. The gate dielectric layer contains a high-k gate dielectric material. The FinFET includes a polysilicon layer conformally formed on the gate dielectric layer. The FinFET includes a metal gate electrode layer formed over the polysilicon layer. The present disclosure provides a method of fabricating a FinFET. The method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a polysilicon layer over the gate dielectric layer, wherein the polysilicon layer is formed in a conformal manner. The method includes forming a dummy gate layer over the polysilicon layer. | 07-25-2013 |
20140134759 | METHOD OF FORMING A PATTERN - An embodiment of a method of forming a substrate pattern including forming a bottom layer and an overlying middle layer on the substrate. A photo resist pattern is formed on the middle layer. An etch coating layer is deposited on the photo resist pattern. The etch coating layer and the photo resist pattern are used as a masking element to pattern at least one of the middle layer and the bottom layer. The substrate is etched to form the substrate pattern using the at least one of the patterned middle layer and the patterned bottom layer as a masking element. The substrate pattern may be used as an element of an overlay measurement process. | 05-15-2014 |
Chia-Jen Chen, Kaohsiung City TW
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20120129633 | SPORTS TRAINING DEVICE - A sports training device includes a base and at least one net frame assembly. The net frame assembly includes a frame mounted detachably to the base, and a net attached to and surrounded by the frame. The net includes a non-elastic mesh area, and an elastic mesh area connecting the non-elastic mesh area to the frame. | 05-24-2012 |
Chia-Jen Chen, Hsinchu County TW
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20090027643 | COMPENSATION OF RETICLE FLATNESS ON FOCUS DEVIATION IN OPTICAL LITHOGRAPHY - A method for lithography patterning includes providing a mask for photolithography patterning; measuring a mask flatness of the mask; calculating focal deviation of imaging the mask to a substrate in a lithography apparatus; adjusting the lithography apparatus to have a compensated focal plane of the mask based on the focal deviation; and exposing the semiconductor substrate utilizing the mask and the lithography apparatus with adjusted focal plane. | 01-29-2009 |
20130298088 | System and Method for Combined Intraoverlay and Defect Inspection - A method and system for measuring layer overlay and for inspecting a mask for defects unrelated to overlay utilizing a singe comprehensive tool is disclosed. An exemplary method includes receiving a mask design database that corresponds to a mask and has a die area with a mask database feature. A mask image of the mask is received, and a comprehensive inspection system compares the mask image to the mask design database in order to detect mask defects that are not related to layer alignment. The system produces mask defect information corresponding to the mask defects. The comprehensive inspection system also compares the mask image to the mask design database to determine a database-to-mask offset. From the database-to-mask offset, a mask overlay characteristic is determined. | 11-07-2013 |
20150205194 | Lithography Mask - The present disclosure provides a lithography mask comprising a substrate, a reflective multiplayer (ML) on the substrate, a barrier layer on the reflective ML, and an absorber layer over the barrier layer. In some embodiments, a thickness of the barrier layer is less than or equal to about 10 nm. In some embodiments, a portion of the absorber layer and a portion of the barrier layer are removed. The present disclosure also provides a method for fabricating a lithography mask, and a method for patterning a substrate using a lithography mask. | 07-23-2015 |
20150227037 | Structure and Method of Photomask with Reduction of Electron-Beam Scatterring - The present disclosure provides a structure of a photomask. The photomask includes a substrate; and a conductive material layer dispose over the substrate and patterned to include a plurality of openings and a recess structure surrounding the plurality of openings. | 08-13-2015 |
Chia-Jen Cheng, Banciao City TW
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20120306070 | Electrical Connection for Chip Scale Packaging - A system and method for providing a post-passivation and underbump metallization is provided. An embodiment comprises a post-passivation layer that is larger than an overlying underbump metallization. The post-passivation layer extending beyond the underbump metallization shields the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion. | 12-06-2012 |
20140113447 | Electrical Connection for Chip Scale Packaging - A system and method for providing a post-passivation and underbump metallization is provided. An embodiment comprises a post-passivation layer that is larger than an overlying underbump metallization. The post-passivation layer extending beyond the underbump metallization shields the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion. | 04-24-2014 |
20150235976 | Electrical Connection for Chip Scale Packaging - A system and method for providing a post-passivation and underbump metallization is provided. An embodiment comprises a post-passivation layer that is larger than an overlying underbump metallization. The post-passivation layer extending beyond the underbump metallization shields the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion. | 08-20-2015 |
Chia-Jen Cheng, Banciao TW
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20080303154 | Through-silicon via interconnection formed with a cap layer - An integrated circuit structure and methods for forming the same are provided. The method includes providing a substrate; forming a through-silicon via (TSV) opening extending into the substrate; forming an under-bump metallurgy (UBM) in the TSV opening, wherein the UBM extends out of the TSV opening; filling the TSV opening with a metallic material; forming a patterned cap layer on the metallic material; and etching a portion of the UBM outside the TSV opening, wherein the patterned cap layer is used as a mask. | 12-11-2008 |
20090026608 | Crosstalk-Free WLCSP Structure for High Frequency Application - A structure, a system, and a method for manufacture of crosstalk-free wafer level chip scale packaging (WLCSP) structure for high frequency applications is provided. An illustrative embodiment comprises a substrate on which various layers and structures form circuitry, a signal pin formed on the substrate and coupled with the circuitry, a ground ring encircling the signal pin, and a grounded solder bump coupled to the ground ring. | 01-29-2009 |
20090115058 | Back End Integrated WLCSP Structure without Aluminum Pads - An integrated circuit structure includes a passivation layer; a via opening in the passivation layer; a copper-containing via in the via opening; a polymer layer over the passivation layer, wherein the polymer layer comprises an aperture, and wherein the copper-containing via is exposed through the aperture; a post-passivation interconnect (PPI) line over the polymer layer, wherein the PPI line extends into the aperture and physically contacts the copper-via opening; and an under-bump metallurgy (UBM) over and electrically connected to the PPI line. | 05-07-2009 |
Chia-Jen Hsu, Taichung City TW
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20150279796 | QUAD-FLAT NO-LEADS PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a quad-flat no-leads package (QFN) structure includes: forming a conducting layer on a surface of a thin-film layer; forming a plurality of conduction wirings from the conducting layer by a means of circuit layout; electrically connecting contact pads of a die to front ends of the conduction wirings, respectively; forming a plurality of through-holes in the thin-film layer by a means of drilling, such that terminal ends of the conduction wirings are exposed from the through-holes, respectively; and forming a plurality of metal bumps at the through-holes, respectively, such that signals from the die are sent to a bottom surface of the thin-film layer through the conduction wirings. Hence, the QFN structure and the method of manufacturing the same based on application of wafer-level chip-scale package (WLCSP) and extension of tape QFN to simplify the package manufacturing process, cut production costs, and enhance production yield. | 10-01-2015 |
Chia-Jen Hsu, Taipei City TW
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20090310810 | MEMS MICROPHONE PACKAGE WITH RF INSENSITIVE MEMS MICROPHONE CHIP - A micro-electro-mechanical-system microphone package includes a substrate, a micro-electro-mechanical-system microphone chip mounted on the substrate, and a cover attached to the substrate to cover the micro-electro-mechanical-system microphone chip. The cover is provided with a sound inlet through which the micro-electro-mechanical-system microphone receives external sound. The micro-electro-mechanical-system microphone chip includes a conductive base connected to a constant voltage, a shielding layer supported by the conductive base and connected to the constant voltage, a diaphragm disposed between the conductive base and the shielding layer, and a back plate also disposed between the conductive base and the shielding layer. | 12-17-2009 |
Chia-Jen Hsu, Los Angeles, CA US
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20080260323 | NON-ELECTRONIC RADIO FREQUENCY FRONT-END WITH IMMUNITY TO ELECTROMAGNETIC PULSE DAMAGE - A non-electronic all-dielectric (NEAD) or non-electronic RF (NERF) front-end that exploits isolation features of photonics to eliminate metal electrodes, interconnects and the antenna. An electro-optic (EO) modulator is integrated with a dielectric resonance antenna to exploit unique isolation features of photonics. A doubly (RF and optical) resonant device design maximizes the receiver sensitivity. High-Q optical disk resonators and dielectric resonant antennas are integrated to create an efficient mixing of light and RF fields. The resulting non-electronic RF technology produces an all-dielectric RF front-end which provides complete isolation between the air interface and the ensuing electronic circuitry, enabling the creation of an RF receiver that is immune to high-power electromagnetic pulses (EMP) and High Power Microwave (HPM) pulses. The device can also be configured as a non-intrusive field probe that co-exists with a conventional receiver and detects a EMP or HPM attack. | 10-23-2008 |
Chia-Jen Hsu, Irvine, CA US
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20130294294 | POWER-EFFICIENT DRIVER ARCHITECTURE - Disclosed are various embodiments for providing a power-efficient driver architecture supporting rail-to-rail operation in full duplex mode. A driver is configured to drive a duplex signal over a transmission medium. A hybrid is configured to recover a received signal from the duplex signal. The received signal is generated by a remote transceiver. The driver is configured to drive the duplex signal based at least in part on the received signal recovered by the hybrid. | 11-07-2013 |
Chia-Jen Hsu, Dounan Township TW
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20100326892 | DYNAMICALLY ADAPTIVE TROMMEL SCREEN SYSTEM - A dynamically real-time adaptive trommel screen system is revealed. The dynamically adaptive trommel screen system includes a fixture, a trommel screen disposed on the fixture for screening a mixture into regenerated filter granules and screened residues, a structured duct for transporting the regenerated filter granules and an enclosure for collecting the screened residues, a tilt control member arranged on the fixture for adjusting the tilt angle of the trommel screen, and a feedback controller that controls the tilt control member according to the mass flow rate of the screened residues when the trommel screen operates so as to adjust the tilt angle of the trommel screen instantly and dynamically. By the feedback controller and the tilt control member, the tilt angle of the trommel screen is adjusted in a real-time and dynamic way so as to increase the screening efficiency. Moreover, the state of fractured filter granules is acquired from the feedback controller so that a certain amount of fresh filter granules can be refilled into the filter system for improving the filtration efficiency. | 12-30-2010 |
Chia-Jen Kao, Hsin-Chu City TW
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20080270056 | WAFER-LEVEL RELIABILITY YIELD ENHANCEMENT SYSTEM AND RELATED METHOD - A yield enhancement system has a fabrication line with semiconductor fabrication devices for fabricating a wafer, an inspection and measurement monitoring system coupled to the fabrication line for determining process data corresponding to semiconductor fabrication devices, and a post-process testing line coupled to the fabrication line for performing in-line wafer-level testing. The post-process testing line includes a wafer acceptance tester, a yield monitor coupled to the wafer acceptance tester, and a wafer level reliability tester coupled to the wafer acceptance tester for estimating a life span of a device on the wafer. | 10-30-2008 |
Chia-Jen Kuo, Taipei TW
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20100270985 | DC-DC CONVERTER - A DC-DC converter includes a voltage input module receiving an input voltage from an exterior power supply, a voltage transforming module connected with the voltage input module for transforming the input voltage into a proper output voltage, a voltage output module connected with the voltage transforming module for supplying the proper output voltage to an exterior electric appliance, a first detecting module connected with the voltage output module for detecting an output current of the voltage output module and sending a corresponding current signal, a second detecting module connected with the voltage output module for detecting the output voltage of the voltage output module and sending a corresponding voltage signal, and a control module for receiving and analyzing the corresponding current and voltage signals and then generating a corresponding control signal so as to control the output voltage of the voltage transforming module for protecting the electric appliance. | 10-28-2010 |
Chia-Jen Lee, Taichung City TW
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20130313448 | LIGHT SPLITTING AND DETECTING SYSTEM - A light splitting and detecting system including at least one light splitting and detecting apparatus is provided. The light splitting and detecting apparatus is capable of receiving a first wavelength optical signal and a second wavelength optical signal. The light splitting and detecting apparatus includes a filter, light detecting unit, a first wavelength filtering unit and a slit. The filter is disposed on the transmission path of the first wavelength optical signal and the second wavelength optical signal. The first wavelength filtering unit is disposed between the filter and the light detecting unit. The slit is disposed between the first wavelength filtering unit and the light detecting unit and expose the light detecting unit. | 11-28-2013 |
Chia-Jen Lee, Taichung TW
Chia-Jen Lee, Taipei TW
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20100031687 | Conduit Joint for a Refrigerant Charging Device - A conduit joint for a refrigerant charging device comprises an upper housing including a connection tube disposed on the outer wall thereof and a first chamber formed therein, a conduit connected between the connection tube and an outlet, a first compression spring mounted in the fist chamber; a lower housing fitted on the upper housing and including a second chamber fixed therein for communicating with the first chamber and balls retained on the outer wall thereof; a leakproof ring disposed in the second chamber and on the valve stem; an action loop mounted in the second chamber and under the leakproof ring, wherein the action loop pushes the balls outward by using the leakproof ring; an outer cover fitted around the lower housing, between the outer cover and the lower housing is defined a second compression spring, wherein the outer cover is pushed to move upward by the balls. | 02-11-2010 |
Chia-Jen Lin, Hsinchu TW
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20140215501 | DISC CLAMPING STRUCTURE OF OPTICAL DISC DRIVE - A disc clamping structure is provided. A fixing base is disposed on a turntable. A plurality of ball seats are disposed around a periphery of the fixing base, and each of the ball seats has an aperture. The balls are received in the ball seats. The elastic members are disposed within the fixing base. The balls are upwardly moved, and the height of the center point of the ball is adjusted according to the thickness of the disc when the disc is clamped on the turntable. A portion of the ball is projected from the aperture of the ball seat before clamping the disc. | 07-31-2014 |
Chia-Jen Tsai, Hsinchu TW
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20140368561 | Method For Modulating A Micro-Led Display - A micro-LED display device and modulation scheme for applying image data to an imager. The micro-LED display, including a plurality of micro-LED pixels disposed in rows and columns array, may use a modulation scheme. The method includes using row write actions to write data to said rows of micro-LED pixels; and using spacing of row write actions to create grey scale modulation, wherein one spacing between sequential row write actions is at a first distance while another spacing between sequential row write actions is at a second distance greater than said first distance. | 12-18-2014 |
Chia-Jen Wang, Pingtung County TW
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20120019279 | METHOD AND PATTERN CARRIER FOR OPTIMIZING INSPECTION RECIPE OF DEFECT INSPECTION TOOL - A method for optimizing an inspection recipe of a defect inspection tool is described. A substrate having thereon intentional defects and locating patterns beside the intentional defects is provided. The defect inspection tool is used to detect the intentional defects with an inspection recipe and obtain the distribution of undetected or partially detected intentional defects. The locating patterns are utilized to locate the undetected or partially detected intentional defects and thereby determine the type(s) of the undetected or partially detected intentional defects. The inspection recipe is modified according to the type(s) of the undetected or partially detected intentional defects in a manner such that there is a minimal number of undetected or partially detected intentional defects under the inspection of the defect inspection tool. | 01-26-2012 |
Chia-Jen Wen, Taipei TW
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20100178345 | Hydrogel Microparticle Composition, Application Thereof and Method for Preparing the Same - Disclosed herein is a method for preparing a hydrogel microparticle composition. A dispersion including 1 part by weight of N-isopropyl acrylamide, about 0.1-0.5 part by weight of chitosan, about 0-0.05 part by weight of N,N′-methylene bisacrylamide, about 0.1-0.5 part by weight of glacial acetic acid, and about 20-40 parts by weight of water is prepared. About 0.01-0.3 part by weight of an anionic initiator is added into the dispersion and the dispersion is allowed to undergo a polymerization reaction at a temperature of about 10-100° C. for about 1 to 5 hours, thereby producing a plurality of hydrogel microparticles dispersed in the water to form the hydrogel microparticle composition. | 07-15-2010 |
Chia-Jen Wu, Hualien TW
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20150147417 | METHOD AND PHARMACEUTICAL COMPOSITION FOR LIVER FIBROSIS PREVENTION AND/OR TREATMENT - The present invention is related to a method for liver fibrosis prevention and/or treatment and a pharmaceutical composition thereof. The method and the pharmaceutical composition are made by taking the advantage of | 05-28-2015 |
20150182570 | COMPOSITION HAVING A. paniculata FOR WOUND HEALING AND SKIN WHITENING, AND METHOD BY USING THE SAME - The present invention provides a pharmaceutical composition for wound healing and/or skin whitening. The pharmaceutical composition comprises active ingredient of | 07-02-2015 |