Patent application number | Description | Published |
20080295686 | Method and apparatus for removing contaminants from a reflow apparatus - A reflow apparatus for solder joining electronic components to a substrate includes a reflow chamber, a conveyor to convey a substrate within the chamber, at least one heating element to provide heat to reflow solder on the substrate, and at least one system to remove contaminants generated from the reflow solder. The system is coupled with the chamber for passage of a vapor stream from the chamber through the system. The system comprises a contaminant collection unit in fluid communication with the vapor stream. The contaminant collection unit includes a coil and a collection container. The coil is configured to receive cooled gas therein. The arrangement is such that when introducing cooled gas in the coil, contaminants in the vapor stream condense on the coil, and when ceasing the introduction of cooled gas in the coil, contaminants in the vapor stream are released from the coil and collected in the collection container. Other embodiments and methods for removing contaminants are further disclosed. | 12-04-2008 |
20110272451 | METHOD AND APPARATUS FOR REMOVING CONTAMINANTS FROM A REFLOW APPARATUS - A reflow apparatus for solder joining electronic components to a substrate includes a reflow chamber, a conveyor to convey a substrate within the chamber, at least one heating element to provide heat to reflow solder on the substrate, and at least one system to remove contaminants generated from the reflow solder. The system is coupled with the chamber for passage of a vapor stream from the chamber through the system. The system comprises a contaminant collection unit in fluid communication with the vapor stream. The contaminant collection unit includes a coil and a collection container. The coil is configured to receive cooled gas therein. The arrangement is such that when introducing cooled gas in the coil, contaminants in the vapor stream condense on the coil, and when ceasing the introduction of cooled gas in the coil, contaminants in the vapor stream are released from the coil and collected in the collection container. Other embodiments and methods for removing contaminants are further disclosed. | 11-10-2011 |
Patent application number | Description | Published |
20110058641 | FAST DYNAMIC REGISTER - A fast dynamic register circuit including first and second precharge circuits, a keeper circuit and an output circuit. The first and second precharge circuits each precharge a corresponding one of a pair of precharge nodes and cooperate to minimize setup and hold times. If an input data node is low when the clock goes high, the first precharge node remains high causing the second precharge node to be discharged. Otherwise if the input node is high, the first precharge node is discharged and the second remains charged. Once either precharge node is discharged, the output state of the register remains fixed until the next rising clock edge independent of changes of the input data node. The fast dynamic register may be implemented with multiple inputs to perform common logic operations, such as OR, NOR, AND and NAND logic operations. | 03-10-2011 |
20140320164 | FAST DYNAMIC REGISTER WITH TRANSPARENT LATCH - A fast dynamic register including a data block, a precharge circuit, a transparent latch, and an output logic gate. The precharge circuit precharges first and second precharge nodes and then releases the first precharge node in response to a clock. The data block evaluates data by either pulling the first precharge node low in response to the clock or does not pull it low, in which case the second precharge node is discharged. The transparent latch passes a state of the second precharge node to a store node when transparent, and otherwise latches the store node. The output logic gate drives an output node to a state based on states of the second precharge node and the store node. The transparent latch may be implemented with relatively small devices to reduce size and power consumption to improve efficiency. | 10-30-2014 |
20140320188 | SCANNABLE FAST DYNAMIC REGISTER - A scannable fast dynamic register including a data and scan enable circuit, a precharge circuit, a select circuit, a store circuit, and a scan input enable circuit. The data and scan enable circuit pulls a first precharge node to a discharge node in response to the clock upon evaluation in normal mode. The precharge circuit precharges first and second precharge nodes high, in which one of the precharged nodes discharges depending upon whether a data block evaluates. The store circuit and an output gate are responsive to the second precharge node to provide the output. The select circuit is interposed before the store circuit to allow injection of scan data in a scan mode. In scan mode, the scan input enable circuit provides scan data to the select and store circuits. The scan input enable circuit also includes a store circuit which operates with the first store circuit in a master-slave configuration. | 10-30-2014 |
Patent application number | Description | Published |
20090127742 | Process For Activating A Web - A process for simultaneously activating two or more portions of a web in different directions. The process involves feeding a web into an apparatus that includes a pair of intermeshing activation rolls having three dimensional surface features configured to simultaneously activate different portions a web in different directions. The three dimensional surface features are arranged in discrete regions on the rolls such that at least two of the regions provide different directions of activation. The rolls include one or more buffer regions positioned between the discrete regions on the roll that provide different directions of activation. | 05-21-2009 |
20090130242 | Apparatus For Activating A Web - An apparatus for simultaneously activating two or more portions of a web in different directions. The apparatus includes a pair of intermeshing activation rolls with three-dimensional surface features disposed thereon. The three dimensional surface features are arranged in discrete regions on the rolls such that at least two of the regions provide different directions of activation. The rolls include one or more buffer regions positioned between the discrete regions on the roll that provide different directions of activation. | 05-21-2009 |
20090131901 | Outer Cover For A Disposable Absorbent Article - An outer cover for a disposable absorbent article. The outer cover includes an elastic material joined to an extensible material to form a laminate. At least two different areas of the laminate are simultaneously activated in different directions by a single pair of intermeshing activation rolls. At least a portion of the two different areas of activation on the outer cover are spatially separated by a buffer zone. | 05-21-2009 |
20100228212 | Outer Cover for a Disposable Absorbent Article - An outer cover for a disposable absorbent article including waist regions elastically stretchable in the cross machine direction and activated in the cross machine direction, activated leg cuff regions elastically stretchable in one or more directions other than the cross machine direction, and an inelastic crotch region having a nonwoven crotch patch for providing the outer cover with suitable tensile strength, opacity, and poke-through properties. | 09-09-2010 |
20110024940 | Method For Making An Elastomeric Apertured Web - A method for making an elastomeric apertured web comprises providing a precursor web comprising a laminate which is subjected to incremental stretching to form an elastomeric precursor web. A forming apparatus is provided comprising a first member and a second member, wherein the first member comprises a mating member, and the second member comprises teeth which are joined to the second member. The elastomeric precursor web is moved through the forming apparatus, wherein apertures are formed in the elastomeric precursor web material as the teeth on the second member penetrate the mating member forming an elastomeric apertured web. The elastomeric apertured web exhibits a WVTR of at least about 1000 g/m | 02-03-2011 |
20110031649 | Process for Activating A Web - A process for simultaneously activating two or more portions of a web in different directions. The process involves feeding a web into an apparatus that includes a pair of intermeshing activation rolls having three dimensional surface features configured to simultaneously activate different portions a web in different directions. The three dimensional surface features are arranged in discrete regions on the rolls such that at least two of the regions provide different directions of activation. The rolls include one or more buffer regions positioned between the discrete regions on the roll that provide different directions of activation. | 02-10-2011 |
20110117235 | Apparatus For Activating A Web - An apparatus for simultaneously activating two or more portions of a web in different directions. The apparatus includes a pair of intermeshing activation rolls with three-dimensional surface features disposed thereon. The three dimensional surface features are arranged in discrete regions on the rolls such that at least two of the regions provide different directions of activation. The rolls include one or more buffer regions positioned between the discrete regions on the roll that provide different directions of activation. | 05-19-2011 |
20110208486 | COMPUTER BASED MODELING OF FIBROUS MATERIALS - Computer based models of fibrous materials. | 08-25-2011 |
20110208487 | COMPUTER BASED MODELING OF PROCESSED FIBROUS MATERIALS - Computer based models of processed fibrous materials. | 08-25-2011 |
20110250413 | BOND PATTERNS FOR FIBROUS WEBS - Bond patterns for fibrous webs. | 10-13-2011 |
20120032370 | Process For Activating A Web - A process for simultaneously activating two or more portions of a web in different directions. The process involves feeding a web into an apparatus that includes a pair of intermeshing activation rolls having three dimensional surface features configured to simultaneously activate different portions a web in different directions. The three dimensional surface features are arranged in discrete regions on the rolls such that at least two of the regions provide different directions of activation. The rolls include one or more buffer regions positioned between the discrete regions on the roll that provide different directions of activation. | 02-09-2012 |
20130123734 | Outer Cover for a Disposable Absorbent Article - An outer cover for a disposable absorbent article. The outer cover includes an elastic material joined to an extensible material to form a laminate. At least two different areas of the laminate are simultaneously activated in different directions by a single pair of intermeshing activation rolls. At least a portion of the two different areas of activation on the outer cover are spatially separated by a buffer zone. | 05-16-2013 |
Patent application number | Description | Published |
20130183231 | INTRODUCTION OF MESOPOROSITY INTO ZEOLITE MATERIALS WITH SEQUENTIAL ACID, SURFACTANT, AND BASE TREATMENT - Compositions and methods for introducing mesoporosity into zeolitic materials employing sequential acid, surfactant, and base treatments are disclosed herein. Mesopores can be introduced into zeolitic materials, such as zeolites, by treatment with an acid and surfactant followed by treatment with a base. The resulting mesoporous zeolitic materials can have a total 20 to 135 Å diameter mesopore volume of at least 0.05 cc/g. Additionally, the resulting mesoporous zeolitic materials can have a total 0 to 20 Å micropore volume of at least 0.10 cc/g. | 07-18-2013 |
20150182953 | INTRODUCING MESOPOROSITY INTO ZEOLITE MATERIALS WITH A MODIFIED ACID PRE-TREATMENT STEP - Methods for introducing mesoporosity into zeolite materials that employ an acid pretreatment step are provided. By utilizing a non-acidic chelating agent during the acid treatment step, the zeolite material can be pretreated with a strong acid, often in higher concentrations or over shorter contact times, than had previously been contemplated. The resulting acid-treated mesoporous materials retain desirable properties, including Si/Al, UCS, and total mesopore and micropore volume. The ability to use a stronger acid without damaging the zeolite material results in a less expensive process capable of producing mesoporous zeolite materials suitable for a wide range of uses. | 07-02-2015 |
Patent application number | Description | Published |
20100030970 | Adaptive Spill-Receive Mechanism for Lateral Caches - Improving cache performance in a data processing system is provided. A cache controller monitors a counter associated with a cache. The cache controller determines whether the counter indicates that a plurality of non-dedicated cache sets within the cache should operate as spill cache sets or receive cache sets. The cache controller sets the plurality of non-dedicated cache sets to spill an evicted cache line to an associated cache set in another cache in the event of a cache miss in response to an indication that the plurality of non-dedicated cache sets should operate as the spill cache sets. The cache controller sets the plurality of non-dedicated cache sets to receive an evicted cache line from another cache set in the event of the cache miss in response to an indication that the plurality of non-dedicated cache sets should operate as the receive cache sets. | 02-04-2010 |
20110078382 | Adaptive Linesize in a Cache - A mechanism is provided in a cache for emulating larger linesize in a substrate with smaller linesize using gang fetching and gang replacement. Gang fetching fetches multiple lines on a cache miss to ensure that all smaller lines that make up the larger line are resident in cache at the same time. Gang replacement evicts all smaller lines in cache that would have been evicted had the cache linesize been larger. The mechanism provides adaptive linesize using set dueling by dynamically selecting between multiple linsizes depending on which linesize performs the best at runtime. Set dueling dedicates a portion of sets of the cache to always use smaller linesize and dedicates one or more portions of the sets of cache to always emulate larger linesizes. One or more counters keep track of which linesize has the best performance. The cache uses that linesize for the remainder of the sets. | 03-31-2011 |
20110078412 | Processor Core Stacking for Efficient Collaboration - A mechanism is provided for improving the performance and efficiency of multi-core processors. A system controller in a data processing system determines an operational function for each primary processor core in a set of primary processor cores in a primary processor core logic layer and for each secondary processor core in a set of secondary processor cores in a secondary processor core logic layer, thereby forming a set of determined operational functions. The system controller then generates an initial configuration, based on the set of determined operational functions, for initializing the set of primary processor cores and the set of secondary processor cores in the three-dimensional processor core architecture. The initial configuration indicates how at least one primary processor core of the set of primary processor cores collaborate with at least one secondary processor core of the set of secondary processor cores. | 03-31-2011 |
20120030481 | Measuring Data Switching Activity in a Microprocessor - A mechanism is provided for approximating data switching activity in a data processing system. A data switching activity identification mechanism in the data processing system receives an identification of a set of data storage devices and a set of bits in the set of data storage devices in the data processing system to be monitored for the data switching activity. The data switching activity identification mechanism sums a count of the identified bits that have changed state for the data storage device along with other counts of the identified bits that have changed state for other data storage devices in the set of data storage devices to form an approximation of data switching activity. A power manager in the data processing system then adjusts a set of operational parameters associated with the data processing system using the approximation of data switching activity. | 02-02-2012 |
20120131304 | Adaptive Wear Leveling via Monitoring the Properties of Memory Reference Stream - Adaptive write leveling in limited lifetime memory devices including performing a method for monitoring a write data stream that includes write line addresses. A property of the write data stream is detected and a write leveling process is adapted in response to the detected property. The write leveling process is applied to the write data stream to generate physical addresses from the write line addresses. | 05-24-2012 |
20120311262 | MEMORY CELL PRESETTING FOR IMPROVED MEMORY PERFORMANCE - Memory cell presetting for improved performance including a system that includes a memory, a cache, and a memory controller. The memory includes memory lines made up of memory cells. The cache includes cache lines that correspond to a subset of the memory lines. The memory controller is in communication with the memory and the cache. The memory controller is configured to perform a method that includes scheduling a request to set memory cells of a memory line to a common specified state in response to a cache line attaining a dirty state. | 12-06-2012 |
20130013860 | MEMORY CELL PRESETTING FOR IMPROVED MEMORY PERFORMANCE - Memory cell presetting for improved performance including a method for using a computer system to identify a region in a memory. The region includes a plurality of memory cells characterized by a write performance characteristic that has a first expected value when a write operation changes a current state of the memory cells to a desired state of the memory cells and a second expected value when the write operation changes a specified state of the memory cells to the desired state of the memory cells. The second expected value is closer than the first expected value to a desired value of the write performance characteristic. The plurality of memory cells in the region are set to the specified state, and the data is written into the plurality of memory cells responsive to the setting. | 01-10-2013 |
20130013886 | ADAPTIVE WEAR LEVELING VIA MONITORING THE PROPERTIES OF MEMORY REFERENCE STREAM - Adaptive write leveling in limited lifetime memory devices including performing a method for monitoring a write data stream that includes write line addresses. A property of the write data stream is detected and a write leveling process is adapted in response to the detected property. The write leveling process is applied to the write data stream to generate physical addresses from the write line addresses. | 01-10-2013 |
20130339570 | VARIABILITY AWARE WEAR LEVELING - Techniques are presented that include determining, for data to be written to a nonvolatile memory, a location in the nonvolatile memory to which the data should be written based at least on one or more wear metrics corresponding to the location. The one or more wear metrics are based on measurements of the location. The measurements estimate physical wear of the location. The techniques further include writing the data to the determined location in the nonvolatile memory. The techniques may be performed by methods, apparatus (e.g., a memory controller), and computer program products. | 12-19-2013 |
20130339574 | VARIABILITY AWARE WEAR LEVELING - Techniques are presented that include determining, for data to be written to a nonvolatile memory, a location in the nonvolatile memory to which the data should be written based at least on one or more wear metrics corresponding to the location. The one or more wear metrics are based on measurements of the location. The measurements estimate physical wear of the location. The techniques further include writing the data to the determined location in the nonvolatile memory. The techniques may be performed by methods, apparatus (e.g., a memory controller), and computer program products. | 12-19-2013 |
20130339762 | ADAPTIVE WORKLOAD BASED OPTIMIZATIONS TO MITIGATE CURRENT DELIVERY LIMITATIONS IN INTEGRATED CIRCUITS - A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack. | 12-19-2013 |
20140082574 | Token-Based Current Control to Mitigate Current Delivery Limitations in Integrated Circuits - A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack. | 03-20-2014 |
20140082580 | CURRENT-AWARE FLOORPLANNING TO OVERCOME CURRENT DELIVERY LIMITATIONS IN INTEGRATED CIRCUITS - A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack. | 03-20-2014 |
20140195996 | ADAPTIVE WORKLOAD BASED OPTIMIZATIONS COUPLED WITH A HETEROGENEOUS CURRENT-AWARE BASELINE DESIGN TO MITIGATE CURRENT DELIVERY LIMITATIONS IN INTEGRATED CIRCUITS - A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack. | 07-10-2014 |
20150309941 | OUT-OF-PLACE PRESETTING BASED ON INDIRECTION TABLE - An aspect of this invention is a method for providing a PreSET region in a memory device wherein the PreSET region includes one or more lines of the memory device which have been PreSET; performing a write operation on one or more out of place lines of the memory device by writing to the PreSET region instead of writing to an in place line of the memory device; and storing in an indirection table a mapping of each of a respective plurality of logical pages of the memory device to a corresponding physical page of a plurality of physical pages of the memory device, wherein the indirection table keeps track of the one or more out of place lines. | 10-29-2015 |
Patent application number | Description | Published |
20130297879 | PROBABILISTIC ASSOCIATIVE CACHE - A computer cache memory organization called Probabilistic Set Associative Cache (PAC) has the hardware complexity and latency of a direct-mapped cache but functions as a set-associative cache for a fraction of the time, thus yielding better than direct mapped cache hit rates. The organization is considered a (1+P)—way set associative cache, where the chosen parameter called | 11-07-2013 |
20140043927 | METHOD FOR OPTIMIZING REFRESH RATE FOR DRAM - A method for determining an optimized refresh rate involves testing a refresh rate on rows of cells, determining an error rate of the rows, evaluating the error rate of the rows; and repeating these steps for a decreased refresh rate until the error rate is greater than a constraint, at which point a slow refresh rate is set. | 02-13-2014 |
20140063997 | DRAM REFRESH - A refresh of a DRAM having at least a fast and a slow refresh rate includes encoding a pointer on a row or rows with refresh information, reading the refresh information, and incrementing a fast refresh address counter with the refresh information. The refresh may be performed by encoding one or more cells on a row that may require a fast refresh, one or more cells on a group of rows that may require a fast refresh, or one or more cells on a row that may not require a fast refresh. | 03-06-2014 |
20140164692 | MANAGING ERRORS IN A DRAM BY WEAK CELL ENCODING - This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data. | 06-12-2014 |
20140164820 | MANAGING ERRORS IN A DRAM BY WEAK CELL ENCODING - This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data. | 06-12-2014 |
20140164871 | DRAM ERROR DETECTION, EVALUATION, AND CORRECTION - This disclosure includes a method for correcting errors on a DRAM having an ECC which includes writing data to a DRAM row, reading data from the DRAM row, detecting errors in the data that cannot be corrected by the DRAM's ECC, determining erasure information for the row, evaluating the errors using the erasure information, and correcting the errors in the data. | 06-12-2014 |
20140164874 | DRAM ERROR DETECTION, EVALUATION, AND CORRECTION - This disclosure includes a method for correcting errors on a DRAM having an ECC which includes writing data to a DRAM row, reading data from the DRAM row, detecting errors in the data that cannot be corrected by the DRAM's ECC, determining erasure information for the row, evaluating the errors using the erasure information, and correcting the errors in the data. | 06-12-2014 |
Patent application number | Description | Published |
20090016140 | DYNAMIC VOLTAGE ADJUSTMENT FOR MEMORY - A power supply voltage for a memory on an integrated circuit is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply voltage. A test memory of the integrated circuit is concurrently powered while operating the memory. The test memory and the memory each include bit cells of a first bit cell configuration type. A voltage level of the supply voltage is adjusted, while operating the memory, based on the testing of the test memory. The voltage level is adjusted with external variations to assume a value that guarantees no failed operation of the memory but also accurately minimizes the supply voltage. The system and method may be implemented with any type of memory. The memory and test memory may be physically implemented either separated or interspersed on the integrated circuit. | 01-15-2009 |
20140129883 | HARDWARE-BASED MEMORY INITIALIZATION - Systems and methods for hardware-based initialization of memory circuitry. In some embodiments, a method may include, after completion and/or independently of an integrity test of a memory circuit, generating a sequence of random logic values using a Built-In-Self-Test (BIST) circuit. The method may further include initializing the memory circuit with the sequence of random logic values using the BIST circuit. In some implementations, the sequence of logic values may be generated using memory circuit identification, chip identification, and/or clock information as a seed state. | 05-08-2014 |
20150162098 | MEMORIES HAVING A BUILT-IN SELF-TEST (BIST) FEATURE - A memory system includes a memory and a built-in self-test (BIST) unit coupled to the memory. The BIST unit is configured to run a test pattern on the memory to accumulate a fault signature, and store fault signature information based on the accumulated fault signature at multiple locations in the memory. | 06-11-2015 |
Patent application number | Description | Published |
20100138501 | END-TO-END VALIDATION IN A PUSH ENVIRONMENT - In a push environment having a communication path along which a service provides messages to a computing device via a gateway, an inactivity timeout value and a registration timeout value enable the computing device to detect failures in the communication path. An application executing on the computing device registers an application endpoint with the gateway. The application separately subscribes to the service to receive the messages. If there is inactivity in accordance with the inactivity timeout value, the application de-registers and re-registers with the gateway, and unsubscribes and re-subscribes with the service. | 06-03-2010 |
20110145063 | TARGETING APPLICATIONS WITH ADVERTISEMENTS - Collecting application execution data by a push service and targeting application programs with advertisements based on the collected data. Statistics such as activity, popularity, and frequency of execution for each of the application programs are generated based on the collected data. The statistics are matched to advertising campaigns to select application programs relevant to the advertising campaigns. Advertisers are charged for delivering the advertisements based on the selected application programs. For example, advertisements delivered to frequently executed application programs are more expensive than advertisements delivered to application programs that are rarely executed. | 06-16-2011 |
20110173681 | FLEXIBLE AUTHENTICATION AND AUTHORIZATION MECHANISM - Techniques and tools for flexible authentication and authorization of services on a push framework. For example, a push notification framework allows services (social networking web services, etc.) to use either an authenticated access mode or an unauthenticated access mode, in order to push information to client devices (e.g., mobile devices). In the authenticated mode, the push framework requires registration of the service with the push framework before allowing the service to push notifications to client devices. Different authenticated modes are provided for third-party and first-party services. In the unauthenticated mode, registration is not required, but notifications are throttled, thereby limiting risk of abuse by unauthenticated services. This allows flexibility for services that use the push framework. | 07-14-2011 |
20120198268 | RE-ESTABLISHING PUSH NOTIFICATION CHANNELS VIA USER IDENTIFIERS - Embodiments enable recovery of push notification channels via session information associated with user identifiers. A proxy service creates session information describing push notification channels (e.g., subscriptions) for a user and associates the session information with a user identifier. The session information is stored in a cloud service or other storage area separate from the proxy service. After failure of a user computing device or the proxy service, the session information is obtained via the user identifiers and the push notification channels are re-created with the session information. In some embodiments, the proxy service enables delivery of the same notification to multiple computing devices associated with the user identifier. | 08-02-2012 |
20130151719 | DETERMINING AN EFFICIENT KEEP-ALIVE INTERVAL FOR A NETWORK CONNECTION - Systems and methods for use in communication between a client and a server, via a networking device, are provided. The method may include sending a request to establish a data connection from the client to the server via the networking device, setting a data connection keep-alive interval for the data connection to a predetermined safe value, and sending a request to establish a test connection between the client and the server. The method may further include determining an efficient keep-alive interval for communication between the client and server via the networking device, using the test connection, setting the data connection keep-alive interval to the efficient keep-alive interval determined using the test connection, and uploading the efficient keep-alive interval from the client to the server in an efficient keep-alive interval notification message, for communication to other clients connected to the server. | 06-13-2013 |
Patent application number | Description | Published |
20080293911 | ANHYDRIDE AND RESORCINOL LATENT CATALYST SYSTEM FOR IMPROVING CURE CHARACTERISTICS OF PHENOLIC RESINS - An anhydride and resorcinol latent catalyst system for a phenolic resole resin provides a resin having long pot life and long shelf life, yet cures quickly thereafter. | 11-27-2008 |
20130209348 | PREPARATION OF POLYMERIC RESINS AND CARBON MATERIALS - The present application is directed to methods for preparation of polymer particles in gel form and carbon materials made therefrom. The carbon materials can have enhanced electrochemical properties and find utility in any number of electrical devices, for example, as electrode material in ultracapacitors or batteries. | 08-15-2013 |
20140148560 | PREPARATION OF PHENOL-FORMALDEHYDE RESIN BEADS USING SUSPENSION OR EMULSION POLYMERIZATION - Methods for making polymer particles in gel form via an emulsion and/or suspension polymerization are provided. In at least one specific embodiment, the method can include reacting a first reaction mixture comprising a phenolic monomer, an aldehyde monomer, and a first catalyst to produce a prepolymer. The method can also include combining the prepolymer with a carrier fluid and a second catalyst to produce a second reaction mixture. The second catalyst can include a dicarboxylic acid, an anhydride, a dihydroxybenzene, or any mixture thereof. The method can also include polymerizing the prepolymer to form polymer particles in gel form. | 05-29-2014 |
20150087731 | METHODS FOR MAKING WET GELS AND DRIED GELS THEREFROM - Methods for making wet gels and dried gels therefrom are provided. The method for making a wet gel can include combining a hydroxybenzene compound, an aldehyde compound, and an additive to produce a reaction mixture. The additive can include a carboxylic acid, an anhydride, a homopolymer, a copolymer, or any mixture thereof. At least the hydroxybenzene compound and the aldehyde compound can be reacted to produce a wet gel. The reaction mixture can include about 10 wt % to about 65 wt % of the hydroxybenzene compound, about 5 wt % to about 25 wt % of the aldehyde compound, up to about 85 wt % of the carboxylic acid, up to about 40 wt % of the anhydride, up to about 40 wt % of the homopolymer, and up to about 40 wt % of the copolymer, where weight percent values are based on the combined weight of the hydroxybenzene compound, the aldehyde compound, and the additive. | 03-26-2015 |
20150321920 | PREPARATION OF POLYMERIC RESINS AND CARBON MATERIALS - Methods for making carbon materials are provided. In at least one specific embodiment, the method can include combining one or more polymer precursors with one or more liquids to produce a mixture. The mixture can be an emulsion, dispersion, or a suspension. The liquid can include hexane, pentane, cyclopentane, benzene, toluene, o-xylene, m-xylene, p-xylene, diethyl ether, ethylmethylketone, dichloromethane, tetrahydrofuran, mineral oils, paraffin oils, vegetable derived oils, or any mixture thereof. The method can also include aging the mixture at a temperature and time sufficient for the polymer precursor to react and form polymer gel particles having a volume average particle size (Dv,50) of the polymer particles in gel form greater than or equal to 1 mm. The method can also include heating the polymer gel particles to produce a carbon material. | 11-12-2015 |
20160039970 | IMPROVED EMULSION AND SUSPENSION POLYMERIZATION PROCESSES, AND IMPROVED ELECTROCHEMICAL PERFORMANCE FOR CARBON DERIVED FROM SAME - The present application is directed to methods for preparation of polymer particles in gel form and carbon materials made therefrom. The carbon materials comprise enhanced electrochemical properties and find utility in any number of electrical devices, for example, as electrode material in ultracapacitors or batteries. The methods herein can also be employed generally to improve emulsion and/or suspension polymerization processes by improved control of diffusion of acidic and basic species between the polymer and secondary phases. | 02-11-2016 |