Kono, Yokohama
Fumihiro Kono, Yokohama JP
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20100027357 | Memory System Having Distributed Read Access Delays - A system having a plurality of memory cells organized in rows and columns. Each column includes upper and lower sets of memory cells connected to corresponding common upper/lower bit lines. Each column includes an evaluation circuit coupled to the upper and lower bit lines and configured to evaluate signals on these bit lines and to produce an output signal. Each of the upper and lower bit lines has an associated bit line delay, one of which is greater than the other. The evaluation circuit has first and second inputs which have associated evaluation delays, one of which is greater than the other. In each column, the bit line having the greater bit line delay is connected to the evaluation circuit input having the smaller evaluation delay, and the bit line having the smaller bit line delay is connected to the evaluation circuit input having the greater evaluation delay. | 02-04-2010 |
20100079164 | Systems and Methods for Improving the PN Ratio of a Logic Gate by Adding a Non-Switching Transistor - Systems and methods for improving a PN ratio of a logic gate by adding a non-switching transistor. In one embodiment, the logic gate includes a plurality of PMOS switching transistors and a plurality of NMOS switching transistors that are switched on and off by received input signals. The PMOS and NMOS switching transistors are interconnected to perform a logic operation on the input signals and produce a corresponding output signal. The non-switching transistor is inserted in the circuit to improve the ratio of PMOS and NMOS transistors between the power nodes of the logic gate. The non-switching transistor is either a PMOS transistor or an NMOS transistor as needed to make the PN ratio closer to 1. The non-switching transistor is biased to keep it switched on and does not affect the logic functions of the gate. | 04-01-2010 |
20100277965 | Memory System Having Multiple Vias at Junctions Between Traces - An improvement to a memory system having a hierarchical bitline structure wherein traces that form global write lines are connected to each other using junctions that include multiple vias to reduce capacitance and increase yield. At least one of a pair of traces connected by the vias includes a widened portion that provides sufficient overlap with the other trace to allow the two or more vias to be formed between the traces at the overlap. Parallel traces for global write lines that carry a write signal and its inverse may be positioned more than one maximum-density grid space apart to allow the widened portions to be formed between the traces. A global read line that is formed in a different metal layer from the global write line traces may be positioned in a grid space between the global write line traces to reduce the capacitance of this line. | 11-04-2010 |
20100302896 | Systems and methods for Stretching Clock Cycles in the Internal Clock Signal of a Memory Array Macro - Systems and methods for stretching clock cycles of the internal clock signal of a memory array macro to allow more time for a data access in the macro than the period of an external clock signal. In one embodiment, a local clock buffer in the memory array macro receives a regular periodic external clock signal and generates an internal clock signal. The local clock buffer includes a first signal path that has one or more faster-than-nominal components so that the first rising edge of the internal clock cycle occurs early than it would in a clock buffer with nominal components. When the memory array macro is active for a data access, the local clock buffer stretches a clock cycle of the internal clock signal so that the first and second half-periods of the internal clock cycle are each greater than the half-periods of the external clock signal. | 12-02-2010 |
20100313174 | Systems and Methods for Improving the PN Ratio of a Logic Gate by Adding a Non-Switching Transistor - Systems and methods for improving a PN ratio of a logic gate by adding a non-switching transistor. In one embodiment, the logic gate includes a plurality of PMOS switching transistors and a plurality of NMOS switching transistors that are switched on and off by received input signals. The PMOS and NMOS switching transistors are interconnected to perform a logic operation on the input signals and produce a corresponding output signal. The non-switching transistor is inserted in the circuit to improve the ratio of PMOS and NMOS transistors between the power nodes of the logic gate. The non-switching transistor is either a PMOS transistor or an NMOS transistor as needed to make the PN ratio closer to 1. The non-switching transistor is biased to keep it switched on and does not affect the logic functions of the gate. | 12-09-2010 |
Masashi Kono, Yokohama JP
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20130064115 | MULTIPLEXING TRANSMISSION SYSTEM, RECEIVER APPARATUS AND MODULE, TRANSMITTER APPARATUS FOR MULTIPLEXING TRANSMISSION - Digital signals having respective pieces of frequency information different from each other are bundled, and transmitted at high speed. On receiving side, digital signals retaining the respective pieces of frequency information are recovered and separated. Transmitter apparatus divides pieces of transmission data that have the different pieces of frequency information and correspond to respective input channels into data blocks having a fixed length, as valid data, and subsequently multiplexes the data blocks corresponding to the respective input channels and outputs the multiplexed data to a transmission path. A receiver apparatus divides data string received into data flows and subsequently restores the transmission data, from the data blocks consecutive in each data flow and stores the restored data, and outputs transmission data corresponding to the respective data flows in synchronization with clocks generated for these data flows. | 03-14-2013 |
Michimune Kono, Yokohama JP
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20090249426 | SUPPLEMENTING BROADCAST SERVICE WITH NETWORK CONTENT - A broadcast interactive television service provides broadcast content received through a broadcast and supplemental content retrieved over a network. The broadcast content may include a broadcast markup language (BML) file which is parsed to provide an interface to the user. If the BML file contains information regarding the location or other information for supplemental content, the supplemental content can be retrieved from over a network and provide through the interface. Once presentation of the supplemental content has completed, the state of the interface may return to that associated with the BML file. | 10-01-2009 |
20100146544 | CONCURRENT INTERACTIVE TELEVISION FOR NETWORK CONNECTED DEVICES - Techniques are disclosed herein for processing iTV. A request to play a first interactive television signal at a first electronic device is received. A first virtual machine for processing the first interactive television signal is instantiated at the first electronic device. A first file that includes information associated with playing interactive TV on the first electronic device is accessed from non-volatile storage on the first electronic device. A request to play a second interactive television signal at a second electronic device that is communicatively coupled to the first electronic device is received. A second virtual machine for processing the second interactive television signal is instantiated at the first device. A second file that includes information associated with playing interactive TV on the second electronic device is stored in non-volatile storage on the first electronic device. | 06-10-2010 |
Misako Kono, Yokohama JP
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20110202735 | COMPUTER SYSTEM, AND BACKUP METHOD AND PROGRAM FOR COMPUTER SYSTEM - A backup is completed within a backup window designated by a user. | 08-18-2011 |
20110314239 | COMPUTER SYSTEM AND SYSTEM CONTROL METHOD - Operation of an environment that supports both host-based replication and array-based replication is realized. According to the present invention, data in the first storage area is copied first to the second storage area using an array-based replication engine. In this case, the execution result of the replication is managed using a flag from which the copy timing can be known. In addition, data in the first storage area is copied to the third storage area using a host-based replication engine, and further, data in the third storage area is copied to the fourth storage area. Then, when data in the second storage area is restored to the first storage area, data in the fourth storage area is returned to the third storage area so that the third storage area has data of the same time as the second storage area (see FIG. | 12-22-2011 |
20120331248 | STORAGE MANAGEMENT SYSTEM AND STORAGE MANAGEMENT METHOD - An embodiment of this invention is a storage management system including a processor and a storage device to manage a storage system having one or more copy functions. The processor locates data designated to determine a backup method. The storage device stores copy function management information on the one or more copy functions of the storage system. The processor refers to the copy function management information to ascertain the unit of copy operation of each of the one or more copy functions. The processor determines a candidate for a copy function of the storage system to be used to back up the designated data depending on the data configuration in a volume holding the designated data and the unit of copy operation of the candidate for the copy function. | 12-27-2012 |
20150032983 | STORAGE MANAGEMENT SYSTEM AND STORAGE MANAGEMENT METHOD - An embodiment of this invention is a storage management system including a processor and a storage device to manage a storage system having one or more copy functions. The processor locates data designated to determine a backup method. The storage device stores copy function management information on the one or more copy functions of the storage system. The processor refers to the copy function management information to ascertain the unit of copy operation of each of the one or more copy functions. The processor determines a candidate for a copy function of the storage system to be used to back up the designated data depending on the data configuration in a volume holding the designated data and the unit of copy operation of the candidate for the copy function. | 01-29-2015 |
20150186223 | STORAGE MANAGEMENT SYSTEM AND STORAGE MANAGEMENT METHOD - An embodiment of this invention is a storage management system including a processor and a storage device to manage a storage system having one or more copy functions. The processor locates data designated to determine a backup method. The storage device stores copy function management information on the one or more copy functions of the storage system. The processor refers to the copy function management information to ascertain the unit of copy operation of each of the one or more copy functions. The processor determines a candidate for a copy function of the storage system to be used to back up the designated data depending on the data configuration in a volume holding the designated data and the unit of copy operation of the candidate for the copy function. | 07-02-2015 |
Mitsunori Kono, Yokohama JP
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20140206680 | SUBSTITUTED 6-AZA-ISOINDOLIN-1-ONE DERIVATIVES - Disclosed are compounds of Formula 1, and pharmaceutically acceptable salts thereof, wherein G, p, R | 07-24-2014 |
Tomohiko Kono, Yokohama JP
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20090304008 | NETWORK RELAY DEVICE AND NETWORK RELAY METHOD - A network relay device for relaying communication for a regular terminal via a port includes an acquiring module, a regular terminal information storing module, and a determination process module. The acquiring module acquires a regular layer 2 address, a regular layer 3 address, regular VLAN information representing a VLAN assigned to the regular terminal, and regular port information representing a port to which the regular terminal is connected. The regular terminal information storing module stores regular terminal information representing a combination of the acquired regular layer 2 address, the regular layer 3 address, the regular VLAN information, and the regular port information. The determination process module determines whether the combination of source layer 2 address, source layer 3 address, assigned VLAN, and reception port of target frame data received via the port is stored as the regular terminal information. | 12-10-2009 |
Tsutomu Kono, Yokohama JP
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20100209041 | PHOTOELECTRIC COMPOSITE WIRING MODULE AND METHOD FOR MANUFACTURING THE SAME - A photoelectric composite wiring module includes a circuit substrate, an optical device, an LSI having a driver and an amplifier for the optical device, and a thin film wiring layer having an electrical wiring. The optical device is connected with the LSI by means of the electrical wiring. The optical device is formed on the circuit substrate and optically coupled to an optical waveguide formed in the circuit substrate. The thin film wiring layer is formed on the optical device to ensure that the optical device is electrically connected with the electrical wiring of the thin film wiring layer. The LSI is mounted on and electrically connected with the thin film wiring layer. | 08-19-2010 |
20120128292 | Photoelectric Composite Wiring Module and Method for Manufacturing Same - A photoelectric composite wiring module, being superior in performances and mass-productivity thereof, and a transmission apparatus of applying that therein are provided. | 05-24-2012 |
Yosuke Kono, Yokohama JP
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20160137161 | Seatbelt Through-Anchor And Seatbelt Device - The present invention provides a seatbelt through-anchor and device capable of preventing jamming during an emergency. A through-anchor is rotatably attached to a vehicle interior wall and is folded back after a webbing extracted from a retractor is inserted through the through-anchor. The through-anchor includes: an insertion hole including an approximately linear lower edge on which the webbing slides, and a lateral edge curving from an end part of the lower edge; a lower-side part provided below the lower edge; and a bump part extending from an end of the lower-side part, protruding beyond a surface of the lower-side part in a direction corresponding to a vehicle interior side. The bump part includes peak parts protruding the furthest in the course of separating from the lateral edge, and includes, between each of the peak parts and the lateral edge, a first sliding surface including a curved surface outwardly protruding from the through-anchor. | 05-19-2016 |