Rana, IN
Abhimanyu Singh Rana, Pune IN
Patent application number | Description | Published |
---|---|---|
20140287534 | HIGHLY SENSITIVE MAGNETIC TUNABLE HETEROJUNCTION DEVICE FOR RESISTIVE SWITCHING - The present invention discloses highly sensitive magnetic heterojunction device consisting of a composite comprising ferromagnetic (La | 09-25-2014 |
Ajay Rana, Himachal Pradesh IN
Patent application number | Description | Published |
---|---|---|
20150051422 | SOLVENT FREE PROCESS FOR PURIFICATION OF FREE BIO-AMINO ACIDS - The present invention relates to a green process for purification of free bio amino acids from plant parts, particularly tea leaves and shoots. The invention more particularly relates to an organic solvent free, fast and economical process for purification of natural amino acids on large scale without using any chemical, acid or alkali substance. The invention also relates to a process for purification of bio amino acids from plant and plant parts (renewable bioresources) which are rich in free amino acids. | 02-19-2015 |
Amar Kishorbhai Rana, Baroda IN
Patent application number | Description | Published |
---|---|---|
20160081972 | PARENTERAL DOSAGE FORM OF AMIODARONE - The present invention relates to a stable, sterile, ready to administer parenteral dosage form of amiodarone or its pharmaceutically acceptable salt. Particularly, the present invention provides a stable, sterile, ready to administer parenteral dosage form of amiodarone comprising an aqueous solution comprising amiodarone or its pharmaceutically acceptable salt, an acid, and a polyol, wherein the pH of the solution is in the range of about 2.0 to 4.0, wherein the solution is filled in a plastic container and wherein the solution is free of a solubilizer. | 03-24-2016 |
Devpal Singh Rana, Bulandshahr IN
Patent application number | Description | Published |
---|---|---|
20150210937 | METHOD FOR REMOVING CHLORIDES FROM HYDROCARBON STREAM BY STEAM STRIPPING - A method for removing chloride impurities from a heavy hydrocarbon stream is disclosed. The heavy hydrocarbon stream is contacted with a stripping medium at a temperature ranging between 100-450° C. and at a pressure ranging between 0.1-2 bar with ratio of the heavy hydrocarbon stream to the stripping medium ranging between 1-30; wherein the temperature is maintained below the initial boiling point of the hydrocarbon stream. | 07-30-2015 |
Dharmesh Rana, Nadiad IN
Patent application number | Description | Published |
---|---|---|
20140258927 | INTERACTIVE GRAPHICAL DOCUMENT INSIGHT ELEMENT - In one embodiment, metadata associated with a document is received. At least one keyword is extracted from the received metadata, wherein the at least one keyword include at least one of actionable information and non-actionable information. Further, an interactive graphical document insight element is generated including a representation of the non-actionable information and one or more interactive icons representing the actionable information. The generated interactive graphical document insight element is rendered on a computer generated user interface. | 09-11-2014 |
Dijixa Chandubhai Rana, Vadodara IN
Patent application number | Description | Published |
---|---|---|
20140099316 | NOVEL PIPERIDINYL MONOCARBOXYLIC ACIDS AS S1P1 RECEPTOR AGONISTS - The present invention relates to novel compounds acting as agonists at S1P (sphingosine-1-phosphate) receptors, compositions containing these compounds, use of these compounds in medicine and their process of preparation. | 04-10-2014 |
Dilip Kumar Rana, Mumbai IN
Patent application number | Description | Published |
---|---|---|
20110196134 | Process for PEGylation of Proteins - The present invention relates to a process for improving pegylation reaction yield of r-metHuG-CSF comprising conjugating r-metHuG-CSF to a PEG aldehyde at a free amine moiety at the N terminal end on the G-CSF in presence of a reducing agent in a pegylation buffer solution comprising a polyol having the formula C | 08-11-2011 |
D. P. S. Rana, Up IN
Patent application number | Description | Published |
---|---|---|
20130213857 | Solvent Extraction Process for Removal of Naphthenic Acids and Calcium from Low Asphaltic Crude Oil - The present disclosure provides a process for obtaining extracted crude oil (ECO) which is substantially free of naphthenic acids, calcium and other impurities from low asphaltic crude oils or their residue fractions by preferential extraction of saturates using at least one solvent. | 08-22-2013 |
Jai Singh Rana, Dehradun IN
Patent application number | Description | Published |
---|---|---|
20110016154 | PROFILE-BASED AND DICTIONARY BASED GRAPH CACHING - Methods and apparatuses are disclosed for caching portions of a Deterministic Finite Automata (DFA) graph during a compilation stage prior to a run-time stage that identifies attack traffic based on the graph. Cacheable components are identified based on a traffic profile, a dictionary of keywords, and/or a geometrical configuration of the graph. Techniques are disclosed for performing various types of caching alone or in combination with other types. Caching based on a dictionary or profile exploit a tendency of graph traversals performed during non-attack scenarios to remain near root nodes that correspond to the start of patterns designating blacklist traffic. By caching nodes that are near root nodes and that are visited frequently during peacetime (non-attack) scenarios, significant cache hits may be achieved during run-time execution. Caching graph components while compiling patterns using presently disclosed techniques avoids the need for expensive hardware to learn what and when to cache. | 01-20-2011 |
Madhu Rana, Punjab IN
Patent application number | Description | Published |
---|---|---|
20110244034 | SUSTAINED RELEASE DRUG DELIVERY SYSTEM - The invention discloses a controlled release dosage form comprising a therapeutically effective amount of a pharmaceutically active agent, illustrated by Acyclovir, that would release in about 12 hours not more than about 90% of the said active agent in a simulated gastric juice in a first order rate of release in a USP type 1 dissolution test, and not containing a solubilizer or a swelling enhancer or both, comprising (a) a tablet made from polymer matrix of at least two biocompatible polymers, illustrated by Carbopol 974P and polyethylene oxide, the said pharmaceutically active agent and pharmaceutically permitted excipients; the said tablet capable of rapid swelling without disintegration in the said simulated gastric juice to a size that shall result in its gastric retention in the stomach and start controlled release of the said active agent by starting controlled erosion as well as diffusion immediately after coming into contact with the said gastric juice, or (b) microspheres of ungrafted chitosan or a chitosan derivative illustrated by thiolated chitosan and trimethyl chitosan, or Carbopol incorporating the said active agent, wherein the said pharmaceutically active agent is not a polymeric molecule and after administration in stomach, the said microspheres adhare to the gastric mucosa for a long time releasing the active agent in a controlled way. | 10-06-2011 |
Manmohan Rana, New Delhi IN
Patent application number | Description | Published |
---|---|---|
20090316464 | LOW POWER READ SCHEME FOR READ ONLY MEMORY (ROM) - A ROM includes a ROM array, an address decoder, a control circuit, a precharge tracker, a precharge circuit, a reference word line, a reference bit line and a reference sense generator. The control circuit generates control signals for reading the ROM. The address decoder enables a bit line and a word line. The precharge tracker generates a programmable precharge signal, which is provided to the precharge circuit for precharging the enabled bit line. A reference word line is enabled based on the programmable precharge signal and the control signals for tracking the enabled word line. A reference bit line is enabled based on the reference word line for tracking the enabled bit line. The reference sense generator generates a programmable sense signal based on the reference bit line, the programmable precharge signal and the control signals for reading a bit cell corresponding to the enabled bit line and word line. | 12-24-2009 |
Manmohan Rana, Ghaziabad IN
Patent application number | Description | Published |
---|---|---|
20100208506 | READ ONLY MEMORY AND METHOD OF READING SAME - A Read Only Memory (ROM) device includes a ROM array, a row address decoder, a column address decoder, a column multiplexer, and a control circuit. Data is stored in bit cells in the ROM array. The control circuit generates control signals for reading the ROM. The row address decoder selects a word line. The column address decoder enables a bit line. The data is sensed from a bit cell corresponding to the selected word line and the enabled bit line by a corresponding sense amplifier and delivered on a data output pin of the ROM. The control signals for enabling the bit line and the sense amplifier operate at a higher voltage than supply voltage of the ROM. This reduces the ROM read time. | 08-19-2010 |
20110128807 | MEMORY DEVICE AND SENSE CIRCUITRY THEREFOR - A memory device includes a memory array, sense circuitry coupled to the memory array, and timing circuitry coupled to the sense circuitry. The timing circuitry generates a sense trigger signal to enable the sense circuitry. A strap region is formed adjacent the memory array. A reference word line is coupled to the timing circuitry. The reference word line formed in the strap region. | 06-02-2011 |
20110211382 | HIGH DENSITY AND LOW VARIABILITY READ ONLY MEMORY - A read-only memory for storing two data values using a single transistor includes a word line, a pair of bit lines, a select line, and a transistor to store data corresponding to each bit lines in the pair of bit lines. The gate terminal of the transistor is connected to the word line, a first diffusion terminal of the transistor is connected to one of the first bit line and the select line based on the first data value and a second diffusion terminal of the transistor is connected to one of the second bit line and the select line based on the second data value. | 09-01-2011 |
20130339761 | POWER MANAGEMENT SYSTEM FOR ELECTRONIC CIRCUIT - A power management circuit for managing power supplied to an electronic circuit by a core power supply. The electronic circuit includes digital and analog circuit domains and operates in POWER-ON, RUN and STANDBY modes. The power management circuit includes a master state machine that exchanges a handshake signal with the analog circuit domain to monitor the modes of operation and generates first and second configuration signals. The power management circuit enables and disables the analog circuit domain based on the first and second configuration signals. A switch connected to the core power supply and the digital circuit module enables and disables the digital circuit domain based on the second configuration signal. | 12-19-2013 |
20140197883 | WELL-BIASING CIRCUIT FOR INTEGRATED CIRCUIT - A well-biasing circuit for an integrated circuit (IC) includes a well-bias regulator for providing well-bias voltages (n-well and p-well bias voltages) to well-bias contacts (n-well and p-well bias contacts) of each cell of the IC when the integrated circuit is in STOP and STANDBY modes. A switch is connected between a core power supply and the well-bias contact for connecting and disconnecting the core power supply and the well-bias contact when the IC is in RUN and STOP modes, and STANDBY mode, respectively. A voltage inverter circuit and a CMOS inverter circuit enable and disable the switch when the IC is in the RUN mode, and STOP and STANDBY modes, respectively. | 07-17-2014 |
20150263039 | STANDARD CELL LAYOUT FOR LOGIC GATE - A standard cell layout for a multiple input logic gate includes first through fourth parallel gate electrodes disposed over first and second active regions. The first and second gate electrodes are disposed on a first side of a first axis at first and second distances, respectively, from the first axis, and the third and fourth gate electrodes are disposed on a second side of the first axis at third and fourth distances, respectively, from the first axis. The first distance is greater than the second distance and the fourth distance is greater than the third distance. The third and fourth gate electrodes form a mirror image of the first and second gate electrodes about the first axis. | 09-17-2015 |
20150378385 | INTEGRATED CIRCUIT WITH INTERNAL AND EXTERNAL VOLTAGE REGULATORS - An integrated circuit that supports both internal and external voltage regulators as well as various modes, such as a low power mode or a test mode, includes voltage regulator selection circuitry and power control circuitry. The regulator selection circuitry selects one of internal and external regulators based on two pin conditions. The power control circuitry controls ON/OFF status of the regulators corresponding to a power mode, including power-on reset, entering a low power mode, and wake-up from a low power mode. | 12-31-2015 |
20160033567 | CRYSTAL OSCILLATOR MONITORING CIRCUIT - In an integrated circuit, a clock monitor circuit detects when an analog clock signal output by an on-chip crystal oscillator has stabilized. The clock monitor circuit uses an envelope follower circuit to monitor the envelope of the analog clock signal and compare the amplitude of the envelope with a predetermined amplitude value. When the predetermined value is reached and the envelope has remained steady for a predetermined time, an oscillator okay signal is generated. If an oscillator okay signal is not detected within another predetermined time, then an oscillator failure signal may be generated. | 02-04-2016 |
Manmohan Rana, Indirapuram IN
Patent application number | Description | Published |
---|---|---|
20150318842 | APPARATUS AND METHOD FOR PREVENTING MULTIPLE RESETS - Multiple resets in a system-on-chip (SOC) during boot where on-board regulators and low voltage detector circuits have different trimmed and untrimmed values may be avoided by the inclusion of a series of latches that latch the trimmed values during boot and retain the trim values even during a SOC reset event. The SOC is prevented from entering into a reset loop during boot or when exiting reset for any reason other than boot. A power-on-reset comparator circuit that does not depend on any trim values enables the latches and only clears the latched trim values if its own supply voltage falls below a preset level. | 11-05-2015 |
Manoj Rana, Gurgaon IN
Patent application number | Description | Published |
---|---|---|
20150231477 | METHOD AND SYSTEM TO ANALYZE SPORTS MOTIONS USING MOTION SENSORS OF A MOBILE DEVICE - A method and system to analyze sports motions using the motion sensors of a mobile device, such as a smart phone, is provided. This method uses the mobile device motion sensor output to define the impact point with a virtual object, such as a golf ball, baseball or tennis ball. The motion sensor signature of the sports motion is analyzed for characteristics, specific to each type of sports motion. A method is disclosed using multiple sensors outputs in a mobile device to compute the impact point with a virtual object, such as a golf ball, baseball, tennis ball. Further, a method is disclosed where moving virtual sports objects interact with virtual sports motions and the responsive outputs are displayed on the mobile device and/or any Web-enabled display device. | 08-20-2015 |
20150238858 | WEB-BASED GAME PLATFORM WITH MOBILE DEVICE MOTION SENSOR INPUT - A distributed gaming platform is provided wherein mobile devices (e.g., a smartphone) with motion sensors are used as input controllers of a game. A cloud-based gaming rules engine manages multiple players and the content for display in the game. The game output is displayed on any web-enabled display which is physically distinct from the mobile device. Multiple players may simultaneously play the same game, or different games, in multiple geographic locations. | 08-27-2015 |
Manoj Kumar Rana, Gurgaon IN
Patent application number | Description | Published |
---|---|---|
20160059120 | METHOD OF USING MOTION STATES OF A CONTROL DEVICE FOR CONTROL OF A SYSTEM - This invention is for control of a system using motion states of a control device. The method enables complex system control typically controlled by complex controllers, but does not require any buttons or actuators, or video capture of body movements or gesture. An embodiment of the invention utilizes the gyroscope and accelerometer motion sensors of a control device such as a smart phone, smart watch, fitness band, or other device with motion sensors connected, via a cable or wirelessly, to a processor for analysis and translation. | 03-03-2016 |
Narayan Singh Rana, Bangalore IN
Patent application number | Description | Published |
---|---|---|
20120315842 | WIRELESS TELEMETRY AUTO TUNING FOR TORQUE MEASUREMENT SYSTEM - A torque measurement system that includes a rotor device and a stator device can perform automatic tuning to improve the initial tuning performed during design and assembly. The stator device can include a variable capacitive element and a micro-controller configured to adjust a capacitance value of the variable capacitive element. Additionally or alternatively, the rotor device can include a variable capacitive element and a micro-controller configured to adjust a capacitance value of the variable capacitive element. The adjustment of the capacitive elements can be based on the quality of signal detected at either the rotor device or stator device. | 12-13-2012 |
20140146897 | WIRELESS TELEMETRY AUTO FOR TORQUE MEASUREMENT SYSTEM - A torque measurement system that includes a rotor device and a stator device can perform automatic tuning to improve the initial tuning performed during design and assembly. The stator device can include a variable capacitive element and a micro-controller configured to adjust a capacitance value of the variable capacitive element. Additionally or alternatively, the rotor device can include a variable capacitive element and a micro-controller configured to adjust a capacitance value of the variable capacitive element. The adjustment of the capacitive elements can be based on the quality of signal detected at either the rotor device or stator device. | 05-29-2014 |
20150131498 | HYBRID DIPLEXER AND CIRCULATOR FRONTEND FOR GPS RECEIVER AND SATCOM MODEM SHARING COMMON ANTENNA - A hybrid diplexer-circulator system including a circulator and a modified-diplexer is provided. The circulator includes a first circulator-port, a second circulator-port coupled to a first chain comprising a receiver module, and a third circulator-port coupled to a second chain comprising a satellite modem. The first chain receives first-frequency signals and reflects second-frequency signals. The second chain receives the second-frequency signals reflected from the first chain and transmits third-frequency signals. The modified-diplexer includes: a first diplexer-port of the modified-diplexer, which is shared as the first circulator-port; a second diplexer-port; and third diplexer-port in the second chain. The second diplexer port inputs the first-frequency signals from a filter in the first chain. The third diplexer-port: inputs the second-frequency signals reflected by the first chain; outputs the second-frequency signals to be received by the satellite modem; inputs third-frequency signals transmitted by the satellite modem; and outputs the third-frequency signals to the third circulator-port. | 05-14-2015 |
Nitin Rana, Bangalore IN
Patent application number | Description | Published |
---|---|---|
20100158026 | Transparent Interaction with multi-layer protocols via Selective Bridging and Proxying - The current invention defines a device and a method of logically inserting the device between two other network devices, for example, in a 3GPP Radio Access Network. The device transparently monitors and interacts with one or more control protocol layers in the two neighboring devices. The invention defines methods by which the intercepting node selectively passes through or proxies (selectively modifying portions of the protocols content) in such as way that the neighbor nodes are un-aware of the intercepting device. The proxy operation implies that the intercepting node is capable of terminating some protocol elements, injecting some protocol elements, or modifying protocol elements before forwarding them in such a way that the operation is transparent to neighboring nodes. These selective insertion/modifications facilitate identifying signaling connections for specific mobile clients, and enhancing and modifying service features for dataplane accesses for those client devices, while transparently passing other protocol messages. | 06-24-2010 |
20130021933 | RAN Analytics, Control And Tuning Via Multi-Protocol, Multi-Domain, And Multi-RAT Analysis - The present invention identifies methods and procedures for correlating control plane and user plane data, consolidating and abstracting the learned and correlated data in a form convenient for minimizing and exporting to other network devices, such as those in the Core Network and the Access Network, or the origin server, CDN devices or client device. These correlation methods may use Control Plane information from a plurality of interfaces in the RAN, and User plane information from other interfaces in the RAN or CN. IF the device is deployed as an inline proxy, this information may be exported using in-band communication, such as HTTP extension headers in HTTP Request or Response packets, or another protocol header, such as the IP or GTP-U header field. Alternatively, this information can be exported out-of-band using a separate protocol between the RAN Transit Network Device (RTND) and the receiving device. | 01-24-2013 |
20130258865 | Distributed RAN Information Collection, Consolidation And RAN-Analytics - Control Plane and User plane packet data are collected within the Radio Access Network using a plurality of network devices. Consolidation and summarization of this information is then performed to present a unified picture of RAN through abstract APIs to management and analytics applications. The invention identifies methods of retaining the collected network data, such as control and application protocol headers at the collection points, and consolidation and exporting this network data to management/reporting/analytics application using application driven rules for consolidation and summarization. Real-time statistical analysis tools, which may be used to predict failure and degradation trends and proactively control the underlying causes, are also disclosed. | 10-03-2013 |
20160080965 | Distributed RAN Information Collection, Consolidation And RAN-Analytics - Control Plane and User plane packet data are collected within the Radio Access Network using a plurality of network devices. Consolidation and summarization of this information is then performed to present a unified picture of RAN through abstract APIs to management and analytics applications. The invention identifies methods of retaining the collected network data, such as control and application protocol headers at the collection points, and consolidation and exporting this network data to management/reporting/analytics application using application driven rules for consolidation and summarization. Real-time statistical analysis tools, which may be used to predict failure and degradation trends and proactively control the underlying causes, are also disclosed. | 03-17-2016 |
Parvinder Rana, Ambala IN
Patent application number | Description | Published |
---|---|---|
20100026403 | SELECTABLE DRIVE STRENGTH HIGH FREQUENCY CRYSTAL OSCILLATOR CIRCUIT - A method, system, and apparatus to a selectable drive strength high frequency crystal oscillator circuit are disclosed. In one embodiment, a system includes a crystal oscillator circuit to generate a signal with a specified frequency value, and a programmable amplifier circuit containing a plurality of programmable inverting amplifiers, and wherein certain ones of a plurality of inverting amplifiers are operated to change a gain and/or a bandwidth of the signal according to the specified frequency value of the crystal oscillator circuit. The system may include further comprising a resistor circuit coupled in parallel to the programmable amplifier circuit to set an operating point of the programmable amplifier circuit. | 02-04-2010 |
Parvinder Rana, Bangalore IN
Patent application number | Description | Published |
---|---|---|
20150092475 | PSEUDO RETENTION TILL ACCESS MODE ENABLED MEMORY - A memory configurable to be used in an RTA mode includes an input latch configured to receive an input address bus and to generate a latched address bus that corresponds to a memory location. An address flop is configured to save the latched address and to generate a flopped address. A first block address pre-decoder stage is configured to generate a pre-decoded latched address to an RTA generation logic in response to the latched address bus; and a second block address pre-decoder configured to generate a pre-decoded flopped address to the RTA generation logic in response to the flopped address. The RTA generation logic generates an RTA enable signal one clock cycle before a memory block access, to activate a memory block corresponding to the memory location, such that an array supply voltage of the memory block starts charging one clock cycle before a memory block access. | 04-02-2015 |
Parvinder Kumar Rana, Ambala Cantt. IN
Patent application number | Description | Published |
---|---|---|
20110037527 | FAST START-UP CRYSTAL OSCILLATOR - An exemplary fast start-up crystal oscillator with reduced start-up time. The exemplary oscillator reduces the start-up time (i.e., the time taken to attain sustained stable oscillations after the power is turned on) by increasing the negative resistance of a circuit. Increasing the negative resistance increases the rate of growth of the oscillations, thereby reducing start-up time. The exemplary crystal oscillator includes a gain stage with negative resistance. A crystal with shunt capacitance is placed in the feedback loop of the gain stage. A buffer is coupled to the gain stage such that it blocks the crystal shunt capacitance from loading the gain stage, effectively increasing the negative resistance of the gain stage. Further, an oscillation detection and control circuit is coupled between the crystal and the gain stage. The oscillation detection and control circuit connects the buffer during start-up, and disconnects the buffer once an oscillation signal attains sustained stable oscillations. | 02-17-2011 |
Parvinder Kumar Rana, Bangalore IN
Patent application number | Description | Published |
---|---|---|
20110299349 | Margin Testing of Static Random Access Memory Cells - A static random access memory (SRAM) and method of evaluating the same for cell stability, write margin, and read current margin. The memory is constructed so that bit line precharge can be disabled, and so that complementary bit lines for each column of cells can float during memory operations. The various tests are performed by precharging the bit lines for a column, then floating the bit lines, and while the bit lines are floating, pulsing the word lines of one or more selected cells to cause the voltage on one of the bit lines to discharge. The discharged bit line voltage is then applied to another cell, which is then read in a normal read operation to determine whether its state changed due to the discharged bit line voltage. The memory can be characterized for cell stability, write margin, and read current margin in this manner; the method can also be adapted into a manufacturing margin screen, or used in failure analysis. | 12-08-2011 |
20130215689 | HIGH PERFORMANCE TWO-PORT SRAM ARCHITECTURE USING 8T HIGH PERFORMANCE SINGLE-PORT BIT CELL - An 8T memory bit cell receives a clock signal and read and write address signals. A read address latch/clock circuit receives the clock signal and the read address signals and initiates a read operation during a first clock cycle state. A write address flip-flop/clock circuit receives the clock signal and the write address signals and initiates a write operation during a second clock cycle state. An inverter receives and inverts the clock signal and applies the inverted clock signal to the write address flip-flop/clock circuit. The read address latch/clock circuit initiates a read word line precharge operation during the second clock cycle state and a write word line precharge operation during the first clock cycle state. The write address flip-flop/clock circuit may also include a loose self-timer to end a write cycle is a clock signal continues beyond a predetermined time. | 08-22-2013 |
Parvinder Kumar Rana, Ambala IN
Patent application number | Description | Published |
---|---|---|
20110216618 | VOLTAGE COMPENSATED TRACKING CIRCUIT IN SRAM - Supply voltage compensated tracking circuit in a split-rail static random access memory (SRAM). The circuit includes a tracking circuit for tracking a delay required for generating sense amplifier enable (SE) signal in a memory. The tracking circuit receives an array supply voltage (VDDAR) and a periphery supply voltage (VDDPR). Further, the circuit includes a discharge control circuit, operatively coupled to the tracking circuit, for increasing delay in activating a first transistor of the tracking circuit when VDDAR is higher than VDDPR; and a contention circuit including an output coupled to the first transistor, for delaying a discharge path activation through the first transistor when VDDAR is lower than the VDDPR. | 09-08-2011 |
Piyush Maheshbhai Rana, Vadodara IN
Patent application number | Description | Published |
---|---|---|
20110306796 | PROCESS FOR THE PREPARATION OF 1-BROMO-3,5-DIMETHYL ADAMANTANE - The present invention relates to an improved process for the preparation of 1-bromo-3,5-dimethyl adamantane of formula (III), which is an useful intermediate for synthesis of 1-amino-3,5-dimethyl adamantane of formula (I) or pharmaceutically acceptable salt thereof. | 12-15-2011 |
Piyush Maheshbhai Rana, Gujarat IN
Patent application number | Description | Published |
---|---|---|
20090312538 | PROCESS FOR THE PREPARATION OF SUCRALOSE OF HIGH PURITY - The present invention relates to an improved process for the preparation of Sucralose having purity of at least 99.6% comprising steps of | 12-17-2009 |
Pravat Ranjan Rana, Bangalore IN
Patent application number | Description | Published |
---|---|---|
20160125495 | PRODUCT BROWSING SYSTEM AND METHOD - A query is input to a search engine and search results, such as product records, are identified as relevant to the query. The results are presented to a user in a first interface, such as one allowing scrolling in a first direction. On selection of a result, a second interface is displayed of a “shelf” for the selected result, the shelf including related items such as might be located on a same shelf as the selected result in a retail location. The second interface may allow scrolling in a second direction perpendicular to the first direction. | 05-05-2016 |
20160125504 | Electronic Shopping Cart Processing System And Method - An electronic shopping cart of a user is presented in a first interface during checkout, such as one allowing scrolling through representations of items in a shopping list in a first direction. On selection of an item, a second interface is displayed of a “shelf” for the selected item, the shelf including related items such as might be located on a same shelf as the selected result in a retail location. The second interface may allow scrolling in a second direction perpendicular to the first direction. Items in the second interface may be selected and either added to the electronic shopping cart or used to replace the selected item. | 05-05-2016 |
Ragnesh Kumar Rana, Mumbai IN
Patent application number | Description | Published |
---|---|---|
20080207946 | PROCESS FOR PREPARATION OF HIGHLY PURE ISOTRETINOIN - The present invention relates to a process for preparation of isotretinoin and more specifically, to a purification process for obtaining highly pure isotretinoin that is useful as a keratolytic agent, particularly useful for the treatment of acne. The process involves treating isotretinoin containing metal contamination and/or other impurities with a base in a suitable solvent to form a solution of isotretinoin, followed by adsorption, precipiation, and filtration or centrifugation | 08-28-2008 |
Rohit K. Rana, Hyderabad IN
Patent application number | Description | Published |
---|---|---|
20100267594 | Nano-encapsulated triggered-release viscosity breakers - A method for the encapsulation and triggered-release of water-soluble or water-dispersible materials. The method comprises a) providing an amount of electrolyte having a charge, b) providing an amount of counterion having a valence of at least 2, c) combining the polyelectrolyte and the counterion in a solution such that the polyelectrolyte self-assembles to form aggregates, d) adding a compound to be encapsulated, and e) adding nanoparticles to the solution such that nanoparticles arrange themselves around the aggregates. Release of the encapsulated species is triggered by disassembly or deformation of the microcapsules though disruption of the charge interactions. This method is specifically useful for the controlled viscosity reduction of the fracturing fluids commonly utilized in the oil field. | 10-21-2010 |
Rohit Kumar Rana, Hyderabad IN
Patent application number | Description | Published |
---|---|---|
20110223111 | CALCIUM CARBONATE MICROSTRUCTURES USEFUL IN ENCAPSULATION APPLICATIONS AND A PROCESS FOR THE PREPARATION THEREOF - A facile method to synthesize stable calcium carbonate microstructures is demonstrated which allows in situ encapsulation of sensitive molecules like drugs. The methodology involves a macromolecular assembly of anionic polypeptide with cationic peptide oligomer to concurrently template and hold to stabilize the mineralized structure. The heterogeneously distributed mixture of anionic and cationic residues in the macromolecular assembly, similar to that is found in natural systems assists in recognizing and coassembling Ca | 09-15-2011 |
Saugata Rana, Kolkata IN
Patent application number | Description | Published |
---|---|---|
20150085315 | Print Job Tracking and Policy Enforcement - Methods and apparatus enforce policy on print jobs and track them per users. A computing device has a layered service provider (LSP) and a spooler. The LSP determines whether data coming to it corresponds to print data or not. If so, it extracts user information and determines whether any imaging policies apply to the user. If policy applies, the LSP iteratively acknowledges to the spooler that data is being successfully transferred to an imaging device so the spooler will continue sending a remainder of the data corresponding to the print job. Upon receipt of an entire print job, the LSP enforces policy and notifies the user. It also notifies an accounting server to update its policies. Further embodiments note relationships between the LSP and spooler and their interaction with layers in a TCP/IP model. | 03-26-2015 |
20150085316 | Print Job Tracking and Policy Enforcement - Methods and apparatus enforce policy on print jobs and track them per users. A computing device has a layered service provider (LSP) and a spooler. The LSP determines whether data coining to it corresponds to print data or not. If so, it extracts user information and determines whether any imaging policies apply to the user. If policy applies, the LSP iteratively acknowledges to the spooler that data is being successfully transferred to an imaging device so the spooler will continue sending a remainder of the data corresponding to the print job. Upon receipt of an entire print job. the LSP enforces policy and notifies the user. It also notifies an accounting server to update its policies. Further embodiments note relationships between the LSP and spooler and their interaction with layers in a TCP/IP model. | 03-26-2015 |
Subhasis Rana, Kolkata West Bengal IN
Patent application number | Description | Published |
---|---|---|
20150301020 | A SENSOR COMPOSITION FOR ACETONE DETECTION IN BREATH - The present invention provides a composition for acetone detection and a process of preparation thereof. The composition comprises γ-ferric oxide (γ-Fe | 10-22-2015 |
Vikas Rana, Pehowa IN
Patent application number | Description | Published |
---|---|---|
20100156496 | HIGH VOLTAGE SWITCH WITH REDUCED VOLTAGE STRESS AT OUTPUT STAGE - The present invention discloses a high voltage switching module having reduced stress at its driver output stage which in turn controls the gate of a transistor requiring a high current drive. The switching module includes a negative elevating circuit, a delay module, a pull-up circuit, and a pull down circuit. The negative elevating circuit senses a transition of a logic input signal to generate a control signal. The first pull-up circuit is operatively coupled to this control signal for switching the driver output from a negative voltage to a ground voltage. There is an additional delay module which is configured to provide a delay in the logic input signal. This delayed logic input signal is operatively coupled to the second pull-up stage which takes the output of the driver from GND to VDD. The pull-down circuit is operatively coupled to the negative elevator for controlling a voltage at the driver output to the negative level. The module further comprises a switching circuit that is operatively coupled to the driver output for controlling the passing of a high voltage with high current requirements. | 06-24-2010 |
Vikas Rana, Pehowa (kkr) IN
Patent application number | Description | Published |
---|---|---|
20120182060 | NEGATIVE VOLTAGE LEVEL SHIFTER CIRCUIT - A negative voltage level shifter circuit includes a pair of input transistors, a gate of each input transistor being driven by one of an input signal and an inverted version of the input signal, a cascode sub-circuit coupled to the pair of input transistors, and a pair of cross-coupled transistors for locking a state of the voltage level shifter depending on the input signal, wherein respective gates of the cross-coupled transistors are driven by outputs of respective comparator sub-circuits. | 07-19-2012 |
Vikas Rana, Noida IN
Patent application number | Description | Published |
---|---|---|
20110299355 | WORD LINE DRIVER FOR MEMORY - A word-line driver includes first, second and third transistors. The first transistor includes a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal and a second conduction terminal coupled to the word-line. The second transistor includes a gate terminal driven by a second group selection signal, a second conduction terminal driven by the second sub-group selection signal, and a first conduction terminal coupled to the word-line. The third transistor includes a gate terminal driven by a third the group selection signal, a first conduction terminal driven by a first sub-group selection signal, and a second conduction terminal coupled to the word-line. | 12-08-2011 |
20140233321 | WORD-LINE DRIVER FOR MEMORY - A word-line driver includes first, second and third transistors. The first transistor includes a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal and a second conduction terminal coupled to the word-line. The second transistor includes a gate terminal driven by a second group selection signal, a second conduction terminal driven by the second sub-group selection signal, and a first conduction terminal coupled to the word-line. The third transistor includes a gate terminal driven by a third the group selection signal, a first conduction terminal driven by a first sub-group selection signal, and a second conduction terminal coupled to the word-line. | 08-21-2014 |
20150146490 | NON-VOLATILE MEMORY WITH REDUCED SUB-THRESHOLD LEAKAGE DURING PROGRAM AND ERASE OPERATIONS - A memory includes an array of non-volatile memory cells. Each cell includes a select transistor in series connection with a floating gate transistor. The cells are configurable for operation in a programming mode and an erase mode. When in the programming mode, the gate terminal of the select transistor is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage. When in the erase mode, the gate terminal of a pull-down transistor coupled to the memory cell is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage. | 05-28-2015 |
20160065220 | CMOS OSCILLATOR HAVING STABLE FREQUENCY WITH PROCESS, TEMPERATURE, AND VOLTAGE VARIATION - A clock signal generation circuit configured to generate the clock signal having a frequency that is maintained across variations in a number of operating conditions, such as changes in supply voltage, temperature and processing time. In an embodiment, the frequency spread of the generated clock signal of a PVT-compensated CMOS ring oscillator is configured to compensate for variations in the supply voltage, as well as for variations in process and temperature via a process and temperature compensation circuit. The PVT-compensated CMOS ring oscillator includes a regulated voltage supply circuit to generate a supply voltage that is resistant to variations due to changes in the overall supply voltage. | 03-03-2016 |
20160099033 | COLUMN DECODER CIRCUITRY FOR A NON-VOLATILE MEMORY - A memory includes a column decoder performing at least two levels of decoding using a first level decoder that decodes between the column bit lines and first level decode lines and a second level decoder that decodes between the first level decode lines and second level decode lines. The second level decoder includes first transistors coupled between the first level decode lines and read output lines and second transistors coupled between the first level decode lines and write input lines. The first transistors have a first voltage rating and are driven by decode control signals referenced to a low supply voltage compatible with the first voltage rating. The second transistors have a second voltage rating, higher than the first voltage rating, and are driven by decode control signals referenced to a high supply voltage (in excess of the low supply voltage) compatible with the second voltage rating. | 04-07-2016 |