Meng-Hsueh
Meng-Hsueh Chiang, Yilan City TW
Patent application number | Description | Published |
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20100026346 | HIGH-DENSITY LOGIC TECHNIQUES WITH REDUCED-STACK MULTI-GATE FIELD EFFECT TRANSISTORS - Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can be reduced and performance can be enhanced. | 02-04-2010 |
Meng-Hsueh Wang, Hsinchu City TW
Patent application number | Description | Published |
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20150162910 | LOW-POWER INTERNAL CLOCK GATED CELL AND METHOD - A circuit includes a clock trigger block and a logic circuit. The logic circuit is configured to output a signal to the clock trigger block based on a logic level of an enable signal received at the logic circuit. The clock trigger block is configured to output an output signal response to a clock signal received at the clock trigger block and the signal received from the logic circuit. | 06-11-2015 |
Meng-Hsueh Wu, Taipei TW
Patent application number | Description | Published |
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20130043061 | CIRCUIT STRUCTURE OF ELECTRONIC DEVICE AND ITS MANUFACTURING METHOD - The present disclosure related to circuit structure of an electronic device, wherein the circuit structure comprises of a main line formed on a substrate; and at least an auxiliary line electrically connected to the main line to form a conductive return circuit used for a signal to pass through the auxiliary line when the main line is disconnected. Addition of the auxiliary line avoids any breaking of signal transmission due to partial disconnection of the main line. The present disclosure also relates to a method for manufacturing the circuit structure, wherein the method simplifies the manufacturing process and also reduces the rate of deformation or disconnection of lines. | 02-21-2013 |
20140079917 | DEVICE HAVING MULTIPLE PRINTING LAYERS AND A PRINTING METHOD THEREOF - The present disclosure discloses a device having multiple printing layers and a printing method thereof, wherein said method comprises: seriatim stack-printing at least one printing layer on a protective substrate in an ascending order of size, wherein the protective substrate has an open surface exposed outward and a laminating surface laminated with a plate, and wherein the printing layer is printed on a part of the laminating surface and the closer the printing layer is to the laminating surface, the smaller area the printing layer has so as to reduce height difference between printing layers and make for the following lamination. | 03-20-2014 |