Dorbie
Angus Dorbie, San Diego, CA US
Patent application number | Description | Published |
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20100020069 | PARTITIONING-BASED PERFORMANCE ANALYSIS FOR GRAPHICS IMAGING - In general, this disclosure relates to techniques for providing a visual representation of a graphical scene that includes a number of different graphical partitions, which may allow a user to identify portions of the graphics scene that exhibit reduced performance due to costs associated with screen partitioning. One example device includes a display device and one or more processors. The one or more processors are configured to display one or more graphics images in a graphical scene on the display device, display a graphical representation of partitions that overlay the one or more graphics images and that graphically divide the scene on the display device, and analyze graphics data for the one or more graphics images to determine which portions of the graphics data are associated with multiple ones of the partitions. | 01-28-2010 |
20100020087 | PERFORMANCE ANALYSIS DURING VISUAL CREATION OF GRAPHICS IMAGES - In general, this disclosure relates to techniques for using graphics instructions and state information received from a graphics device to visually create a graphics image. Performance analysis may also be conducted to identify potential bottlenecks during instruction execution on the graphics device. One example device includes a display device and one or more processors. The one or more processors are configured to receive a plurality of graphics instructions from an external graphics device, wherein the graphics instructions are executed by the external graphics device to display a graphics image, and to receive state information from the external graphics device, wherein the state information is associated with execution of the graphics instructions on the external graphics device. The one or more processors are further configured to display, on the display device, a representation of the graphics image according to the graphics instructions and the state information. | 01-28-2010 |
20100020098 | MAPPING GRAPHICS INSTRUCTIONS TO ASSOCIATED GRAPHICS DATA DURING PERFORMANCE ANALYSIS - In general, this disclosure relates to techniques for optimizing a graphics scene, such as a three-dimensional (3D) scene, by allowing application developers and/or graphics artists to identify which graphics instructions and associated graphics data (e.g., polygonal data, texture data) may be associated with identified performance issues. One example method comprises receiving mapping information from the external device, wherein the mapping information includes information to map the graphics instructions to primitive graphics data that is used to render one or more graphics images during execution of the graphics instructions, and identifying a performance issue associated with execution of at least one graphics instruction within the graphics instructions. The method further comprises using the mapping information to identify a portion of the primitive graphics data that is associated with the performance issue based upon execution of the at least one graphics instruction. | 01-28-2010 |
Angus M. Dorbie, San Diego, CA US
Patent application number | Description | Published |
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20080198168 | EFFICIENT 2-D AND 3-D GRAPHICS PROCESSING - Techniques for supporting both 2-D and 3-D graphics are described. A graphics processing unit (GPU) may perform 3-D graphics processing in accordance with a 3-D graphics pipeline to render 3-D images and may also perform 2-D graphics processing in accordance with a 2-D graphics pipeline to render 2-D images. Each stage of the 2-D graphics pipeline may be mapped to at least one stage of the 3-D graphics pipeline. For example, a clipping, masking and scissoring stage in 2-D graphics may be mapped to a depth test stage in 3-D graphics. Coverage values for pixels within paths in 2-D graphics may be determined using rasterization and depth test stages in 3-D graphics. A paint generation stage and an image interpolation stage in 2-D graphics may be mapped to a fragment shader stage in 3-D graphics. A blending stage in 2-D graphics may be mapped to a blending stage in 3-D graphics. | 08-21-2008 |
Angus M. Dorbie, Redwood City, CA US
Patent application number | Description | Published |
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20140327696 | VARIABLE ACUITY RENDERING USING MULTISAMPLE ANTI-ALIASING - Embodiments are described for a method for using anti-aliasing hardware to generate a higher resolution image at the processing of a lower resolution image with anti-aliasing. A graphics image comprising allocating a buffer used in a multisample anti-aliasing process, wherein the allocated buffer has a dimension comprising a reduction in at least one of the width or height of an original dimension of an original buffer provided by the anti-aliasing hardware; rendering sampled image data to the allocated buffer at a sampling rate proportional to the reduction; and expanding the allocated buffer back to the dimension of the original buffer. | 11-06-2014 |
Angus Macdonald Dorbie, San Diego, CA US
Patent application number | Description | Published |
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20090073166 | METHOD AND APPARATUS FOR OPTIMIZING TRIANGLES INTO TRIANGLE STRIPS ACCORDING TO A VARIETY OF CRITERIA - Methods and computing devices enable optimized triangle strip generation using forward looking game tree evaluation methods with node evaluation of strip options based on desired performance criteria. The evaluation of possible triangle paths is performed using metrics which may be weighted for each desirable criteria at each move depth. A recursive algorithm may be used to recursively descend through alternative triangle paths and accumulates a score for the path. The final score for each evaluated triangle path at a dead end or maximum depth of evaluation provides a basis for selecting the best alternative path from the base or root triangle for graphic processing. This evaluation or alternative triangle paths may be repeated to select each subsequent triangle for processing or may be repeated after a number of triangles within the selected path have been processed. | 03-19-2009 |
20090309876 | METHOD AND APPARATUS FOR ORGANIZING OBJECT GEOMETRY FOR SPATIAL AND MEMORY COHERENCY AND OPTIMAL RENDERING - Methods and computing devices enable the generation of contiguous triangle patches for use in generating triangle strips for processing in a computer graphics engine. A seed triangle is selected and a patch of contiguous triangles is formed by incrementally adding adjacent triangles to the patch at equal steps from the seed triangle until a limit is reached or no more triangles can be added to the patch. Triangles whose vertices are already included in the patch are also added to the patch. If no more triangles can be added to the patch before the vertex limit is reached, a new seed triangle may be selected and another patch generated until the vertex limit is reached. Forming patches of contiguous triangles before generating triangle strips improves memory utilization can speed the processing of computer graphic objects. | 12-17-2009 |
20100273460 | INTEGRATED ALERT SYSTEM - The specification and drawing figures describe a method of automatically providing an integrated alert to the user of a mobile wireless communications instrument on the substantial imminent or actual occurrence of an event and geographic location. A programmable algorithm in the form of an executable program is installed in the mobile wireless communications instrument, which is connectable to a location determination system. Optionally a graphical mapping subsystem is included. | 10-28-2010 |