Patent application number | Description | Published |
20140351446 | ELECTRONIC DEVICE USING LOGICAL CHANNELS FOR COMMUNICATION - An apparatus and method for providing one or more protocols for one or more electronic devices are provided. The method includes establishing, by an electronic device configured to provide a framework interface by executing instructions stored in a memory, one or more physical channels with an external electronic device, using one or more communication modules, executing, by the electronic device, two or more application programs to interface with the framework interface, and communicating, via the framework interface, data from the two or more application programs through the one or more physical channels to the external electronic device, using at least one logical channel or session for a respective one of the two or more application programs. | 11-27-2014 |
20140351832 | ELECTRONIC DEVICE USING FRAMEWORK INTERFACE FOR COMMUNICATION - An apparatus and method for providing one or more protocols for one or more electronic devices are provided. The method includes establishing, by an electronic device configured to provide a framework interface by executing instructions stored in a memory, one or more physical channels with an external electronic device, using one or more communication modules, executing, by the electronic device, two or more application programs to interface with the framework interface, and communicating, via the framework interface, data from the two or more application programs through the one or more physical channels to the external electronic device, using at least one logical channel or session for a respective one of the two or more application programs. | 11-27-2014 |
Patent application number | Description | Published |
20150118508 | TRANSPARENT CONDUCTOR, METHOD FOR PREPARING THE SAME, AND OPTICAL DISPLAY INCLUDING THE SAME - A transparent conductor, a method for preparing the same, and an optical display including the same, the transparent conductor including a base layer; and a conductive layer on the base layer, the conductive layer including metal nanowires and a matrix, wherein the transparent conductor has a transmissive b* value of about 1.5 or less, and the matrix is prepared from a matrix composition including a tri-functional monomer and one of a penta-functional monomer or a hexa-functional monomer a base layer; and a conductive layer formed on the base layer and including metal nanowires and a matrix, wherein the transparent conductor has a transmissive b* value of about 1.5 or less, and the matrix is formed of a composition including a penta- or hexa-functional monomer and a tri-functional monomer. | 04-30-2015 |
20150156866 | TRANSPARENT CONDUCTOR, METHOD FOR PREPARING THE SAME, AND OPTICAL DISPLAY INCLUDING THE SAME - A transparent conductor, a method of fabricating the same, and an optical display, the transparent conductor including a base layer; and a conductive layer on the base layer, the conductive layer including metal nanowires and a matrix, wherein the matrix is prepared from a matrix composition, the matrix composition including inorganic hollow particles, a fluorine-containing monomer, or a mixture thereof. | 06-04-2015 |
Patent application number | Description | Published |
20090300515 | Web server for supporting collaborative animation production service and method thereof - A web server for supporting a collaborative animation production service. The web server includes a user interface (UI) unit to provide a UI to receive direction data for each scene required for animation production in parallel to users connected to the web server, and a generating unit to combine the direction data input to the UI for each scene and generate an animation corresponding to the combined direction data. A plurality of users thereby collaborate to produce an animation in real time, making it possible to shorten the production time of the animation and produce a high quality animation. | 12-03-2009 |
20090327898 | STORAGE MEDIUM, APPARATUS, AND METHOD TO AUTHOR AND PLAY INTERACTIVE CONTENT - A storage medium to store interactive content may include at least one content unit and interactive content including story map information, the story map information selectively connecting the at least one content unit according to conditions to form a story. | 12-31-2009 |
20110087726 | CLOUD SERVER, CLIENT TERMINAL, DEVICE, AND METHOD OF OPERATING CLOUD SERVER AND CLIENT TERMINAL - A cloud computing system that allows a client terminal to make use of different types of devices using a cloud computing service of a cloud server, is provided. The cloud server retrieves a virtual device driver for a device using retrieval information received from the client terminal and installs the virtual device driver so that the client terminal may control the device. Although the client terminal does not support an information format which is supported by the device, the computing service allows information to be used by the client terminal. | 04-14-2011 |
20130006981 | STORAGE DEVICE AND DATA PROCESSING DEVICE UTILIZING DETERMINED DICTIONARY COMPRESSION - A data processing device for a storage device can include a dictionary storage unit that is configured to store a plurality of dictionaries and a compression unit that is configured to determine a selected dictionary from the plurality of dictionaries based on received data, and compress the received data using the selected dictionary to provide compressed data. Each of the plurality of dictionaries can include a plurality of pattern-symbol correspondence relations defining a one-to-one correspondence between respective ones of a plurality of patterns and respective ones of a plurality of symbols. | 01-03-2013 |
20130031300 | NON-VOLATILE MEMORY DEVICE, METHOD OF OPERATING THE SAME, AND MEMORY SYSTEM HAVING THE NON-VOLATILE MEMORY DEVICE - According to an aspect of the inventive concepts, there is provided a non-volatile memory device including a memory array with at least one stripe. The at least one stripe includes at least one parity page and at least one data page. The non-volatile memory device further includes a chip controller. The chip controller includes an operation module configured to perform an operation on data input from the outside of the memory device, to store a result of the performing, and to program the result of the performing into the at least one parity page. The chip controller further includes a data buffer configured to store the input data and to program the input data into the at least one data page. | 01-31-2013 |
Patent application number | Description | Published |
20140351446 | ELECTRONIC DEVICE USING LOGICAL CHANNELS FOR COMMUNICATION - An apparatus and method for providing one or more protocols for one or more electronic devices are provided. The method includes establishing, by an electronic device configured to provide a framework interface by executing instructions stored in a memory, one or more physical channels with an external electronic device, using one or more communication modules, executing, by the electronic device, two or more application programs to interface with the framework interface, and communicating, via the framework interface, data from the two or more application programs through the one or more physical channels to the external electronic device, using at least one logical channel or session for a respective one of the two or more application programs. | 11-27-2014 |
20140351832 | ELECTRONIC DEVICE USING FRAMEWORK INTERFACE FOR COMMUNICATION - An apparatus and method for providing one or more protocols for one or more electronic devices are provided. The method includes establishing, by an electronic device configured to provide a framework interface by executing instructions stored in a memory, one or more physical channels with an external electronic device, using one or more communication modules, executing, by the electronic device, two or more application programs to interface with the framework interface, and communicating, via the framework interface, data from the two or more application programs through the one or more physical channels to the external electronic device, using at least one logical channel or session for a respective one of the two or more application programs. | 11-27-2014 |
Patent application number | Description | Published |
20100279160 | RECHARGEABLE SECONDARY BATTERY HAVING IMPROVED SAFETY AGAINST PUNCTURE AND COLLAPSE - A rechargeable battery according to embodiments of the present invention has improved safety against puncture and collapse. The secondary battery includes an electrode assembly, a case, a first electrode terminal and a second electrode terminal, a cap plate, and a short circuit member. The electrode assembly includes a first electrode, a separator, and a second electrode. The case contains the electrode assembly. The first electrode terminal and a second electrode terminal are electrically connected to the first electrode and the second electrode of the electrode assembly, respectively. The short circuit member extends from the end of one of the first electrode and the second electrode and is wound around the outermost periphery of the electrode assembly to short circuit the electrode assembly when the secondary battery is punctured or collapsed. | 11-04-2010 |
20100279170 | RECHARGEABLE SECONDARY BATTERY HAVING IMPROVED SAFETY AGAINST PUNCTURE AND COLLAPSE - A rechargeable battery having improved safety against puncture and collapse includes an electrode assembly, a case, a first electrode terminal and a second electrode terminal, a cap plate, and a short circuit member. The electrode assembly includes a first electrode, a separator, and a second electrode. The case contains the electrode assembly. The first electrode terminal and a second electrode terminal are electrically connected to the first electrode and the second electrode, respectively. The short circuit member is between the electrode assembly and the case and short circuits the secondary battery when the secondary battery is punctured or collapsed. | 11-04-2010 |
20110052963 | Secondary battery - A secondary battery including a can having at least two receiving spaces with a separation space therebetween, an electrode assembly received in the receiving spaces of the can, a collector electrically connected to the electrode assembly, and a cap plate coupled to an upper portion of the can to seal the can. | 03-03-2011 |
Patent application number | Description | Published |
20140191192 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - There is provided a semiconductor light emitting device having improved light emitting efficiency by increasing an inflow of holes into an active layer while preventing an overflow of electrons. The semiconductor light emitting device includes an n-type semiconductor layer; an active layer formed on the n-type semiconductor layer and including at least one quantum well layer and at least one quantum barrier layer alternately stacked therein; an electron blocking layer formed on the active layer and having at least one multilayer structure including three layers having different energy band gaps stacked therein, a layer adjacent to the active layer among the three layers having an inclined energy band structure; and a p-type semiconductor layer formed on the electron blocking layer. | 07-10-2014 |
20140231746 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer interposed between the n-type semiconductor layer and the p-type semiconductor layer. The p-type semiconductor layer includes a first impurity region including a p-type impurity and a second impurity region including an n-type impurity. The first and second impurity regions are alternately repeated at least once. | 08-21-2014 |
20140326944 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a nitride semiconductor light emitting device includes forming a first conductivity type nitride semiconductor layer. An active layer is formed on the first conductivity type nitride semiconductor layer. A second conductivity type nitride semiconductor layer is formed on the active layer. In the forming of the active layer, quantum well layers and quantum barrier layers are alternatively stacked and at least two dopant layers are formed inside of at least one of the quantum well layers. The dopant layers are doped with a dopant in a predetermined concentration. | 11-06-2014 |
20150048394 | LIGHT EMITTING DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A light emitting device package includes a body including a lead frame part, and a light emitting laminate disposed on the body and electrically connected to the lead frame part to emit light. The light emitting laminate has a multilayer structure in which a plurality of light emitting devices are stacked. In the plurality of light emitting devices, an upper light emitting device is stacked on a lower light emitting device such that vertex portions of the upper light emitting device do not overlap and are offset from vertex portions of the lower light emitting device, and portions of the lower light emitting device are externally exposed. | 02-19-2015 |
20150221826 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE - The nitride semiconductor light emitting device includes a first conductivity-type nitride semiconductor layer, a first superlattice layer disposed on the first conductivity-type nitride semiconductor layer, a pit forming layer disposed on the first superlattice layer and having a plurality of V-shaped pits, a second superlattice layer, an active layer, and a second conductivity-type nitride semiconductor layer disposed on the active layer and filling the V-shaped pits. The second superlattice layer is disposed on the pit forming layer and has windings that have the same shape as a shape of windings generated by the V-shaped pits. The active layer is disposed on the second superlattice layer and has windings that have the same shape as the shape of the windings generated by the V-shaped pits. | 08-06-2015 |
Patent application number | Description | Published |
20090020817 | Semiconductor device having a plurality of stacked transistors and method of fabricating the same - A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line. A metal node plug may be disposed within the intermediate insulating layer and the lower insulating layer to contact the source region of the upper channel body pattern. Example embodiments also relate to a method of fabricating the above semiconductor device. | 01-22-2009 |
20100254191 | SEMICONDUCTOR MEMORY DEVICE COMPRISING THREE-DIMENSIONAL MEMORY CELL ARRAY - A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string. | 10-07-2010 |
20110012189 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes stacked-gate structures including a plurality of cell gate patterns and insulating patterns alternately stacked on a semiconductor substrate and extending in a first direction. Active patterns and gate dielectric patterns are disposed in the stacked-gate structures. The active patterns penetrate the stacked-gate structures and are spaced apart from each other in a second direction intersecting the first direction, and the gate dielectric patterns are interposed between the cell gate patterns and the active patterns and extend onto upper and lower surfaces of the cell gate patterns. The active patterns share the cell gate patterns in the stacked-gate structures. | 01-20-2011 |
20110014754 | Semiconductor device having a plurality of stacked transistors and method of fabricating the same - A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line. A metal node plug may be disposed within the intermediate insulating layer and the lower insulating layer to contact the source region of the upper channel body pattern. Example embodiments also relate to a method of fabricating the above semiconductor device. | 01-20-2011 |
20110147801 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds. | 06-23-2011 |
20110284943 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: a plurality of conductive patterns stacked on a substrate and spaced apart from each other and a pad pattern including a flat portion extending in a first direction parallel to the substrate from one end of any one of the plurality of conductive patterns, and a landing sidewall portion extending upward from a top surface of the flat portion, wherein a width of a portion of the landing sidewall portion in a second direction parallel to the substrate and perpendicular to the first direction is less than a width of the flat portion. | 11-24-2011 |
20110291172 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate doped with a first conductive type dopant, a plurality of stacked structures arranged side by side on the substrate and extending in a first direction, each of the stacked structures including gate electrodes spaced apart from each other, the plurality of stacked structures including a pair of stacked structures spaced apart from each other at a first interval in a second direction perpendicular to the first direction, and a pick-up region extending in the first direction in the substrate between the pair of stacked structures and doped with the first conductive type dopant. | 12-01-2011 |
20120061744 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES - Three dimensional semiconductor memory devices are provided. The three dimensional semiconductor memory device includes a first stacked structure and a second stacked structure sequentially stacked on a substrate. The first stacked structure includes first insulating patterns and first gate patterns which are alternately and repeatedly stacked on a substrate, and the second stacked structure includes second insulating patterns and second gate patterns which are alternately and repeatedly stacked on the first stacked structure. A plurality of first vertical active patterns penetrate the first stacked structure, and a plurality of second vertical active patterns penetrate the second stacked structure. The number of the first vertical active patterns is greater than the number of the second vertical active patterns. | 03-15-2012 |
20120077320 | MANUFACTURING SEMICONDUCTOR DEVICES - A semiconductor device includes a semiconductor pattern on a substrate, gate structures on sidewalls of the semiconductor pattern, the gate structures being spaced apart from one another, insulating interlayers among the gate structures, wherein an uppermost insulating interlayer is lower than an upper face of the semiconductor pattern, a common source line contacting the substrate and protruding above the uppermost insulating interlayer, an etch stop layer pattern on the semiconductor pattern and on the common source line wherein the common source line protrudes above the uppermost insulating interlayer, an additional insulating interlayer on the uppermost insulating interlayer, and contact plugs extending through the additional insulating interlayer so as to make contact with the semiconductor pattern and the common source line, respectively. | 03-29-2012 |
20120098050 | Three-Dimensional Semiconductor Devices - Three-dimensional semiconductor devices may be provided. The devices may include a stack-structure including gate patterns and an insulation pattern. The stack-structure may further include a first portion and a second portion, and the second portion of the stack-structure may have a narrower width than the first portion. The devices may also include an active pattern that penetrates the stack-structure. The devices may further include a common source region adjacent the stack-structure. The devices may additionally include a strapping contact plug on the common source region. | 04-26-2012 |
20120108048 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A method of fabricating a three-dimensional semiconductor memory device includes providing a substrate which includes a cell array region and a peripheral region. The method further includes a peripheral structure on the peripheral region of the substrate, where the peripheral structure includes peripheral circuits and is configured to expose the cell array region of the substrate. The method further includes forming a lower cell structure on the cell array region of the substrate, forming an insulating layer to cover the peripheral structure and the lower cell structure on the substrate, planarizing the insulating layer using top surfaces of the peripheral structure and the lower cell structure as a planarization stop layer, and forming an upper cell structure on the lower cell structure. | 05-03-2012 |
20120193705 | VERTICAL NONVOLATILE MEMORY DEVICES HAVING REFERENCE FEATURES - A memory device includes a substrate having a cell array region defined therein. A dummy structure is disposed on or in the substrate near a boundary of the cell array region. The memory device also includes a vertical channel region disposed on the substrate in the cell array region. The memory device further includes a plurality of vertically stacked conductive gate lines with insulating layers interposed therebetween, the conductive gate lines and interposed insulating layers disposed laterally adjacent the vertical channel region and extending across the dummy structure, at least an uppermost one of the conductive gate lines and insulating layers having a surface variation at the crossing of the dummy structure configured to serve as a reference feature. The dummy structure may include a trench, and the surface variation may include an indentation overlying the trench. | 08-02-2012 |
20120322252 | SEMICONDUCTOR MEMORY DEVICE COMPRISING THREE-DIMENSIONAL MEMORY CELL ARRAY - A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string. | 12-20-2012 |
20130109148 | METHODS OF FORMING A PATTERN AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME | 05-02-2013 |
20140048873 | SEMICONDUCTOR DEVICES - A semiconductor device includes a semiconductor pattern on a substrate, gate structures on sidewalls of the semiconductor pattern, the gate structures being spaced apart from one another, insulating interlayers among the gate structures, wherein an uppermost insulating interlayer is lower than an upper face of the semiconductor pattern, a common source line contacting the substrate and protruding above the uppermost insulating interlayer, an etch stop layer pattern on the semiconductor pattern and on the common source line wherein the common source line protrudes above the uppermost insulating interlayer, an additional insulating interlayer on the uppermost insulating interlayer, and contact plugs extending through the additional insulating interlayer so as to make contact with the semiconductor pattern and the common source line, respectively. | 02-20-2014 |
20140248766 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds. | 09-04-2014 |
Patent application number | Description | Published |
20110014254 | UV-BLOCKING COSMETICS PREPARED BY BEING IMPREGNATED WITH URETHANE FOAM - The present invention relates to a cosmetic product comprising a UV-blocking W/O or O/W composition of low viscosity packaged in a compact-type container. More specifically, the invention relates to a UV-blocking cosmetic product prepared by impregnating a UV-blocking W/O or O/W cosmetic composition of low viscosity into expanded urethane foam, preparing a compact formulation from the expanded urethane foam impregnated with the composition, and then packaging the compact formulation in a cosmetic container. Thus, the UV-blocking cosmetic product is convenient for the user to carry and use and also has a skin-cooling effect. | 01-20-2011 |
20130045258 | COSMETIC PRODUCT COMPRISING UV-BLOCKING COSMETIC COMPOSITION IMPREGNATED INTO EXPANDED URETHANE FOAM - The present invention relates to a cosmetic product comprising a UV-blocking W/O or O/W composition of low viscosity packaged in a compact-type container. More specifically, the invention relates to a UV-blocking cosmetic product prepared by impregnating a UV-blocking W/O or O/W cosmetic composition of low viscosity into expanded urethane foam, preparing a compact formulation from the expanded urethane foam impregnated with the composition, and then packaging the compact formulation in a cosmetic container. Thus, the UV-blocking cosmetic product is convenient for the user to carry and use and also has a skin-cooling effect. | 02-21-2013 |
20130045259 | COSMETIC PRODUCT COMPRISING UV-BLOCKING COSMETIC COMPOSITION IMPREGNATED INTO EXPANDED URETHANE FOAM - The present invention relates to a cosmetic product comprising a UV-blocking W/O or O/W composition of low viscosity packaged in a compact-type container. More specifically, the invention relates to a UV-blocking cosmetic product prepared by impregnating a UV-blocking W/O or O/W cosmetic composition of low viscosity into expanded urethane foam, preparing a compact formulation from the expanded urethane foam impregnated with the composition, and then packaging the compact formulation in a cosmetic container. Thus, the UV-blocking cosmetic product is convenient for the user to carry and use and also has a skin-cooling effect. | 02-21-2013 |
20130243714 | COSMETIC MAKEUP COMPOSITION HAVING AN EXCELLENT MOISTURE-SUSTAINING CAPABILITY - The present invention relates to a cosmetic makeup composition having an excellent moisture-sustaining capability, and more particularly, to a cosmetic makeup composition for providing instant moistening and moisture-sustaining capabilities when coated on the skin by stabilizing a large amount of polyol using at least one element selected from the emulsifying-agent group consisting of branched-type polyglycerine-modified dimethicones and cross-linked polymer-type polyglycerine-modified dimethicones. | 09-19-2013 |
Patent application number | Description | Published |
20100214569 | Semiconductor Apparatus Including Alignment Tool - Provided is a semiconductor apparatus. The semiconductor apparatus includes a reference grating and a plurality of detectors. The reference grating diffracts an optical signal generated by being reflected from the alignment grating of a substrate to diffraction beams with different orders. The plurality of detectors measure intensities of a plurality of diffraction beams selected from the diffraction beams, respectively. | 08-26-2010 |
20110224945 | METHOD OF PERFORMING ETCH PROXIMITY CORRECTION, METHOD OF FORMING PHOTOMASK LAYOUT USING THE METHOD, COMPUTER-READABLE RECORDING MEDIUM STORING PROGRAMMED INSTRUCTIONS FOR EXECUTING THE METHOD, AND MASK IMAGING SYSTEM - A method of performing etch proximity correction, taking into account an orientation-dependent component, includes providing a layout, selecting a target point on an edge of the layout, defining a proximity range from the target point, defining a probability function including a distance-dependent component, an orientation-dependent component, or both a distance-dependent component and an orientation-dependent component with respect to the proximity range, and calculating a surface integral of the probability function over the proximity range. | 09-15-2011 |
20110265048 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE BY USING UNIFORM OPTICAL PROXIMITY CORRECTION - A method of manufacturing a semiconductor device includes dividing a design pattern layout into a repetitive pattern part and a non-repetitive pattern part, obtaining an optical proximity correction (OPC) bias from an extracted portion, the extracted portion being a partial portion of the repetitive pattern part, applying the OPC bias obtained from the extracted portion equally to the extracted portion and other portions of the repetitive pattern part so as to form a first corrected layout in which corrected layouts of the other portions are the same as that of the extracted portion, and forming a photomask in all portions of the repetitive pattern part according to the first corrected layout. | 10-27-2011 |
20120188543 | METHOD AND APPARATUS FOR MEASURING OVERLAY - A method of measuring an overlay includes generating an original signal using first and second overlay measurement keys that are spaced apart from each other, generating a first spectrum signal by performing Fourier transform of the original signal, generating a second spectrum signal by filtering the first spectrum signal, and generating a corrected signal by performing inverse Fourier transform of the second spectrum signal. | 07-26-2012 |
20120201447 | Methods And Apparatuses For Correcting A Mask Layout - Methods of correcting a mask layout are provided. The methods may include acquiring two-dimensional (2D) geometry information of a mask pattern. The methods may further include acquiring an After Development Inspection (ADI) image parameter of the mask pattern. The methods may additionally include calculating an etch skew using the 2D geometry information and the ADI image parameter. | 08-09-2012 |
20120208111 | METHOD OF MANUFACTURING PHOTO-MASK - Provided is a method of manufacturing a photo-mask having a micro pattern. The method includes providing an analyzing design layout, dividing the analyzing design layout into a two-dimensionally repeated portion, a one-dimensionally repeated portion, and a non-repeated portion, forming a first corrected layout by performing optical proximity correction (OPC) in the two-dimensionally repeated portion, forming a second corrected layout, taking account of the first corrected layout, by performing OPC in the one-dimensionally repeated portion, forming a third corrected layout, taking account of the first corrected layout and the second corrected layout, by performing OPC in the non-repeated portion, and forming a photo-mask based on the first through third corrected layouts. | 08-16-2012 |
20130219349 | METHOD FOR PROCESS PROXIMITY CORRECTION - A method for process proximity correction may include obtaining a point spread function (PSF) from test patterns, the test patterns including an etching process performed thereon, generating a target layout with polygonal patterns, dividing the target layout into grid cells, generating a density map including long-range layout densities, each of the long-range layout densities being obtained from the polygonal patterns located within a corresponding one of the grid cells, performing a convolution of the long-range layout densities with the PSF to obtain long-range etch skews for the grid cells, and generating an etch bias model including short-range etch skews and the long-range etch skews, each of the short-range etch skews being obtained from a neighboring region of a target pattern selected from the polygonal patterns in each of the grid cells. | 08-22-2013 |
20130219351 | METHOD OF DESIGNING A PHOTO MASK LAYOUT - A method of designing a photo mask layout may include selecting a target pattern from polygonal patterns in a layout, setting a reference point on the target pattern, obtaining a target raster at the reference point, and comparing the target raster with a hot-spot raster to determine whether the target pattern corresponds to a failure pattern. | 08-22-2013 |
Patent application number | Description | Published |
20090309767 | EXTENDIBLE KEYPAD MODULE AND MOBILE TERMINAL HAVING THE SAME - An extendible keypad module and a mobile terminal having the same are provided. The keypad module includes a plurality of key supports for mounting keys; a guide unit for housing the plurality of key supports; a driver for moving to the inside and the outside of the guide unit at one side of the guide unit; and a link for connecting the driver and the plurality of key supports, wherein gaps between the plurality of key supports are changed by movement of the driver. Thereby, when using a mobile terminal, gaps between keys can be widened and thus the keys can be more conveniently input. Further, by adjusting locations of coupling protrusions formed in a link, gaps between the keys can be adjusted. | 12-17-2009 |
20100016042 | SLIDING-TYPE PORTABLE COMMUNICATION DEVICE - A sliding-type portable communication device is provided. The sliding-type portable communication device includes a first housing, a second housing slidably engaged with the first housing, face to face, and first and second sliding cover portions at both sides of the first housing, for sliding from both sides of the first housing, while sliding the second housing, thereby widening or narrowing the first housing. | 01-21-2010 |
20100087233 | EXTENDABLE SLIDING MODULE AND MOBILE TERMINAL HAVING THE SAME - An extendable sliding module is disclosed, including a main body, a plurality of plates disposed at an upper part thereof and movable in a longitudinal direction thereof, a guide groove formed in at least one of opposite side surfaces of the main body and extending in the longitudinal direction thereof, and a hinge having one side slidably housed in the guide groove and the other side attached to the plurality of plates, and being extendable and retractable by a sliding movement between a first retracted state in which the plurality of plates are disposed to contact each other in the longitudinal direction of the main body and a second extended state in which the plurality of plates are disposed at a predetermined separation from each other. | 04-08-2010 |
Patent application number | Description | Published |
20140351446 | ELECTRONIC DEVICE USING LOGICAL CHANNELS FOR COMMUNICATION - An apparatus and method for providing one or more protocols for one or more electronic devices are provided. The method includes establishing, by an electronic device configured to provide a framework interface by executing instructions stored in a memory, one or more physical channels with an external electronic device, using one or more communication modules, executing, by the electronic device, two or more application programs to interface with the framework interface, and communicating, via the framework interface, data from the two or more application programs through the one or more physical channels to the external electronic device, using at least one logical channel or session for a respective one of the two or more application programs. | 11-27-2014 |
20140351832 | ELECTRONIC DEVICE USING FRAMEWORK INTERFACE FOR COMMUNICATION - An apparatus and method for providing one or more protocols for one or more electronic devices are provided. The method includes establishing, by an electronic device configured to provide a framework interface by executing instructions stored in a memory, one or more physical channels with an external electronic device, using one or more communication modules, executing, by the electronic device, two or more application programs to interface with the framework interface, and communicating, via the framework interface, data from the two or more application programs through the one or more physical channels to the external electronic device, using at least one logical channel or session for a respective one of the two or more application programs. | 11-27-2014 |
Patent application number | Description | Published |
20150092138 | LIQUID CRYSTAL DISPLAY - A liquid crystal display includes a display substrate, an opposite substrate, a liquid crystal layer, a main spacer, and a sub-spacer. The display substrate includes a plurality of pixel areas and a light blocking area, and at least one thin film transistor is disposed in the light blocking area. The opposite substrate is coupled to the display substrate. The liquid crystal layer is disposed between the display substrate and the opposite substrate. The main spacer is disposed on the display substrate, includes a light blocking material, and makes contact with the opposite substrate to maintain a cell gap between the display substrate and the opposite substrate. The sub-spacer is disposed on the display substrate, includes the light blocking material, and is spaced apart from the opposite substrate. The sub-spacer has a size corresponding to the light blocking area, and the main spacer is protruded from the sub-spacer. | 04-02-2015 |
20150103296 | LIQUID CRYSTAL DISPLAY - A liquid crystal display includes a display substrate, an opposite substrate coupled to and facing the display substrate, and a liquid crystal layer disposed between the display substrate and the opposite substrate. The display substrate includes a gate line extending in a first direction, a data line extending in a second direction crossing the first direction, a shielding electrode disposed along the data line covering the data line, a protruding electrode extending from the shielding electrode partially covering the gate line, and a pixel electrode electrically insulated from the shielding electrode and configured to receive a signal from the gate and data lines. | 04-16-2015 |
20150234224 | LIQUID CRYSTAL DISPLAY DEVICE - Provided is an LCD device including a first substrate, a second substrate, a liquid crystal layer, a main spacer, and a supplementary spacer. The liquid crystal layer is interposed between the first and second substrates. The main spacer makes contact with the first and second substrates. The supplementary spacer makes contact with one of the first and second substrates and is spaced apart from the other. A first area ratio defined by dividing the area of a first top surface by that of a first bottom surface of the main spacer may be smaller than a second area ratio defined by dividing the area of a second top surface by that of a second bottom surface of the supplementary spacer. | 08-20-2015 |
Patent application number | Description | Published |
20100118236 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a display device and a method for manufacturing the display device. The display device includes at least one partition formed on a lower display panel. A color filter may fill a region defined by the partitions. A first upper passivation layer is formed on the color filter, and a second upper passivation layer is formed on the first upper passivation layer and the partitions such that the LCD structure is planarized. In the display device, the height of the partition is sufficiently high to prevent mixing of the colors of neighboring pixel filters, and the process margin of the spacer and the light blocking member may be ensured. The partitions can be formed with multiple layers having different widths such that the mixture of colors between the neighboring pixels may be prevented, and the color reproducibility may be increased. | 05-13-2010 |
20100141875 | LIQUID CRYSTAL DISPLAY, PANEL THEREFOR, AND MANUFACTURING METHOD THEREOF - A display panel includes a substrate, a partition formed on the substrate and defining a plurality of openings, a plurality of color filters formed in the openings and having a substantially uniform thickness within each respective opening, and a spacer formed on the partition. The color filters and the spacer are formed through inkjet printing. The color filters have the substantially uniform thickness by the partition having a height which is greater than the thickness of the color filters during the inkjet printing. The height of the partition may be in a range of about 1.5 to about 2 times the thickness of the color filter. | 06-10-2010 |
20100157235 | LIQUID CRYSTAL DISPLAY - A liquid crystal display according to an exemplary embodiment of the present invention includes: a substrate; a partition formed on the substrate and defining a pixel; a plurality of protrusion members formed with the same material as the partition on the substrate, and disposed with a linear plane shape inside the pixel defined by the partition; and a color filter filled inside the pixel defined by the partition. Accordingly, in the liquid crystal display according to an exemplary embodiment of the present invention, a plurality of transparent protrusion members are formed in the pixel defined by the partition such that movement of color filter ink dripped through an Inkjet method is controlled such that a color filter may be planarized on the whole surface of the pixel. | 06-24-2010 |
20100309241 | METHOD FOR INKJET PRINTING - A method for inkjet printing includes providing a light blocking member pattern including a plurality of openings at positions corresponding to pixels, dripping a dummy ink drop on the light blocking member pattern by using an inkjet printer, providing a CCD (charge-coupled device) image for the dripped dummy ink drop, representing the CCD image on rectangular coordinates, calculating a central point under an x-axis and a y-axis of the CCD image, calculating an escape value as a deviation of the central point under the x-axis and the y-axis in the CCD image from a reference point established by the inkjet printer, calculating a time adjustment value of the ink drip based on the escape value, and controlling the time for the ink drip for each nozzle of the inkjet printer by the time adjustment value of the ink drip. | 12-09-2010 |
20110019140 | LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF - A display panel according to the present invention includes a first insulating substrate with a gate line and a data line formed thereon. A thin film transistor is connected to the gate line and the data line and a partition is formed according to the gate line and the data line defining a color filter filling region. Color filter is formed as a convex shape since both circumferences of upper portion and lower portion of the partition are larger than that of center portion. A color filter is formed in the filling region. A passivation layer is formed on the color filter and the partition and a pixel electrode on the passivation layer connected to the thin film transistor through a contact hole punching the passivation layer and the color filter. | 01-27-2011 |
20110180798 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A display substrate includes a transistor, a black matrix and a color spacer. The transistor is connected to a gate line, and a data line crossing the gate line. The black matrix includes a first light-blocking portion covering the gate line and the data line, and a second light-blocking portion covering a channel of the transistor. The second light-blocking portion has a thickness which is smaller than a thickness of the first light-blocking portion. The color spacer is disposed on the second light-blocking portion. | 07-28-2011 |
20120249937 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a display device and a method for manufacturing the display device. The display device includes at least one partition formed on a lower display panel. A color filter may fill a region defined by the partitions. A first upper passivation layer is formed on the color filter, and a second upper passivation layer is formed on the first upper passivation layer and the partitions such that the LCD structure is planarized. In the display device, the height of the partition is sufficiently high to prevent mixing of the colors of neighboring pixel filters, and the process margin of the spacer and the light blocking member may be ensured. The partitions can be formed with multiple layers having different widths such that the mixture of colors between the neighboring pixels may be prevented, and the color reproducibility may be increased. | 10-04-2012 |
20130252352 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A display substrate includes a transistor, a black matrix and a color spacer. The transistor is connected to a gate line, and a data line crossing the gate line. The black matrix includes a first light-blocking portion covering the gate line and the data line, and a second light-blocking portion covering a channel of the transistor. The second light-blocking portion has a thickness which is smaller than a thickness of the first light-blocking portion. The color spacer is disposed on the second light-blocking portion. | 09-26-2013 |
20130314652 | DISPLAY SUBSTRATE, METHOD OF MANUFACTURING THE DISPLAY SUBSTRATE AND DISPLAY PANEL HAVING THE DISPLAY SUBSTRATE - A method of manufacturing a display substrate includes forming a first color filter on a base substrate in a first region, forming a second color filter on the base substrate in a second region, forming an organic layer on the base substrate, the first color filter and the second color filter, forming a third color filter on the organic layer in a third region and forming an overcoat layer on the organic layer and the third color filter. | 11-28-2013 |
20140002903 | DISPLAY PANEL HAVING ANTI-STATIC FEATURE AND METHOD FOR MANUFACTURING THE SAME | 01-02-2014 |
20140045102 | MASK AND METHOD OF MANUFACTURING A SUBSTRATE USING THE MASK - A mask includes a substantially transparent portion. The mask further includes a halftone portion abutting the substantially transparent portion, a light transmittance of the halftone portion being greater than 0% and less than 100%. The mask further includes a blocking portion abutting the halftone portion, a light transmittance of the blocking portion being less than the light transmittance of the halftone portion | 02-13-2014 |
20140065542 | PHOTORESIST COMPOSITION AND METHOD OF FORMING A BLACK MATRIX USING THE SAME - A photoresist composition includes a binder resin combined with a black dye, a monomer, a photo-polymerization initiator and a remainder of a solvent. | 03-06-2014 |
20140141685 | LIQUID CRYSTAL DISPLAY, PANEL THEREFOR, AND MANUFACTURING METHOD THEREOF - A display panel includes a substrate, a partition formed on the substrate and defining a plurality of openings, a plurality of color filters formed in the openings and having a substantially uniform thickness within each respective opening, and a spacer formed on the partition. The color filters and the spacer are formed through inkjet printing. The color filters have the substantially uniform thickness by the partition having a height which is greater than the thickness of the color filters during the inkjet printing. The height of the partition may be in a range of about 1.5 to about 2 times the thickness of the color filter. | 05-22-2014 |
20150077688 | LIQUID CRYSTAL DISPLAY - A liquid crystal display is provided. The liquid crystal display includes a first substrate, and a first electrode and a second electrode formed overlapping with each other on the first substrate, wherein a first insulating layer is disposed between the first electrode and the second electrode. The liquid crystal display further includes a light blocking member formed on the second electrode, a first spacer and a second spacer formed on the light blocking member, and a second substrate facing the first substrate. | 03-19-2015 |
20150131018 | LIQUID CRYSTAL DISPLAY DEVICE INCLUDING CONDUCTIVE SPACER - A liquid crystal display device includes a first substrate, a thin film transistor on the first substrate, a first electrode on the first substrate and connected to the thin film transistor, a second substrate facing the first substrate, color filters on the first substrate or the second substrate, a black matrix between the color filters on the first substrate or the second substrate, a second electrode spaced apart from the first electrode and on the first substrate or the second substrate, a second electrode conductive line on the black matrix, a spacer which is between the first substrate and the second substrate and supports the first substrate and the second substrate, and a liquid crystal layer between the first substrate and the second substrate. The spacer is electrically connected to the second electrode and the second electrode conductive line. | 05-14-2015 |