Patent application number | Description | Published |
20090017325 | ROLLED COPPER FOIL - A rolled copper foil according to the present invention includes a crystal grain alignment wherein: when normalized intensity of {200} | 01-15-2009 |
20090173414 | Rolled Copper Foil and Manufacturing Method of Rolled Copper Foil - A rolled copper foil, according to the present invention, obtained after a final cold rolling step but before recrystallization annealing includes a group of crystal grains which exhibits four-fold symmetry in results obtained by X-ray diffraction (XRD) pole figure measurement with respect to a rolled surface. In the XRD pole figure measurement, at least four peaks of a {220} | 07-09-2009 |
20100037996 | COPPER ALLOY MATERIAL AND METHOD OF MAKING SAME - A copper alloy material having: 1.0 to 5.0 mass % of Ni; 0.2 to 1.0 mass % of Si; 1.0 to 5.0 mass % of Zn; 0.1 to 0.5 mass % of Sn; 0.003 to 0.3 mass % of P; and the balance consisting of Cu and an unavoidable impurity. The mass ratio between Ni and each of Si, Zn and Sn is to be Ni/Si=4 to 6, Zn/Ni=0.5 or more, and Sn/Ni=0.05 to 0.2. | 02-18-2010 |
20100224292 | Copper alloy material and a method for fabricating the same - A copper alloy material has a rolled surface having a plurality of crystal faces parallel to the rolled surface. The crystal faces includes at least one crystal face selected from a group consisted of {011}, {1nn} (n is an integer, n≧1), {11m} (m is an integer, m≧1), {023}, {012}, and {135}. Diffraction intensities of the crystal faces in an inverse pole figure obtained by crystal diffraction measurement of the rolled surface as a reference satisfy the relationships of: | 09-09-2010 |
20100291402 | ROLLED COPPER FOIL AND MANUFACTURING METHOD THEREOF - A rolled copper foil applied with a recrystallization annealing after a final cold rolling step and having a crystal grain alignment satisfying a ratio of [a]/[b]≧3, where [a] and [b] are normalized average intensities of a {111} | 11-18-2010 |
20100319818 | Method for fabricating a copper alloy and copper alloy fabricated by the same - A method for fabricating a copper alloy. Cu and Cr, Zr, and Sn to be doped to the Cu are melt to cast a copper alloy material. Hot working is carried out on the copper alloy material to form a plate material having a rolled texture. Heat treatment is carried out on the plate material. Cold rolling with workability of 80% or more and less than 90% is carried out on the plate material after the heat treatment to form an intermediate plate material. Aging treatment is carried out on the intermediate plate material. Another cold rolling with workability of 20% to 40% is carried out as finish rolling on the intermediate plate material after the aging treatment step. The intermediate plate material after the finish rolling step is heated as stress relief annealing. | 12-23-2010 |
Patent application number | Description | Published |
20110209167 | PROGRAM GUIDE DISTRIBUTION APPARATUS, PROGRAM TRANSMISSION APPARATUS, PROGRAM GUIDE RECEPTION TERMINAL, PROGRAM GUIDE TRANSMISSION/RECEPTION SYSTEM, PROGRAM GUIDE DISTRIBUTION METHOD, PROGRAM GUIDE RECEPTION METHOD, PROGRAM, AND RECORDING MEDIUM - Provided is a program guide distribution apparatus in which the user does not particularly have to consciously perform searching, and the user can naturally recognize a forgot-to-view program in a daily act of viewing TV broadcast or TV guide. The program guide distribution apparatus includes: a related program decision unit that compares distributable programs which were broadcasted and which can be distributed, with programs which exist in a program guide of broadcast, and decides whether programs related to each other exist; a display information providing unit that provides a display indicative of the existence of the related program among the distributable programs to the program guide, when the related programs exists; and a program guide information distribution unit that distributes information of the program guide. | 08-25-2011 |
20120030697 | DISPLAY CONTROL APARATUS, DISPLAY CONTROL METHOD, PROGRAM, AND RECORDING MEDIUM - In the conventional program recommend method, there is a problem that the user misses to view a program being wanted to view or a problem that the information is redundant to the user. A display control apparatus of the present invention includes a preference information acquisition unit which acquires a preference information of a viewer from the broadcast reception apparatus, a program information acquisition unit which acquires the program information of a preference target program which suits the preference information, from the server, a reception apparatus state detection unit which detects an instruction of a power supply off to the broadcast reception apparatus, a program information display unit which displays at least a part of the program information, and a display control unit which controls a start of a display of the program information, on the basis of the instruction of the power supply off. | 02-02-2012 |
20130167084 | INFORMATION TERMINAL, METHOD OF CONTROLLING INFORMATION TERMINAL, AND PROGRAM FOR CONTROLLING INFORMATION TERMINAL - An information terminal includes: a display unit which displays one or more objects; a sensor unit which obtains a position of a first point and a position of a second point designated by a user on the display unit; and a control unit which selects, from among the one or more objects, at least one object displayed on a straight line determined by the first point and second point, and when the first point or the second point is moved along the straight line, moves the selected object in a direction corresponding to a direction of the movement of the first point or the second point. | 06-27-2013 |
Patent application number | Description | Published |
20120193726 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including an n-channel-type MISFET (Qn) having an Hf-containing insulating film ( | 08-02-2012 |
20130087855 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The semiconductor integrated circuit device has a hybrid substrate structure which includes both of an SOI structure and a bulk structure on the side of the device plane of a semiconductor substrate. In the device, the height of a gate electrode of an SOI type MISFET is higher than that of a gate electrode of a bulk type MISFET with respect to the device plane. | 04-11-2013 |
20130119470 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region formed of a semiconductor region surrounded by an element isolation region; and (b) an insulating layer arranged below the active region. Further, the semiconductor device includes: (c) a p-type semiconductor region arranged below the active region so as to interpose the insulating layer; and (d) an n-type semiconductor region whose conductivity type is opposite to the p-type, arranged below the p-type semiconductor region. And, the p-type semiconductor region includes a connection region extending from below the insulating layer, and the p-type semiconductor region and a gate electrode of the MISFET are connected to each other by a shared plug which is an integrally-formed conductive film extending from above the gate electrode to above the connection region. | 05-16-2013 |
20130140669 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A first MISFET which is a semiconductor element is formed on an SOI substrate. The SOI substrate includes a supporting substrate which is a base, BOX layer which is an insulating layer formed on a main surface (surface) of the supporting substrate, that is, a buried oxide film; and an SOI layer which is a semiconductor layer formed on the BOX layer. The first MISFET as a semiconductor element is formed to the SOI layer. In an isolation region, an isolation groove is formed penetrating though the SOI layer and the BOX layer so that a bottom surface of the groove is positioned in the middle of a thickness of the supporting substrate. An isolation film is buried in the isolation groove being formed. Then, an oxidation resistant film is interposed between the BOX layer and the isolation film. | 06-06-2013 |
20130187230 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. | 07-25-2013 |
20130264644 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer. | 10-10-2013 |
20140042529 | SEMICONDUCTOR DEVICE AND MANUFACTRUING METHOD OF THE SAME - A semiconductor device is manufactured by using an SOI substrate having an insulating layer on a substrate and a semiconductor layer on the insulating layer. The semiconductor device is provided with a gate electrode formed on the semiconductor layer via a gate insulating film, a sidewall spacer formed on a sidewall of the gate electrode, a semiconductor layer for source/drain that is epitaxially grown on the semiconductor layer, and a sidewall spacer formed on a sidewall of the semiconductor layer. | 02-13-2014 |
20140353756 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device using an SOI (Silicon On Insulator) substrate, capable of preventing malfunction of MISFETs (Metal Insulator Semiconductor Field Effect Transistor) and thus improving the reliability of the semiconductor device. Moreover, the parasitic resistance of the MISFETs is reduced, and the performance of the semiconductor device is improved. An epitaxial layer formed on an SOI layer above an SOI substrate is formed to have a large width so as to cover the ends of the upper surface of an isolation region adjacent to the SOI layer. By virtue of this, contact plugs of which formation positions are misaligned are prevented from being connected to a semiconductor substrate below the SOI layer. Moreover, by forming the epitaxial layer at a large width, the ends of the SOI layer therebelow are prevented from being silicided. As a result, increase in the parasitic resistance of MISFETs is prevented. | 12-04-2014 |
20150084064 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device has a gate electrode GE formed on a substrate via a gate insulating film GI and a source/drain semiconductor layer EP | 03-26-2015 |