Patent application number | Description | Published |
20080200035 | METHOD OF FORMING CONTACT HOLE OF SEMICONDUCTOR DEVICE - A method of forming a contact hole of a semiconductor device is disclosed. At the time of a hard mask formation process for forming a contact hole of a semiconductor device, first patterns are formed using a photoresist pattern employing an exposure process. Spacers having a predetermined thickness are formed on sidewalls of the first patterns using an amorphous carbon layer. Spaces between the first patterns including the spacers are gap filled to form second patterns. Accordingly, a contact hole having a pitch with exposure equipment resolution or less can be formed. | 08-21-2008 |
20080233729 | METHOD OF FORMING MICRO PATTERN IN SEMICONDUCTOR DEVICE - A method of forming a fine pattern in a semiconductor device includes forming an target layer, a hard mask layer and first sacrificial patterns on a semiconductor substrate; forming an insulating layer and a second sacrificial layer on the hard mask layer and the first sacrificial patterns; performing the first etch process so as to allow the second sacrificial layer remain on the insulating layer between the first sacrificial patterns for forming second sacrificial patterns; removing the insulating layer placed on the first sacrificial patterns and between the first and second sacrificial patterns; etch the hard mask layer through the second etch process utilizing the first and second sacrificial patterns as the etch mask to form a mask pattern; and etch the target layer through the third etch process utilizing the hard mask pattern as the etch mask. | 09-25-2008 |
20080248654 | METHOD OF FORMING A MICRO PATTERN OF A SEMICONDUCTOR DEVICE - A method of forming a micro pattern of a semiconductor device includes forming an etch target layer, a hard mask layer, a Bottom Anti-Reflective Coating (BARC) layer and a first photoresist pattern over a semiconductor substrate. An organic layer is formed on a surface of the first photoresist pattern. A second photoresist layer is formed over the BARC layer and the organic layer. An etch process is performed so that the second photoresist layer remains on the BARC layer between the first photoresist patterns and becomes a second photoresist pattern. The organic layer on the first photoresist pattern and between the first and second photoresist patterns is removed. The BARC layer formed below the organic layer is removed. The hard mask layer is etched using the first and second photoresist patterns as an etch mask. The etch target layer is etched using a hard mask pattern as an etch mask. | 10-09-2008 |
20080261389 | METHOD OF FORMING MICRO PATTERN OF SEMICONDUCTOR DEVICE - A method of forming a micro pattern of a semiconductor device method includes forming an etch target layer over a substrate, a hard mask layer over the etch target layer, and first auxiliary patterns over the etch target layer. The first auxiliary patterns defining a plurality of structures that are spaced apart from each other. Silicon is injected into the first auxiliary patterns to form silylated first auxiliary patterns. An insulating layer is formed over the hard mask layer and the silylated first auxiliary patterns, the insulating layer defining a space between two adjacent silylated first auxiliary patterns. A second auxiliary pattern is formed over the insulating layer at the space defined between the two silylated first auxiliary patterns. The insulating layer is etched to remove a portion of the insulating layer provided between the silylated first auxiliary patterns and the second auxiliary pattern while not removing a portion of the insulating layer provided below the second auxiliary pattern. The hard mask layer etched using the silylated first auxiliary patterns and the second auxiliary pattern as an etch mask to define hard mask patterns. The etch target layer is etched using the hard mask patterns to obtain target micro patterns. | 10-23-2008 |
20080268649 | METHOD OF FORMING A MICRO PATTERN IN SEMICONDUCTOR DEVICE - A method of forming a micro pattern in a semiconductor device includes forming an etching object layer and a hard mask layer on a semiconductor substrate. Cross-shaped first auxiliary patterns are formed on the hard mask layer. An insulating layer is formed on the hard mask layer including the first auxiliary pattern. A second auxiliary pattern is formed on the insulating layer between the first auxiliary patterns. An etching process is performed such that the insulating layer remains only on a lower portion of the second auxiliary pattern. The hard mask is etched through an etching process using the first and second auxiliary patterns as an etching mask to form a hard mask pattern. The etching object layer is etched using the hard mask pattern as an etching mask. | 10-30-2008 |
20080280216 | METHOD OF FORMING A HARD MASK PATTERN IN A SEMICONDUCTOR DEVICE - In a method of forming hard mask patterns in a semiconductor device, an etch mask has a pitch less than a resolution limitation of exposure equipment. The method includes forming first hard mask patterns through an exposure process utilizing photoresist patterns, forming a separation layer on a resulting structure including the first hard mask patterns, forming a second hard mask pattern in a space between the first hard mask patterns, and removing the exposed separation layer. | 11-13-2008 |
20080280431 | METHOD OF FABRICATING FLASH MEMORY DEVICE - The present invention relates to a method of fabricating a flash memory device. In a method according to an aspect of the present invention, a first hard mask film is formed over a semiconductor laminate. A plurality of first hard mask patterns are formed by etching an insulating layer for a hard mask. Spacers are formed on top surfaces and sidewalls of the plurality of first hard mask patterns. A second hard mask film is formed over a total surface including the spacers. Second hard mask patterns are formed in spaces between the spacers by performing an etch process so that a top surface of the spacers is exposed. The spacers are removed. Accordingly, gate patterns can be formed by employing hard mask patterns having a pitch of exposure equipment resolutions or less. | 11-13-2008 |
20080280444 | METHOD OF FORMING MICRO PATTERN OF SEMICONDUCTOR DEVICE - The present invention relates to a method of forming a micro pattern of a semiconductor device. In the method according to an aspect of the present invention, an etch target layer, a first hard mask layer, and insulating patterns of a lonzenge are formed over a semiconductor substrate. A first auxiliary pattern is formed on the first hard mask layer including the insulating patterns, wherein a contact hole having the same shape as that of the insulating pattern is formed at the center of four adjacent insulating patterns, which form a quadrilateral. A second auxiliary pattern is formed by etching the first auxiliary pattern so that a top surface of the insulating patterns is exposed. The exposed insulating patterns are removed. A first hard mask pattern is formed by etching the first hard mask layer using an etch process employing the second auxiliary pattern as an etch mask. The etch target layer is etched using the first hard mask pattern. | 11-13-2008 |
20090004866 | METHOD OF FORMING MICRO PATTERN OF SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a target etch layer over a substrate, a first auxiliary layer over the target etch layer, an isolation layer over the first auxiliary layer, and a second auxiliary layer over the isolation layer. A first exposure process is performed, where the first auxiliary layer is in focus and the second auxiliary layer is out of focus. A second exposure process is performed, where the second auxiliary layer in focus and the first auxiliary layer is out of focus. The second auxiliary layer is developed to form first mask patterns. The isolation layer and the first auxiliary layer are etched by using the first mask patterns to form second mask patterns. The second mask patterns are developed to form third mask patterns that are used to facilitate subsequent etching of the target etch layer. | 01-01-2009 |
20090061641 | METHOD OF FORMING A MICRO PATTERN OF A SEMICONDUCTOR DEVICE - In a method of forming micro patterns, an etch target layer, a hard mask layer, a silicon-containing bottom anti-reflective coating (BARC) layer, and first auxiliary patterns are formed over a semiconductor substrate. The silicon-containing BARC layer is etched to form silicon-containing BARC patterns. Insulating layers are formed on a surface of the silicon-containing BARC patterns and the first auxiliary patterns. A second auxiliary layer is formed on the hard mask layer and the insulating layers. An etch process is performed such that the second auxiliary layer remains on the hard mask layer between the silicon-containing BARC patterns thereby forming second auxiliary patterns. The insulating layers on the first auxiliary patterns and between the silicon-containing BARC patterns and the second auxiliary patterns are removed. The hard mask layer is etched thereby forming hard mask patterns. The etch target layer is etched using the hard mask patterns as an etch mask. | 03-05-2009 |
20090124086 | METHOD OF FABRICATING A FLASH MEMORY DEVICE - A method of fabricating a flash memory device, in which a pre-metal dielectric layer, a hard mask layer, and a first etch mask pattern are sequentially formed over a semiconductor substrate; an auxiliary layer is formed along a surface of the first etch mask pattern and the hard mask layer; and an etch mask layer is formed on the auxiliary layer to gap-fill between adjacent first etch mask pattern elements. The etch mask layer is etched to form a second etch mask pattern between adjacent first etch mask pattern elements. The auxiliary layer between the first and second etch mask patterns is removed; and a hard mask pattern is formed by etching the hard mask layer between the first etch mask pattern and the second etch mask pattern. The pre-metal dielectric layer is etched process using the hard mask pattern as a mask to form contact holes. | 05-14-2009 |
20090140398 | HARD MASK PATTERNS OF A SEMICONDUCTOR DEVICE AND A METHOD FOR FORMING THE SAME - In a method for forming hard mask patterns of a semiconductor device first hard mask patterns are formed on a semiconductor substrate. Second hard mask patterns are formed and include first patterns which are substantially perpendicular to the first hard mask patterns and second patterns which are positioned between the first hard mask patterns. Third hard mask patterns are formed between the first patterns. | 06-04-2009 |
20090142711 | METHOD OF FORMING MASK PATTERN - The present invention relates to a method of forming a mask pattern. According to the present invention, a negative photoresist layer is formed over a substrate. Some regions of the negative photoresist layer are exposed. The exposed negative photoresist layers are developed. A positive photoresist layer is formed over the substrate including negative tone working photoresist layers. The substrate is baked so that a hydrogen gas is diffused into the positive photoresist layers at boundary portions of the negative tone working photoresist layers. The positive photoresist layers into which the hydrogen gas is diffused are developed. | 06-04-2009 |
20090142932 | METHOD OF FORMING A HARD MASK PATTERN IN A SEMICONDUCTOR DEVICE - In a method of forming a hard mask pattern in a semiconductor device, only processes for forming patterns having a row directional line shape and a column directional line shape on a plane are performed so that the hard mask patterns can be formed to define densely disposed active regions. A pitch of the hard mask patterns is less than a resolution limit of an exposure apparatus. | 06-04-2009 |
20090170031 | METHOD OF FORMING A PATTERN OF A SEMICONDUCTOR DEVICE - A pattern for a gate line is formed using a first photoresist pattern and a first BARC layer. A pad and patterns for a select line, which has a width that is larger than that of the gate line, are formed using a second photoresist pattern and a second BARC layer. The gate line, the pad and the select line can be formed at a same time. | 07-02-2009 |
20090170033 | METHOD OF FORMING PATTERN OF SEMICONDUCTOR DEVICE - The present invention relates to a method of forming patterns of a semiconductor device. In aspect of the present invention, a photoresist layer is formed on a semiconductor substrate. Exposure regions are formed in the photoresist layer to which light, which corresponds to an intermediate value of a maximum intensity and a minimum intensity of the light, is irradiated by performing an exposure process. Photoresist patterns are formed by removing the exposure regions. | 07-02-2009 |
20090170310 | METHOD OF FORMING A METAL LINE OF A SEMICONDUCTOR DEVICE - In a method of forming a metal line of a semiconductor device, a dielectric film is formed on a semiconductor substrate. A plurality of parallel photoresist patterns are formed over the entire structure including the dielectric film. A spacer is formed on sidewalls of the photoresist patterns. The dielectric film is exposed by removing the photoresist patterns. Damascene patterns are formed by etching the exposed dielectric film. The spacer is removed. Metal material is formed over the entire structure including the damascene patterns and polishing the metal material, thereby forming a metal line. | 07-02-2009 |
20090170325 | METHOD OF FORMING A SEMICONDUCTOR DEVICE PATTERN - In a method of forming patterns of a semiconductor device, first etch mask patterns are formed over a semiconductor substrate. An auxiliary film is formed over the first etch mask patterns to a thickness in which a step corresponding to the first etch mask patterns can be maintained. Second etch mask patterns are formed in spaces defined by the auxiliary film between adjacent first etch mask patterns. First auxiliary film patterns are formed by removing the auxiliary film formed on the first etch mask patterns. Each first auxiliary film pattern has opposite ends projecting upwardly. The first etch mask patterns and the second etch mask patterns are removed. Second auxiliary film patterns are formed by etching between the ends of the first auxiliary film patterns such that the opposite ends of the first auxiliary film patterns are isolated from each other. | 07-02-2009 |
20090170326 | METHOD OF FORMING MICRO PATTERN OF SEMICONDUCTOR DEVICE - The present invention relates to a method of forming micro patterns of a semiconductor device. In the method according to an aspect of the present invention, first etch mask patterns having a second pitch, which is twice larger than a first pitch of target patterns, are formed in a column direction over a semiconductor substrate. An auxiliary film is formed over the semiconductor substrate including a surface of the first etch mask patterns. An etch mask film is formed over the semiconductor substrate including the auxiliary film. An etch process is performed in order to form second etch mask patterns having the second pitch in such a manner that the etch mask film, the auxiliary film, and the first etch mask patterns are isolated from one another in a row direction and the etch mask film remains between the first etch mask patterns. The auxiliary film between the first and second etch mask patterns is removed. | 07-02-2009 |
20090170330 | METHOD OF FORMING A MICRO PATTERN OF A SEMICONDUCTOR DEVICE - In a method of forming micro patterns of a semiconductor device, first etch mask patterns are formed over a semiconductor substrate. An auxiliary film is formed over the semiconductor substrate including a surface of the first etch mask patterns. Second etch mask patterns are formed between the auxiliary films formed on sidewalls of the first etch mask patterns. The first etch mask patterns and the second etch mask patterns are formed using the same material. The auxiliary films between the first and second etch mask patterns are removed. Accordingly, more micro patterns can be formed than allowed by the resolution limit of an exposure apparatus while preventing misalignment. | 07-02-2009 |
20090176377 | METHOD OF FORMING PATTERNS OF SEMICONDUCTOR DEVICE - The present invention relates to a method of forming patterns of a semiconductor device. In an aspect of the present invention, the method may include providing a semiconductor substrate, including a first area in which patterns are formed at a first interval and a second area formed wider than the first interval, forming an etch mask layer formed over the semiconductor substrate, forming photoresist patterns formed over the etch mask layer, wherein an auxiliary pattern is formed at an outermost area of the second area, forming first etch mask patterns by patterning the etch mask layer using the photoresist patterns and the auxiliary pattern, forming an auxiliary layer on the entire surface including the first etch mask patterns, forming a second etch mask pattern in concave portions of the auxiliary layer, and removing the auxiliary layer that is exposed. | 07-09-2009 |
20090286388 | METHOD OF FORMING MICRO PATTERN IN SEMICONDUCTOR DEVICE - A method of forming a micro pattern in a semiconductor device includes: forming an target layer, a hard mask layer and first sacrificial patterns over a semiconductor substrate on which a cell gate region, a selective transistor region and a periphery circuit region are defined; forming an insulating layer and a second sacrificial layer on the hard mask layer and the first sacrificial patterns; removing the insulating layer and the second sacrificial layer formed in the selective transistor region and the periphery circuit region; performing the first etch process so as to allow the second sacrificial layer formed in the cell gate region to remain on the insulating layer between the first sacrificial patterns for forming second sacrificial patterns; removing the insulating layer placed on the first sacrificial patterns and between the first and second sacrificial patterns in the cell gate region; etching the hard mask layer using the second etch process utilizing the first and second sacrificial patterns as the etch mask to form a mask pattern; and etching the target layer using the third etch process utilizing the hard mask pattern as the etch mask. | 11-19-2009 |
20100021849 | Method of Forming Patterns of Semiconductor Device - In a method of forming patterns of a semiconductor device, a semiconductor substrate defining photoresist patterns formed over a target etch layer is provided. An auxiliary layer is formed over the semiconductor substrate and the photoresist patterns. The auxiliary layer formed on a surface of the photoresist patterns is denatured into first auxiliary patterns. A photoresist film is formed over the semiconductor substrate, the first auxiliary patterns, and the auxiliary layer. The auxiliary layer formed below the photoresist film is denatured into a second auxiliary pattern. Here, the auxiliary layer remains only between the photoresist patterns. Etch mask patterns, including the photoresist patterns and the auxiliary layer, are formed by removing the photoresist film and the first and second auxiliary patterns. | 01-28-2010 |
20120146110 | SEMICONDUCTOR DEVICE AND FORMING METHOD OF THE SAME - A semiconductor device includes contact structures and conductive wires formed over the contact structures and coupled to the respective contact structures. Part of each of the conductive wires crosses the contact structure. | 06-14-2012 |
20140103547 | ALIGNMENT KEY OF SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - An alignment key of a semiconductor device includes: a material layer formed at a scribe region of a semiconductor substrate, a first dummy hole and a second dummy hole passing through the material layers, a first channel insulation layer formed inside the first dummy hole, a second channel insulation layer formed inside the second dummy hole, a first capping layer formed on a side wall of an upper portion of the first dummy hole and an upper portion of the first channel insulation layer, and a second capping layer formed on a side wall of an upper portion of the second dummy hole and an upper portion of the channel insulation layer, having a height of a lower surface portion greater than that of a lower surface portion of the first capping layer. | 04-17-2014 |