Patent application number | Description | Published |
20100163939 | TRANSISTOR DEVICE COMPRISING AN EMBEDDED SEMICONDUCTOR ALLOY HAVING AN ASYMMETRIC CONFIGURATION - In sophisticated semiconductor devices, an asymmetric transistor configuration may be obtained on the basis of a strain-inducing semiconductor alloy. To this end, strain relaxation implantation processes may be performed at the drain side according to some illustrative embodiments, while, in other cases, the deposition of the strain-inducing alloy may be performed in an asymmetric manner with respect to the drain side and the source side of the transistor. | 07-01-2010 |
20100164016 | ADJUSTING OF STRAIN CAUSED IN A TRANSISTOR CHANNEL BY SEMICONDUCTOR MATERIAL PROVIDED FOR THRESHOLD ADJUSTMENT - The threshold voltage of a sophisticated transistor may be adjusted by providing a specifically designed semiconductor alloy in the channel region of the transistor, wherein a negative effect of this semiconductor material with respect to inducing a strain component in the channel region may be reduced or over-compensated for by additionally incorporating a strain-adjusting species. For example, a carbon species may be incorporated in the channel region, the threshold voltage of which may be adjusted on the basis of a silicon/germanium alloy of a P-channel transistor. Consequently, sophisticated metal gate electrodes may be formed in an early manufacturing stage. | 07-01-2010 |
20100164020 | TRANSISTOR WITH AN EMBEDDED STRAIN-INDUCING MATERIAL HAVING A GRADUALLY SHAPED CONFIGURATION - In a transistor, a strain-inducing semiconductor alloy, such as silicon/germanium, silicon/carbon and the like, may be positioned very close to the channel region by providing gradually shaped cavities which may then be filled with the strain-inducing semiconductor alloy. For this purpose, two or more “disposable” spacer elements of different etch behavior may be used in order to define different lateral offsets at different depths of the corresponding cavities. Consequently, enhanced uniformity and, thus, reduced transistor variability may be accomplished, even for sophisticated semiconductor devices. | 07-01-2010 |
20100193881 | REDUCTION OF THICKNESS VARIATIONS OF A THRESHOLD SEMICONDUCTOR ALLOY BY REDUCING PATTERNING NON-UNIFORMITIES PRIOR TO DEPOSITING THE SEMICONDUCTOR ALLOY - The growth rate in a selective epitaxial growth process for depositing a threshold adjusting semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by performing a plasma-assisted etch process prior to performing the selective epitaxial growth process. For example, a mask layer may be patterned on the basis of the plasma-assisted etch process, thereby simultaneously providing superior device topography during the subsequent growth process. Hence, the threshold adjusting material may be deposited with enhanced thickness uniformity, thereby reducing overall threshold variability. | 08-05-2010 |
20120025315 | Transistor with Embedded Strain-Inducing Material and Dummy Gate Electrodes Positioned Adjacent to the Active Region - The uniformity of transistor characteristics may be enhanced for transistors having incorporated therein a strain-inducing semiconductor material by using appropriately positioned dummy gate electrode structures. To this end, the dummy gate electrode structures may be positioned such that these structures may connect to or may overlap with the edge of the active region, thereby preserving a portion of the initial semiconductor material of the active region at the edge thereof upon forming the corresponding cavities. | 02-02-2012 |
20120153350 | SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - Embodiments of semiconductor devices and methods for fabricating the semiconductor devices are provided. The method includes forming a cavity in a semiconductor region laterally adjacent to a gate electrode structure of a transistor. The gate electrode structure is disposed on a channel region of a first silicon-germanium alloy. A strain-inducing silicon-germanium alloy is formed in the cavity and in contact with the first silicon-germanium alloy. The strain-inducing silicon-germanium alloy includes carbon and has a composition different from the first silicon-germanium alloy. | 06-21-2012 |
20120153354 | PERFORMANCE ENHANCEMENT IN TRANSISTORS COMPRISING HIGH-K METAL GATE STACKS AND AN EMBEDDED STRESSOR BY PERFORMING A SECOND EPITAXY STEP - When forming sophisticated transistors, for instance comprising high-k metal gate electrode structures, a significant material loss of an embedded strain-inducing semiconductor material may be compensated for, or at least significantly reduced, by performing a second epitaxial growth step after the incorporation of the drain and source extension dopant species. In this manner, superior strain conditions may be achieved, while also the required drain and source dopant profile may be implemented. | 06-21-2012 |
20120164805 | FORMATION OF A CHANNEL SEMICONDUCTOR ALLOY BY FORMING A HARD MASK LAYER STACK AND APPLYING A PLASMA-BASED MASK PATTERNING PROCESS - When forming sophisticated high-k metal gate electrode structures, a threshold adjusting semiconductor alloy may be formed on the basis of selective epitaxial growth techniques and a hard mask comprising at least two hard mask layers. The hard mask may be patterned on the basis of a plasma-based etch process, thereby providing superior uniformity during the further processing upon depositing the threshold adjusting semiconductor material. In some illustrative embodiments, one hard mask layer is removed prior to actually selectively depositing the threshold adjusting semiconductor material. | 06-28-2012 |
20120196417 | Sophisticated Gate Electrode Structures Formed by Cap Layer Removal with Reduced Loss of Embedded Strain-Inducing Semiconductor Material - When forming sophisticated gate electrode structures, such as high-k metal gate electrode structures, an appropriate encapsulation may be achieved, while also undue material loss of a strain-inducing semiconductor material that is provided in one type of transistor may be avoided. To this end, the patterning of the protective spacer structure prior to depositing the strain-inducing semiconductor material may be achieved for each type of transistor on the basis of the same process flow, while, after the deposition of the strain-inducing semiconductor material, an etch stop layer may be provided so as to preserve integrity of the active regions. | 08-02-2012 |
20120211838 | Complementary Transistors Comprising High-K Metal Gate Electrode Structures and Epitaxially Formed Semiconductor Materials in the Drain and Source Areas - When forming sophisticated semiconductor devices including complementary transistors having a reduced gate length, the individual transistor characteristics may be adjusted on the basis of individually provided semiconductor alloys, such as a silicon/germanium alloy for P-channel transistors and a silicon/phosphorous semiconductor alloy for | 08-23-2012 |
20120223363 | TRANSISTOR WITH AN EMBEDDED STRAIN-INDUCING MATERIAL HAVING A GRADUALLY SHAPED CONFIGURATION - In a transistor, a strain-inducing semiconductor alloy, such as silicon/germanium, silicon/carbon and the like, may be positioned very close to the channel region by providing gradually shaped cavities which may then be filled with the strain-inducing semiconductor alloy. For this purpose, two or more “disposable” spacer elements of different etch behavior may be used in order to define different lateral offsets at different depths of the corresponding cavities. Consequently, enhanced uniformity and, thus, reduced transistor variability may be accomplished, even for sophisticated semiconductor devices. | 09-06-2012 |
20120305995 | PERFORMANCE ENHANCEMENT IN TRANSISTORS BY PROVIDING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR MATERIAL ON THE BASIS OF A SEED LAYER - In sophisticated semiconductor devices, transistors may be formed on the basis of a high-k metal gate electrode structure provided in an early manufacturing phase, wherein an efficient strain-inducing mechanism may be implemented by using an embedded strain-inducing semiconductor alloy. In order to reduce the number of lattice defects and provide enhanced etch resistivity in a critical zone, i.e., in a zone in which a threshold voltage adjusting semiconductor alloy and the strain-inducing semiconductor material are positioned in close proximity, an efficient buffer material or seed material, such as a silicon material, is incorporated, which may be accomplished during the selective epitaxial growth process. | 12-06-2012 |
20120306027 | TRANSISTORS WITH EMBEDDED STRAIN-INDUCING MATERIAL FORMED IN CAVITIES PROVIDED BY AN OXIDIZING ETCH PROCESS - When forming sophisticated semiconductor devices including transistors with sophisticated high-k metal gate electrode structures and a strain-inducing semiconductor alloy, transistor uniformity and performance may be enhanced by providing superior growth conditions during the selective epitaxial growth process. To this end, a semiconductor material may be preserved at the isolation regions in order to avoid the formation of pronounced shoulders. Furthermore, in some illustrative embodiments, additional mechanisms are implemented in order to avoid undue material loss, for instance upon removing a dielectric cap material and the like. | 12-06-2012 |
20130161695 | REDUCTION OF THICKNESS VARIATIONS OF A THRESHOLD SEMICONDUCTOR ALLOY BY REDUCING PATTERNING NON-UNIFORMITIES PRIOR TO DEPOSITING THE SEMICONDUCTOR ALLOY - The growth rate in a selective epitaxial growth process for depositing a threshold adjusting semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by performing a plasma-assisted etch process prior to performing the selective epitaxial growth process. For example, a mask layer may be patterned on the basis of the plasma-assisted etch process, thereby simultaneously providing superior device topography during the subsequent growth process. Hence, the threshold adjusting material may be deposited with enhanced thickness uniformity, thereby reducing overall threshold variability. | 06-27-2013 |
20130307090 | ADJUSTING OF STRAIN CAUSED IN A TRANSISTOR CHANNEL BY SEMICONDUCTOR MATERIAL PROVIDED FOR THE THRESHOLD ADJUSTMENT - The threshold voltage of a sophisticated transistor may be adjusted by providing a specifically designed semiconductor alloy in the channel region of the transistor, wherein a negative effect of this semiconductor material with respect to inducing a strain component in the channel region may be reduced or over-compensated for by additionally incorporating a strain-adjusting species. For example, a carbon species may be incorporated in the channel region, the threshold voltage of which may be adjusted on the basis of a silicon/germanium alloy of a P-channel transistor. Consequently, sophisticated metal gate electrodes may be formed in an early manufacturing stage. | 11-21-2013 |
Patent application number | Description | Published |
20080233715 | METHOD AND APPARATUS FOR THE LASER SCRIBING OF ULTRA LIGHTWEIGHT SEMICONDUCTOR DEVICES - A system for the laser scribing of semiconductor devices includes a laser light source operable to selectably deliver laser illumination at a first wavelength and at a second wavelength which is shorter than the first wavelength. The system further includes a support for a semiconductor device and an optical system which is operative to direct the laser illumination from the light source to the semiconductor device. The optical system includes optical elements which are compatible with the laser illumination of the first wavelength and the laser illumination of the second wavelength. In specific instances, the first wavelength is long wavelength illumination such as illumination of at least 1000 nanometers, and the second wavelength is short wavelength illumination which in specific instances is 300 nanometers or shorter. By the use of the differing wavelengths, specific layers of the semiconductor device may be scribed without damage to subjacent layers. Also disclosed are specific scribing processes. | 09-25-2008 |
20090075483 | ULTRA LIGHTWEIGHT PHOTOVOLTAIC DEVICE AND METHOD FOR ITS MANUFACTURE - An ultra lightweight semiconductor device such as a photovoltaic device is fabricated on a non-etchable barrier layer which is disposed upon an etchable substrate. The device is contacted with an appropriate etchant for a period of time sufficient to remove at least a portion of the thickness of the substrate. The barrier layer prevents damage to the photovoltaic material during the etching process. Photovoltaic devices fabricated by this method have specific power levels in excess of 300 w/kg. | 03-19-2009 |
20090298217 | METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICES ON LIGHTWEIGHT SUBSTRATES - A method for making a semiconductor device having front-surface electrical terminals in which the device is manufactured so as to include a bottom electrode, a top electrode and a semiconductor body therebetween. A first bus bar is disposed in a groove in the semiconductor body. It is in electrical communication with the bottom electrode, and includes a tab portion which projects from the device. A second bus bar is in electrical communication with the top electrode, and is disposed atop the first electrode, and electrically insulated therefrom. The tab of the first bus bar provides one terminal of the device and is folded onto the second bus bar and is electrically insulated therefrom. The second bus bar provides the second terminal of the device. | 12-03-2009 |
20100059098 | MONOLITHIC PHOTOVOLTAIC MODULE - A photovoltaic module comprised of a plurality of series connected photovoltaic cells disposed upon a substrate is fabricated utilizing thin film device techniques. A body of photovoltaic stock material comprised of an electrically conductive substrate having at least a bottom electrode layer, a body of photovoltaic material, and a top electrode layer supported thereupon is patterned so as to define a number of individual, electrically isolated photovoltaic cells and a number of electrically isolated connection zones. The connection zones are patterned to each include a portion of the bottom electrode material and are configured so that the bottom electrode material in each segment of the connection zone is exposed, and is in electrical communication with the bottom electrode portion of a particular cell. A current collecting grid structure is disposed on the top electrode of each cell and is placed in electrical communication with the bottom electrode of an adjoining cell via the electrode layer in an appropriate connection zone. In this manner, a series interconnection between the cells is established. Electrical terminals may be affixed to the module, and the finished module may be encapsulated in a body of protective materials. The substrate used in the manufacture of the module may comprise a thin, flexible layer of polymeric material and the disclosed techniques may be utilized to fabricate ultra lightweight photovoltaic modules. Also disclosed are specific module structures. | 03-11-2010 |