Patent application number | Description | Published |
20080233704 | Integrated Resistor Capacitor Structure - A resistor capacitor structure and a method of fabrication. A resistor capacitor structure provides a capacitance between at least two nodes within a microelectronic circuit. A bottom plate of the resistor capacitor structure comprises a resistance layer, which in turn provides a resistance path between an additional node within the circuit. The resistor capacitor structure may be formed on top or within interlevel dielectric layers. The resistance layer, alternatively, may be used to fill a cavity located between interlevel dielectric layers and accordingly provide a resistance path between the interlevel dielectric layers. | 09-25-2008 |
20080254590 | Fabrication process for silicon-on-insulator field effect transistors using high temperature nitrogen annealing - Disclosed is a method of fabricating a silicon-on-insulator (SOI) device that enables high device densities and mitigates variances in carrier mobility and saturation drain current (Id | 10-16-2008 |
20090065866 | Non-Planar Silicon-On-Insulator Device that Includes an "Area-Efficient" Body Tie - Non-planar SOI devices that include an “area-efficient” body tie are disclosed. The device includes a bulk substrate, an insulator layer formed on a surface of the bulk substrate, and a silicon body formed on a surface of the insulator layer. The silicon body preferably includes (i) a non-planar channel connecting a source region and a drain region, and (ii) a body tie that is adjacent to the channel and couples the channel to a voltage potential. The device further includes a gate dielectric formed on the channel and a gate material formed on the gate dielectric. | 03-12-2009 |
20100117153 | HIGH VOLTAGE SOI CMOS DEVICE AND METHOD OF MANUFACTURE - A high voltage FET and process for fabricating such an FET are provided. An extended drain and thick gate oxide device design is implemented in a basic CMOS structure to enable higher operating voltages. The basic concept of the invention is well suited for the body-tie architecture often utilized in this technology and is also applicable to other SOI processes using similar isolation schemes. | 05-13-2010 |
20100214009 | METHOD FOR DIGITAL PROGRAMMABLE OPTIMIZATION OF MIXED-SIGNAL CIRCUITS - A method for digital programmable optimization of a mixed-signal circuit is provided. The method comprises dividing up one or more transistor devices of the mixed-signal circuit into one or more transistor segments, with each transistor segment including a body tie bias terminal. Each body tie bias terminal is coupled to at least one voltage bias, either by placing each body tie bias terminal in signal communication with one or more bias nodes in the mixed-signal circuit, or by placing each body tie bias terminal in signal communication with a non-precision bias voltage source. Each body tie terminal is also arranged to be in signal communication with a separate one of one or more digital programmable storage elements. | 08-26-2010 |
20110089331 | Neutron Detector Cell Efficiency - Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production. | 04-21-2011 |
20110186940 | NEUTRON SENSOR WITH THIN INTERCONNECT STACK - A semiconductor device comprises a substrate, an active semiconductor layer situated on the substrate, a stack of interconnect layers deposited on the active semiconductor layer, and a neutron conversion layer deposited on the stack of interconnect layers, wherein the stack of interconnect layers is configured such that at least about 10% of secondary charged particles generated in the neutron conversion layer will have a sufficient ion track length in the active semiconductor layer to generate a detectable charge in the active semiconductor layer. Another semiconductor device comprises a substrate, an active semiconductor layer situated on the substrate, a neutron conversion layer deposited on the active semiconductor layer, and a stack of interconnect layers deposited on the neutron conversion layer. | 08-04-2011 |
20120228513 | NEUTRON DETECTOR CELL EFFICIENCY - Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production. | 09-13-2012 |
20130341521 | INTEGRATED COMPARATIVE RADIATION SENSITIVE CIRCUIT - This disclosure is directed to devices, integrated circuits, and methods for sensing radiation. In one example, a device includes a radiation sensitive oscillator, configured to deliver a first output signal at intervals defined by a first oscillation frequency that alters in resistance in response to radiation. The device includes a reference oscillator, configured to deliver a reference output signal at a constant reference oscillation frequency. A controller records a first instance of the count from the radiation sensitive oscillator for a duration of time defined by the count from the reference counter; compares a second instance of the count from the radiation sensitive oscillator with the first instance of the count from the radiation sensitive oscillator; and performs a selected action in response to the second instance of the count from the radiation sensitive oscillator varying from the first instance of the count from the radiation sensitive oscillator. | 12-26-2013 |
20130341522 | INTEGRATED RADIATION SENSITIVE CIRCUIT - This disclosure is directed to devices, integrated circuits, and methods for sensing radiation. In one example, a device includes an oscillator, configured to deliver a signal via an output at intervals defined by an oscillation frequency, and a counter, connected to the output of the oscillator and configured to count a number of times the comparator delivers the output signal. The oscillator includes a radiation-sensitive cell that applies a resistance. The resistance of the radiation-sensitive cell is configured to vary in response to incident radiation, wherein the oscillation frequency varies based at least in part on the resistance of the radiation-sensitive cell. | 12-26-2013 |
20140132306 | CMOS LOGIC CIRCUIT USING PASSIVE INTERNAL BODY TIE BIAS - This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor. | 05-15-2014 |
20140332922 | PROGRAMMABLE ELECTRICAL FUSE WITH TEMPERATURE GRADIENT BETWEEN ANODE AND CATHODE - In some examples, a programmable electrical fuse includes at least one structural feature that increases a thermal gradient between an anode and a cathode of the programmable electrical fuse. For example, a device may include a semiconductor substrate, an electrically insulating layer overlying the semiconductor substrate, and a programmable electrical fuse overlying a portion of the electrically insulating layer. The programmable electrical fuse may include a cathode, an anode, and a conductor link connecting the cathode and the anode. The electrically insulating layer may define a first thickness between the semiconductor substrate and the cathode and a second thickness between the semiconductor substrate and the anode, and the first thickness being less than the second thickness. | 11-13-2014 |
20150028395 | pH SENSOR WITH BONDING AGENT DISPOSED IN A PATTERN - Embodiments described herein provide for a pH sensor that comprises a substrate and an ion sensitive field effect transistor (ISFET) die. The ISFET die includes an ion sensing part that is configured to be exposed to a medium such that it outputs a signal related to the pH level of the medium. The ISFET die is bonded to the substrate with at least one composition of bonding agent material disposed between the ISFET die and the substrate. One or more strips of the at least one composition of bonding agent material is disposed between the substrate and the ISFET die in a first pattern. | 01-29-2015 |
20150028396 | pH SENSOR WITH SUBSTRATE OR BONDING LAYER CONFIGURED TO MAINTAIN PIEZORESISTANCE OF THE ISFET DIE - Embodiments described herein provide for a pH sensor that is configured for use over a pressure and temperature range. The ISFET die of the pH sensor is bonded to the substrate of the pH sensor with a bonding layer that is disposed between the substrate and the ISFET die. The pressure and temperature change across the pressure and temperature range generates an environmental force in the pH sensor. Further, the substrate or the bonding layer or both change volume over the pressure and temperature range, and the substrate or the bonding layer or both are configured such that the volume change induces a counteracting force that opposes at least a portion of the environmental force. The counteracting force is configured to maintain the change in piezoresistance of the ISFET die from the drain to the source to less than 0.5% over the pressure and temperature range. | 01-29-2015 |