Patent application number | Description | Published |
20110080374 | OPTICAL TOUCH APPARATUS, OPTICAL TOUCH DISPLAY APPARATUS, AND LIGHT SOURCE MODULE - An optical touch apparatus includes at least one light source, at least one light guide unit, at least one optical detector, and a light reducing structure. The light source is disposed beside a display area of a display and capable of providing a light beam. The light guide unit is disposed beside the display area and in a transmission path of the light beam. The light guide unit has a first surface, a second surface, and a light incident surface. The light beam is capable of entering the light guide unit through the light incident surface and being transmitted to a sensing space in front of the display area through the first surface. The optical detector is disposed beside the display area. The light reducing structure covers a portion of the first surface adjacent to the light incident surface. | 04-07-2011 |
20110128255 | LIGHT SOURCE MODULE AND OPTICAL TOUCH APPARATUS - A light source module includes a light source, a light guide unit, an opaque reflective element, a reflective unit, and a patterned light-absorbing element. The light guide unit has first and second surfaces, a light incident surface, and third and fourth surfaces. A beam from the light source enters the light guide unit through the light incident surface and is transmitted to outside through the first surface. The opaque reflective element covers a portion of the first surface adjacent to the light incident surface. The patterned light-absorbing element is disposed on a surface of the reflective unit. A portion of the patterned light-absorbing element is between a portion of the third surface adjacent to the light incident surface and the reflective unit. Another portion of the patterned light-absorbing element is between a portion of the fourth surface adjacent to the light incident surface and the reflective unit. | 06-02-2011 |
20150331170 | BACKLIGHT MODULE - A backlight module including a back plate, a light guide plate, a light source, a plastic frame, and a light conversion layer is provided. The light guide plate is disposed on the back plate and has a light incident surface and a light exit surface, wherein a first edge of the light exit surface is adjacent to the light incident surface. The light source is disposed on the back plate and faces the light incident surface. The plastic frame is disposed on the back plate and covers the first edge. The light conversion layer is disposed on the light exit surface and extends to the first edge. | 11-19-2015 |
Patent application number | Description | Published |
20110241573 | LIGHT GUIDE PLATE AND LIGHT SOURCE MODULE - A light guide plate includes a first surface, a second surface, at least a light incident surface, and a plurality of groove sets. The second surface is opposite to the first surface. The light incident surface connects the first surface and the second surface. The groove sets are separately disposed on the second surface. Each of the groove sets includes a plurality of curved grooves. Each of the curved grooves has a curved inclined reflective surface and a curved light-back-surface. The curved inclined reflective surface is inclined with respect to the first surface. The curved grooves of each of the groove sets curve towards a same curving direction. The curved inclined reflective surface of one of two curved grooves is connected to the curved light-back-surface of the other one of the two curved grooves. A backlight module is also provided. | 10-06-2011 |
20120188792 | LIGHT GUIDE PLATE AND LIGHT SOURCE MODULE - A light guide plate including a first surface, a second surface, at least one light incident surface, and a plurality of groove sets is provided. The light incident surface connects the first surface and the second surface. The groove sets are separately disposed on the second surface. Each of the groove sets includes a plurality of curved grooves. Each of the curved grooves has a curved inclined reflective surface and a curved back-to-light surface connected thereto. The curved inclined reflective surface is inclined with respect to the first surface. The curved grooves of each of the groove sets curve toward the same curving direction. The curved inclined reflective surface of one of two adjacent curved grooves is connected to the curved back-to-light surface of the other one of the two adjacent curved grooves through a connection surface. A light source module is also provided. | 07-26-2012 |
20120275190 | LIGHT GUIDE PLATE AND LIGHT SOURCE MODULE - A light guide plate (LGP) includes a first surface, a second surface, at least one light incident surface, and a plurality of micro-structure sets. The second surface is opposite to the first surface. The light incident surface connects the first surface to the second surface. The micro-structure sets are separately disposed on the second surface, and the micro-structure sets are not continuous in any direction parallel to the first surface. Each of the micro-structure sets includes at least one protrusive structure that protrudes from the second surface and at least one recessive structure that is recessed in the second surface. A light source module is also provided. | 11-01-2012 |
20140254023 | DISPLAY APPARATUS - A display apparatus including a display unit, a first reflector, a second reflector, a third reflector and a lens unit is provided. The display unit emits an image beam. The first reflector is disposed on a transmission path of the image beam. The second reflector is disposed on the transmission path of the image beam from the first reflector. The third reflector is disposed on the transmission path of the image beam from the second reflector. The lens unit is disposed on the transmission path of the image beam from the third reflector. The image beam emitted from the display unit passes through a space defined between the second reflector and the third reflector and is transmitted to the first reflector. Afterward, the image beam is sequentially reflected by the first reflector, the second reflector and the third reflector, and then passes through the lens unit. | 09-11-2014 |
20150192265 | VEHICLE HEADLIGHT DEVICE - A vehicle headlight device includes a light guide plate, a light source device and a light-pattern adjustment plate. A thickness of the light guide plate is gradually increased from a light incident side to a light reflection side, and the light reflection side is provided with a parabolic surface. The light source device is disposed to coincide with or be near a focus point of the parabolic surface. The parabolic surface reflects at least one light beam emitted from the light source device to allow the light beam to propagate in an alignment direction. The light-pattern adjustment plate has multiple grooves. The grooves are parallel to each other and arranged on a surface of the light-pattern adjustment plate facing the light guide plate, and a longitudinal direction of the grooves is different to the alignment direction. | 07-09-2015 |
Patent application number | Description | Published |
20090021292 | RELIABLE LEVEL SHIFTER OF ULTRA-HIGH VOLTAGE DEVICE USED IN LOW POWER APPLICATION - The present invention relates to integrated circuits. In particular, it relates to an IC comprising a receiving stage for receiving an input signal, an output stage for generating an output signal having a larger voltage range than the input signal and a level shifter. Embodiments of the invention provide a structure and a method for fabricating the IC wherein the level shifter is incorporated within the IC to improve reliability of the IC. | 01-22-2009 |
20120119823 | Bias Circuit with High Enablement Speed and Low Leakage Current - A circuit includes a first and a second PMOS transistor, wherein a gate of the second PMOS transistor is coupled to a gate and a drain of the first PMOS transistor; a first NMOS transistor having a drain coupled to a drain of the first PMOS transistor; and a second NMOS transistor, wherein a drain of the second NMOS transistor is coupled to a gate of the first NMOS transistor, a gate of the second NMOS transistor, and a drain of the second PMOS transistor. A first switch is coupled between the drain of the first PMOS transistor and the drain of the second PMOS transistor. A second switch is coupled between a source of the first NMOS transistor and an electrical ground. A third switch is coupled between a source of the second NMOS transistor and the electrical ground. | 05-17-2012 |
20130070519 | READ ARCHITECTURE FOR MRAM - A read architecture for reading random access memory (RAM) cells includes a multi-level sense amplifier, the multi-level sense amplifier including a plurality of sense amplifiers, each sense amplifier having a respective sense threshold and a respective sense output, and a storage module coupled to the multi-level sense amplifier for storing the sense outputs of the multi-level sense amplifier. The storage module stores a first set of sense outputs corresponding to a first read of an RAM cell and stores a second set of sense outputs corresponding to a second read of the RAM cell. The architecture also includes a decision module for comparing the first and second set of sense outputs and determining a data state of the RAM cell based on the comparison. | 03-21-2013 |
20130188418 | MAGNETORESISTIVE RANDOM ACCESS MEMORY - A magnetoresistive random access memory (MRAM) cell includes a magnetic tunnel junction (MTJ), a top electrode disposed over the MTJ, a bottom electrode disposed below the MTJ, and an induction line disposed above or below the MTJ. The induction line is configured to induce a magnetic field at the MTJ. | 07-25-2013 |
20130201754 | MRAM WITH CURRENT-BASED SELF-REFERENCED READ OPERATIONS - A magnetoresistive memory stores logic values in high and low resistance states of magnetic tunnel junction elements. Instead of comparing the resistance of elements to a fixed threshold to discern a logic state, the resistances of elements are self-compared before and after imposing a low resistance state. A measure of the resistance of an element in its unknown resistance state is stored, for example by charging a capacitor to a voltage produced when read current bias is applied. Then the element is written into its low resistance state and read current bias is applied again to develop another voltage, representing the low resistance state. A comparison circuit using current summing and an offset providing a minimum difference tolerance determines whether the resistance of the element was changed or remained the same. This determines the logic state of the element. | 08-08-2013 |
20130242676 | FAST-SWITCHING WORD LINE DRIVER - A word line driver of a semiconductor memory includes logic circuitry for coupling a word line to a first node set at a first voltage level when the word line driver is in a first state or to a second node set at a second voltage level when the word line driver is in a second state. A capacitor is configured to be charged to a third voltage level that is greater than the first and second voltage levels. First and second transistors are configured to selectively couple the word line to the capacitor and to a third node set at a fourth voltage level when the word line driver is in a third state. The fourth voltage level is greater than the first voltage level and less than the second voltage level. | 09-19-2013 |
20130265820 | ADJUSTING REFERENCE RESISTANCES IN DETERMINING MRAM RESISTANCE STATES - Magneto-resistive memory bit cells in an array have high or low resistance states storing logic values. During read operations, a bias source is coupled to an addressed memory word, coupling a parameter related to cell resistance to a sense amplifier at each bit position. The sense amplifiers determine whether the parameter value is greater or less than a reference value between the high and low resistance states. The reference value is derived by averaging or splitting a difference of resistances of reference cells at high and/or low resistance states. Bias current is conducted over address lines with varying resistance, due to different distances between the sense amplifiers and addressed memory words, which is canceled by inserting into the comparison circuit a resistance from a dummy addressing array, equal to the resistance of the conductor addressing the selected word line and bit position. | 10-10-2013 |
20130272059 | DIFFERENTIAL MRAM STRUCTURE WITH RELATIVELY REVERSED MAGNETIC TUNNEL JUNCTION ELEMENTS ENABLING WRITING USING SAME POLARITY CURRENT - A magnetoresistive memory has first and second magnetic tunnel junction (MTJ) elements operated differentially, each with a pinned magnetic layer and a free magnetic layer that can have field alignments that are parallel or anti-parallel, producing differential high and low resistance states representing a bit cell value. Writing a high resistance state to an element requires an opposite write current polarity through the pinned and free layers, and differential operation requires that the two MTJ elements be written to different resistance states. One aspect is to arrange or connect the layers in normal and reverse order relative to a current bias source, thereby achieving opposite write current polarities relative to the layers using the same current polarity relative to the current bias source. The differentially operated MTJ elements can supplement or replace single MTJ elements in a nonvolatile memory bit cell array. | 10-17-2013 |
20140064000 | Fast Bit-Line Pre-Charge Scheme - A device includes a first switch configured to control a connection between a first voltage node and a capacitor, and a second switch configured to control a connection between a common charge node and the capacitor. The device further includes a plurality of bit-lines, and a plurality of bit-line charge switches, each configured to control a connection between a respective one of the plurality of bit-lines and the common charge node. | 03-06-2014 |
20140071750 | ADAPTIVE WORD-LINE BOOST DRIVER - A word line driver circuit includes a first transistor having its gate coupled to a first node configured to receive a word line select signal. A second transistor has its gate coupled to the first node and a drain coupled to a drain of the first transistor at a second node that is coupled to a word line. A word line assist control circuit is coupled to the first node, to the word line, and to a gate of a third transistor. The word line assist control circuit is configured to turn on or turn off the third transistor to adjust a voltage of the word line. | 03-13-2014 |
20140157088 | MRAM Smart Bit Write Algorithm with Error Correction Parity Bits - Some aspects of the present disclosure relate a method. The method attempts to write an expected multi-bit word to a memory location in memory. After writing of the multi-bit word has been attempted, an actual multi-bit word is read from the memory location. The actual multi-bit word is then compared with the expected multi-bit word to identify a number of erroneous bits and a number of correct bits stored in the memory location. The number of erroneous bits is re-written to the memory location without attempting to re-write the correct bits to the memory location. | 06-05-2014 |
20140211549 | ACCOMMODATING BALANCE OF BIT LINE AND SOURCE LINE RESISTANCES IN MAGNETORESISTIVE RANDOM ACCESS MEMORY - A memory has magnetic tunnel junction elements with different resistances in different logic states, for bit positions in memory words accessed by a word line signal coupling each bit cell in the addressed word between a bit line and source line for that bit position. The bit lines and source lines are longer and shorter at different word line locations, causing a resistance body effect. A clamping transistor couples the bit line to a sensing circuit when reading, applying a current through the bit cell and producing a read voltage compared by the sensing circuit to a reference such as a comparable voltage from a reference bit cell circuit having a similar structure. A drive control varies an input to the switching transistor as a function of the word line location, e.g., by word line address, to offset the different bit and source line resistances. | 07-31-2014 |
20140266312 | Sensing Circuit with Reduced Bias Clamp - A sensing circuit having a reduced bias clamp and method of operating the sensing circuit are provided. The sensing circuit may include a reference path and a sensing path. The sensing path may include a first transistor, clamping capacitor and a pair of switches. The reference path may include a second transistor, clamping capacitor and another pair of switches. A common gain stage receiving a bias voltage charges the clamping capacitors for the respective paths in a charging mode. The clamping capacitors may be charged in a serial or partially parallel manner during the charging mode. Each path may be coupled to a comparator, which may sense current or voltage changes between the paths during a sense mode. The sensing circuit may be configured to provide for sensing current or voltage changes between multiple sensing and/or reference paths in a parallel or serial manner. | 09-18-2014 |
20140269030 | METHOD AND APPARATUS FOR MRAM SENSE REFERENCE TRIMMING - A trimming process for setting a reference current used in operating an MRAM module comprising an operational MRAM cell coupled to a bit line, multiple reference MRAM cells coupled to a reference bit line, and a sense amplifier coupled to the bit line and the reference bit line is disclosed in some embodiments. The process includes applying a bit line reference voltage to the reference bit line to provide a reference cell current formed by a sum of respective currents through the plurality of reference MRAM cells. The reference cell current is detected. A determination is made as to whether the detected reference cell current differs from a target reference cell current. The bit line reference voltage is varied, or a sensing ratio of the sense amplifier is varied, if it is determined that the detected reference cell current differs from the target reference cell current. | 09-18-2014 |
20150063048 | Sample-and-Hold Current Sense Amplifier and Related Method - A device includes an amplifier and a first switched current sampler. The first switched current sampler includes a first transistor, a first capacitor, and first, second, and third switches. The first capacitor has a first terminal electrically connected to a gate electrode of the first transistor, and a second terminal electrically connected to a source electrode of the first transistor. The first switch has a first terminal electrically connected to a first current source, and a second terminal electrically connected to the gate electrode of the first transistor. The second switch has a first terminal electrically connected to the first current source, and a second terminal electrically connected to a drain electrode of the first transistor. The third switch has a first terminal electrically connected to the drain electrode of the first transistor, and a second terminal electrically connected to a first input terminal of the amplifier. | 03-05-2015 |
20150187721 | PACKAGE WITH MULTIPLE PLANE I/O STRUCTURE - A embodiment package includes a three dimensional integrated circuit (3D IC) with first input/output pads on a first side and second input/output pads on a second side, a first fan out structure electrically coupled to the first input/output pads on the first side of the three dimensional integrated circuit, and a second fan out structure electrically coupled to the second input/output pads on the second side of the three dimensional integrated circuit. | 07-02-2015 |
20150234403 | LOW-DROPOUT REGULATOR - A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes. | 08-20-2015 |
20150294696 | STABILIZING CIRCUIT - A stabilizing circuit is provided that is connected to a biased voltage. The stabilizing circuit is configured to inhibit a change in voltage of the biased voltage caused by a first change in voltage of one or more nodes that are connected to the biased voltage through a first parasitic capacitance. In some embodiments, the stabilizing circuit induces a voltage on the biased voltage through a second parasitic capacitance that changes from a first voltage level to a second voltage level during the first change in voltage such that a total change in parasitic voltage that is induced at the biased voltage during the first change in voltage is close to 0 V. | 10-15-2015 |
20150355963 | MRAM SMART BIT WRITE ALGORITHM WITH ERROR CORRECTION PARITY BITS - Some embodiments relate to a system that includes write circuitry, read circuitry, and comparison circuitry. The write circuitry is configured to attempt to write an expected multi-bit word to a memory location in a memory device. The read circuitry is configured to read an actual multi-bit word from the memory location. The comparison circuitry is configured to compare the actual multi-bit word read from the memory location with the expected multi-bit word which was previously written to the memory location to distinguish between a number of erroneous bits in the actual multi-bit word and a number of correct bits in the actual multi-bit word. The write circuitry is further configured to re-write the number of erroneous bits to the memory location without attempting to re-write the number of correct bits to the memory location. | 12-10-2015 |
20160072494 | Sensing Circuit with Reduced Bias Clamp - A sensing circuit having a reduced bias clamp and method of operating the sensing circuit are provided. The sensing circuit may include a reference path and a sensing path. The sensing path may include a first transistor, clamping capacitor and a pair of switches. The reference path may include a second transistor, clamping capacitor and another pair of switches. A common gain stage receiving a bias voltage charges the clamping capacitors for the respective paths in a charging mode. The clamping capacitors may be charged in a serial or partially parallel manner during the charging mode. Each path may be coupled to a comparator, which may sense current or voltage changes between the paths during a sense mode. The sensing circuit may be configured to provide for sensing current or voltage changes between multiple sensing and/or reference paths in a parallel or serial manner. | 03-10-2016 |
Patent application number | Description | Published |
20090184730 | System and Method For Display Test - The system for display test includes a driving circuit having integrated circuit (IC) pads on the substrate and the IC pads are electrically connected to the signal lines, respectively. And the first switches are between the first test pads and the IC pads, wherein the number of the first test pads is less than the number of the IC pads. | 07-23-2009 |
20110254783 | TOUCH PANEL - A touch panel includes a plurality of driving lines, a plurality of sensing lines and a plurality of sensing units. The sensing lines are arranged intersecting with the driving lines. The sensing units are arranged in an array, and each of the sensing units is electrically coupled to a corresponding one of the driving lines and a corresponding one of the sensing lines. The driving lines or the sensing lines only pass through a single side of the touch panel. | 10-20-2011 |
20120169630 | TOUCH PANEL - A touch panel includes a substrate, scan lines, data output lines, a signal processing unit and touch sensing units. Each touch sensing unit includes a sensing electrode, a reference capacitor, an output circuit and a reset circuit. The sensing electrode is disposed in a breach of the sensing electrode. The reference capacitor, the output circuit and the reset circuit are disposed on the substrate and in the breach. The output circuit, the reset circuit, the reference capacitor and the sensing electrode are electrically coupled to a reference point. The output circuit is configured to output touch signals to the corresponding data output line. The signal processing unit is configured to obtain electric potential of the data output line and perform a corresponding processing step. When the touch sensing unit is out of working, the reference point is reset to a predetermined electric potential. | 07-05-2012 |
20120236223 | LIQUID CRYSTAL DISPLAY HAVING PHOTO-SENSING INPUT MECHANISM - A liquid crystal display having photo-sensing input mechanism includes a first gate line for transmitting a first gate signal, a second gate line for transmitting a second gate signal, a data line for transmitting a data signal, a pixel unit for outputting an image signal according to the first gate signal and the data signal, a readout line for transmitting a readout signal, a photo-sensing input unit and a driving adjustment unit. The photo-sensing input unit is utilized for generating a sensing voltage according to a driving voltage and an incident light signal, and is further utilized for outputting the readout signal according to the sensing voltage and the first gate signal. The driving adjustment unit is employed to provide the driving voltage according to the second gate signal and the incident light signal. | 09-20-2012 |
20150035805 | LIQUID CRYSTAL DISPLAY HAVING PHOTO-SENSING INPUT MECHANISM - A liquid crystal display having photo-sensing input mechanism includes a first gate line for transmitting a first gate signal, a second gate line for transmitting a second gate signal, a data line for transmitting a data signal, a pixel unit for outputting an image signal according to the first gate signal and the data signal, a readout line for transmitting a readout signal, a photo-sensing input unit and a driving adjustment unit. The photo-sensing input unit is utilized for generating a sensing voltage according to a driving voltage and an incident light signal, and is further utilized for outputting the readout signal according to the sensing voltage and the first gate signal. The driving adjustment unit is employed to provide the driving voltage according to the second gate signal and the incident light signal. | 02-05-2015 |
Patent application number | Description | Published |
20100052057 | HIGH VOLTAGE DEVICE WITH REDUCED LEAKAGE - A semiconductor device is provided which includes a semiconductor substrate, a gate structure formed on the substrate, sidewall spacers formed on each side of the gate structure, a source and a drain formed in the substrate on either side of the gate structure, the source and drain having a first type of conductivity, a lightly doped region formed in the substrate and aligned with a side of the gate structure, the lightly doped region having the first type of conductivity, and a barrier region formed in the substrate and adjacent the drain. The barrier region is formed by doping a dopant of a second type of conductivity different from the first type of conductivity. | 03-04-2010 |
20100317181 | Gate Stack Integration of Complementary MOS Devices - A method of forming an integrated circuit structure includes providing a substrate comprising a first device region and a second device region; forming an oxide cap over the substrate and in the first device region and the second device region; forming a first metal layer over the oxide cap, wherein the first metal layer has a first portion in the first device region and a second portion in the second device region; forming a mask to cover the second portion of the first metal layer, wherein the first portion of the first metal layer is exposed; removing the first portion of the first metal layer and the oxide cap from the first device region; removing the mask; and forming a second metal layer in the first device region and the second device region, wherein the second metal layer in the second device region is over the second portion of the first metal layer. | 12-16-2010 |
20120273890 | Method of Fabricating a Gate Stack Integration of Complementary MOS Device - A method includes providing a substrate comprising a first device region and a second device region; forming an oxide cap over the substrate and in the first device region and the second device region; forming a first metal layer over the oxide cap, wherein the first metal layer has a first portion in the first device region and a second portion in the second device region; forming a mask to cover the second portion of the first metal layer, wherein the first portion of the first metal layer is exposed; removing the first portion of the first metal layer and the oxide cap from the first device region; removing the mask; and forming a second metal layer in the first device region and the second device region, wherein the second metal layer in the second device region is over the second portion of the first metal layer. | 11-01-2012 |
20130119466 | High Voltage Device with Reduced Leakage - A semiconductor device is provided which includes a semiconductor substrate, a gate structure formed on the substrate, sidewall spacers formed on each side of the gate structure, a source and a drain formed in the substrate on either side of the gate structure, the source and drain having a first type of conductivity, a lightly doped region formed in the substrate and aligned with a side of the gate structure, the lightly doped region having the first type of conductivity, and a barrier region formed in the substrate and adjacent the drain. The barrier region is formed by doping a dopant of a second type of conductivity different from the first type of conductivity. | 05-16-2013 |
20150111361 | Integrated Circuit Resistor - A method of fabricating a semiconductor device is disclosed. The method includes providing a substrate including an isolation region, forming a resistor over the isolation region, and forming a contact over the resistor. The method also includes implanting with a dopant concentration that is step-increased at a depth of the resistor and that remains substantially constant as depth increases. | 04-23-2015 |
Patent application number | Description | Published |
20090009679 | Backlight Module - A backlight module includes a frame, an optical element, a bottom plate, a holder, and a light source. The optical elements are located on the frame and a space between the sidewall of the frame and the optical elements. The bottom plate located under the optical elements. The light source is on the holder inserted into the space, The holder is inserted into the space along the direction toward the bottom surface of the bottom plate, and is removed from the space along the opposing direction. | 01-08-2009 |
20090034177 | Supporting Assembly for a Liquid Crystal Display - A supporting assembly for a LCD includes a front bezel, a cover, a first fastener, a back bezel, a second fastener, a frame, a lighting carrier. The cover is extended from the front bezel. The first fastener is disposed on the cover. The back bezel is coupled to the front bezel and has an opening opposite the cover. The second fastener is disposed on the back bezel and fastened to the first fastener. The frame is disposed between the front bezel and the back bezel and has a carrier socket opposite the cover. The lighting carrier is plugged into the carrier socket. | 02-05-2009 |
20090052176 | Replacable Light Source for Light Source Module and Back Light Module - The present invention provides a light source module for using in a backlight module which includes a frame, a light source and a lid. The frame has two opposite side walls, and each of the side walls includes an inner side surface, a top surface and a cave. The cave has a first opening and a second opening connected with each other on the inner surface and the top surface respectively. Each of the inner surfaces is facing the other side wall, and the top surface intersects the inner surface with an angle. A light source has two opposite ends, and each of ends includes a positioning block. The positioning block engages with the cave through the second opening, and the light source extends along a first direction perpendicular to the inner surface, through the first opening and towards the opposite side wall of the frame. The lid covers the second opening and restricts the positioning block from moving relatively to the cave from the second opening. | 02-26-2009 |
20100238371 | Backlight Module - A backlight module includes a frame, an optical element, a bottom plate, a holder, and a light source. The optical elements are located on the frame and a space between the sidewall of the frame and the optical elements. The bottom plate located under the optical elements. The light source is on the holder inserted into the space, The holder is inserted into the space along the direction toward the bottom surface of the bottom plate, and is removed from the space along the opposing direction. | 09-23-2010 |
20110109832 | Supporting Assembly for a Liquid Crystal Display - A supporting assembly for a LCD includes a front bezel, a cover, a first fastener, a back bezel, a second fastener, a frame, a lighting carrier. The cover is extended from the front bezel. The first fastener is disposed on the cover. The back bezel is coupled to the front bezel and has an opening opposite the cover. The second fastener is disposed on the back bezel and fastened to the first fastener. The frame is disposed between the front bezel and the back bezel and has a carrier socket opposite the cover. The lighting carrier is plugged into the carrier socket. | 05-12-2011 |
Patent application number | Description | Published |
20130122674 | Silicon Layer for Stopping Dislocation Propagation - A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices. | 05-16-2013 |
20130270579 | Epitaxy Silicon on Insulator (ESOI) - Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI structure comprises a second epitaxial layer on the substrate, and a second dielectric layer on the second epitaxial layer. A semiconductor fabrication method comprises forming a dielectric layer over a substrate and surrounding a device fabrication region in the substrate with an isolation trench extending through the dielectric layer. The method also includes filling the isolation trench with a first epitaxial layer and forming a second epitaxial layer over the device fabrication region and over the first epitaxial layer. Then a portion of the first epitaxial layer is replaced with an isolation dielectric, and then a device such as a transistor is formed second epitaxial layer within the device fabrication region. | 10-17-2013 |
20140252489 | FinFET with Rounded Source/Drain Profile - A method of forming a FinFET with a rounded source/drain profile comprises forming a fin in a substrate, etching a source/drain recess in the fin, forming a plurality of source/drain layers in the source/drain recess; and etching at least one of the plurality of source/drain layers. The source/drain layers may be a silicon germanium compound. Etching at the source/drain layers may comprises partially etching each of the plurality of source/drain layers prior to forming subsequent layers of the plurality of source/drain layers. The source/drain layers may be formed with a thickness at a top corner of about 15 nm, and the source/drain layers may each be etched back by about 3 nm prior to forming subsequent layers of the plurality of source/drain layers. Forming the plurality of source/drain layers optionally comprises forming at least five source/drain layers. | 09-11-2014 |
20140264491 | Semiconductor Strips with Undercuts and Methods for Forming the Same - An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip. Each of the first dielectric region and the second dielectric region includes a first portion level with the semiconductor strip, and a second portion lower than the semiconductor strip. The second portion further includes a portion overlapped by the semiconductor strip. | 09-18-2014 |
20140264590 | FinFET with Bottom SiGe Layer in Source/Drain - A FinFET includes a substrate, a fin structure on the substrate, a source in the fin structure, a drain in the fin structure, a channel in the fin structure between the source and the drain, a gate dielectric layer over the channel, and a gate over the gate dielectric layer. At least one of the source and the drain includes a bottom SiGe layer. | 09-18-2014 |
20150102392 | FinFETs and Methods for Forming the Same - A FinFET and methods for forming a FinFET are disclosed. A method includes forming a semiconductor fin on a substrate, implanting the semiconductor fin with dopants, and forming a capping layer on a top surface and sidewalls of the semiconductor fin. The method further includes forming a dielectric on the capping layer, and forming a gate electrode on the dielectric. | 04-16-2015 |
20150137180 | FinFET with Bottom SiGe Layer in Source/Drain - A FinFET includes a substrate, a fin structure on the substrate, a source in the fin structure, a drain in the fin structure, a channel in the fin structure between the source and the drain, a gate dielectric layer over the channel, and a gate over the gate dielectric layer. At least one of the source and the drain includes a bottom SiGe layer. | 05-21-2015 |
Patent application number | Description | Published |
20090060750 | Fluid transportation device - A fluid transportation device includes a valve seat, a valve cap, a valve membrane, multiple buffer chambers, a vibration film and an actuator. The valve membrane is arranged between the valve seat and the valve cap, and includes several hollow-types valve switches, which includes at least a first valve switch and a second valve switch. The multiple buffer chambers include a first buffer chamber between the valve membrane and the valve cap and a second buffer chamber between the valve membrane and the valve seat. The vibration film is separated from the valve cap when the fluid transportation device is in a non-actuation status, thereby defining a pressure cavity. The actuator is connected to the vibration film. When the actuator is driven to be subject to deformation, the vibration film connected to the actuator is transmitted to render a volume change of the pressure cavity and result in a pressure difference for moving the fluid. | 03-05-2009 |
20090159830 | Fluid transportation device - A fluid transportation device includes a valve seat, a valve cap, a valve membrane, multiple buffer chambers, and an actuating module. The valve seat has an inlet channel and an outlet channel. The valve cap is disposed on the valve seat. The valve membrane is arranged between the valve seat and the valve cap. The multiple buffer chambers include a first buffer chamber between the valve membrane and the valve cap and a second buffer chamber between the valve membrane and the valve seat. Each of the first buffer chamber and the second buffer chamber has a flow-guiding structure extended from an outer edge to a center thereof. The actuating module has a periphery fixed on the valve cap. A pressure cavity is defined between the actuating module and the valve cap. Another flow-guiding structure is formed at an inner edge of the pressure cavity. | 06-25-2009 |
20090217994 | Multi-channel fluid conveying apparatus - A multi-channel fluid conveying apparatus, for delivering a fluid, includes a valve seat, a valve cover, a valve membrane, a plurality of temporary-deposit chambers, and an actuating device. The valve seat includes at least one inlet channel and at least one outlet channel. The valve cover is arranged on the valve seat. The valve membrane is interposed between the valve seat and the valve cover and includes a plurality of valve structures made of the same material with the same thickness, wherein at least one of the valve structures has a rigidity different from those of other valve structures. The plurality of temporary-deposit chambers is interposed between the valve membrane and the valve cover and between the valve membrane and the valve seat. The actuating device is, having a periphery, fixed to the valve cover. | 09-03-2009 |
20090242060 | Fluid transportation device having multiple double-chamber actuating structrures - A fluid transportation device includes a flow-gathering module and multiple double-chamber actuating structures. The flow-gathering module includes two surfaces opposed to each other, multiple first flow paths and multiple second flow paths running through the two surfaces, an inlet channel arranged between the two surfaces and communicated with the multiple first flow paths, and an outlet channel arranged between the two surfaces and communicated with the multiple second flow paths. The multiple double-chamber actuating structures are arranged on the flow-gathering module side by side. Each double-chamber actuating structure includes a first chamber and a second chamber symmetrically arranged on the two surface of the flow-gathering module. Each of the first chamber and the second chamber includes a valve cap arranged over the flow-gathering module, a valve membrane arranged between the flow-gathering module and the valve cap, and an actuating member having a periphery fixed on the valve cap. | 10-01-2009 |
20090242061 | Dual-cavity fluid conveying apparatus - A dual-cavity fluid conveying apparatus includes a flow-converging device, a first cavity body, and a second cavity body. The flow-converging device includes two sides corresponding to each other; a first channel and a second channel both passing through the two sides; and an inlet passage and an outlet passage both arranged between the two sides and communicated with the first channel and the second channel, respectively. The first cavity body and the second cavity body are symmetrically disposed at the two sides of the flow-converging device, wherein the first cavity body and the second cavity body each includes a valve cover disposed on one side of the flow-converging device, a valve membrane interposed between the one side of the flow-converging device and the valve cover, and an actuating device disposed circumferentially on the valve cover so as to define, together with the valve cover, a pressure chamber. | 10-01-2009 |
20100301701 | VOLTAGE CONVERTER AND DRIVING SYSTEM USING SUCH VOLTAGE CONVERTER - A voltage converter is provided for receiving a low input DC voltage and driving a piezoelectric actuator of a fluid transportation device. The voltage converter includes plural capacitors, a resistor and a boost chip. The boost chip is connected with the plural capacitors and the resistor, has a switch element and a polar switching circuit, and receives the low input DC voltage. The low input DC voltage is increased and multiplied to a high DC voltage by a switching operation of the switch element. The high DC voltage is converted into an output AC voltage by the polar switching circuit so as to drive the piezoelectric actuator. An operating frequency of the boost chip is controlled by the plural capacitors and the resistor. | 12-02-2010 |
20120081420 | PRINTING SYSTEM - The present invention relates to a printing system, which comprises: a data receiving and processing unit connected with the electronic device, for receiving a printing signal from the electronic device and processing the printing signal into a data signal; and an ink-jet head module including a control chip and an ink-jet heating chip. The control chip includes a wireless transmission module and a control circuit, wherein the wireless transmission module includes an antenna, a front-end processing unit, an instruction unit, a clock transmission unit, and a modulation and demodulation unit. Besides, the control circuit includes a control processing unit, a coding and decoding processing unit, and a memory device, to receive the data signal processed by the wireless transmission module and transform the processed data signal into a control signal. In addition, the ink-jet heating chip is connected with the control circuit for executing the ink-jet printing. | 04-05-2012 |
20120081471 | INK-JET CHIP - The present invention relates to an ink-jet chip, adaptive for a printing device, at least comprising: a plurality of ink-jet heating elements and an ink-jet signal generating circuit. The ink-jet signal generating circuit at least includes: a counter electrically connected with the printing device, for receiving a counter control signal and a pulse signal, and generating a plurality of counter signals corresponding to the counter control signal and the pulse signal; and a decoder electrically connected with the counter, for receiving and decoding the plurality of counter signals, for generating a plurality of address signals, and selecting a corresponding ink-jet heating element basing on the plurality of address signals. | 04-05-2012 |
20120242726 | INK-JET HEAD - The present invention related to an ink-jet head, adaptive for an ink cartridge including at least one ink tank, the ink jet head includes: a nozzle board, having a plurality of nozzles; and an ink-jet chip, being used for controlling the ink-jetting and having a total area region consisting of a length and a width, wherein the total area region includes: a non-wiring region, where at least one ink flow channel being installed therein; and a wiring region, where an internal circuit being installed therein; wherein the internal circuit includes a plurality of ink-jet unit sets, and every ink-jet units of the plurality of ink-jet unit sets include a heater installed correspondingly to the nozzle; wherein the area of the wiring region of the ink-jet chip is less than 77% of the area of the total area region of the ink-jet chip. | 09-27-2012 |
20120242746 | INKJET PRINTHEAD - The present invention related to an inkjet printhead, adaptive for an ink cartridge including three ink-supplying tank, the inkjet printhead includes: a nozzle plate having a plurality of nozzles; and an inkjet chip for controlling ink jetting and having a total area region having a length and a width, the total area region including: a non-wiring region for installing three single ink-supplying flow channels; and a wiring region for installing an internal circuit including a plurality inkjet unit assembly, each inkjet unit of the inkjet unit assembly including a heater installed correspondingly to the nozzle; wherein an area of the wiring region of the inkjet chip is or less than 77% of a total area of the inkjet chip. | 09-27-2012 |
20120242752 | INKJET PRINTHEAD - The present invention related to an inkjet printhead, adaptive for an ink cartridge including one ink-supplying tank, the inkjet printhead includes: a nozzle plate having a plurality of nozzles; and an inkjet chip for controlling ink jetting and having a total area region having a length and a width, the total area region including: a non-wiring region for installing one single ink-supplying flow channels; and a wiring region for installing an internal circuit including a plurality inkjet unit assembly, each inkjet unit of the inkjet unit assembly including a heater installed correspondingly to the nozzle; wherein an area of the wiring region of the inkjet chip is or less than 82% of a total area of the inkjet chip. | 09-27-2012 |
20120242763 | INK-JET HEAD - The present invention related to an ink-jet head, adaptive for an ink cartridge including two ink tanks, the ink-jet head includes: a nozzle board, having a plurality of nozzles; and an ink-jet chip, being used for controlling the ink-jetting and having a total area region consisting of a length and a width, wherein the total area region includes: a non-wiring region, where two ink flow channels being installed therein; and a wiring region, where an internal circuit being installed therein; wherein the internal circuit includes a plurality of ink-jet unit sets, and every ink-jet units of the plurality of ink-jet unit sets include a heater installed correspondingly to the nozzle; wherein the area of the wiring region of the ink-jet chip is less than 77% of the area of the total area region of the ink-jet chip. | 09-27-2012 |
Patent application number | Description | Published |
20080204730 | Method and System for Improving Accuracy of Critical Dimension Metrology - A method for improving accuracy of optical critical dimension measurement of a substrate is provided. A process parameter that influences the refractive index and extinction coefficient of a thin film in the substrate is identified. A refractive index and extinction coefficient across a plurality of wavelengths as a function of the process parameter is identified. During the regression modeling of the optical critical dimension measurement, the refractive index and extinction coefficient across the plurality of wavelengths is adjusted through the function via the process parameter. | 08-28-2008 |
20080233487 | Method and System for Optimizing Lithography Focus and/or Energy Using a Specially-Designed Optical Critical Dimension Pattern - Disclosed is a method and a system for optimizing lithography focus and/or energy using a specially-designed optical critical dimension pattern. A wafer comprising a plurality of photomasks is received. Critical dimension, line-end shortening, and side wall angle of the plurality of photomasks are measured using an integrated metrology equipment. A spectrum analysis is performed in a simulated spectra library to form analysis data. The analysis data is stored into a plurality of lookup tables of an optical critical dimension library. A lookup of the plurality of lookup tables is performed to determine a focus or energy of the wafer. | 09-25-2008 |
20150024305 | EXTREME ULTRAVIOLET LIGHT (EUV) PHOTOMASKS AND FABRICATION METHODS THEREOF - Embodiments of EUV photomasks and methods for forming a EUV photomask are provided. The method comprises providing a substrate, a reflective layer, a capping layer, a hard mask layer, and forming an opening therein. An absorber layer is then filled in the opening and over the top surface of the hard mask layer. A removing process is provided to form an absorber with a top surface lower than a top surface of the capping layer. | 01-22-2015 |
20150069622 | Via Definition Scheme - A method includes defining a metal pattern layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is grown over the metal pattern layer and the first dielectric layer. A metal trench is formed with a metal width in the first dielectric layer. A via hole is formed with a via width in the second dielectric layer. | 03-12-2015 |
20150072519 | Metal and Via Definition Scheme - A method includes defining a photoresist layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is formed over the photoresist and the first dielectric layer. The spacer layer has an opening that has a via width. The opening is disposed directly above a via location. A metal trench with a metal width is formed in the first dielectric layer. The metal width at the via location is greater than the via width. A via hole with the via width is formed at the via location in the second dielectric layer. | 03-12-2015 |
20150085268 | Extreme Ultraviolet Lithography Process And Mask - A system of an extreme ultraviolet lithography (EUVL) is disclosed. an extreme ultraviolet lithography (EUVL) system includes an extreme ultraviolet (EUV) reflection-type mask having a patterned flare-suppressing-by-phase-shifting (FSbPhS) layer disposed over a patterned absorption layer. The system also includes a radiation to expose the EUV mask and a projection optics box (POB) to collect and direct the radiation that reflects from the EUV mask to expose a target. | 03-26-2015 |
20150147686 | Extreme Ultraviolet Lithography Process And Mask - A low EUV reflectivity mask includes a low thermal expansion material (LTEM) layer, a low EUV reflectivity (LEUVR) multilayer over the LTEM layer in a first region, a high EUV reflectivity (HEUVR) multilayer over the LTEM layer in a second region and a patterned absorption layer over the LEUVR multilayer and the HEUVR multilayer. | 05-28-2015 |
20150287596 | Method to Define Multiple Layer Patterns with a Single Exposure by Charged Particle Beam Lithography - The present disclosure provides a method that includes forming a first patternable material layer on a substrate; forming a second patternable material layer over the first patternable material layer; and performing a charged particle beam lithography exposure process to the first patternable material layer and the second patternable material layer, thereby forming a first latent feature in the first patternable material layer and a second latent feature in the second patternable material layer. | 10-08-2015 |
20150331307 | Extreme Ultraviolet Light (EUV) Photomasks and Fabrication Methods Thereof - Embodiments of EUV photomasks and methods for forming a EUV photomask are provided. The method comprises providing a substrate, a reflective layer, a capping layer, a hard mask layer, and forming an opening therein. An absorber layer is then filled in the opening and over the top surface of the hard mask layer. A removing process is provided to form an absorber with a top surface lower than a top surface of the capping layer. | 11-19-2015 |