Owen, MA
Dafydd Rhys Owen, Cambridge, MA US
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20140121279 | Enkephalin Analogues - The present invention relates to dipeptide enkephalin analogues of Formula (I) and their tautomers, ionic forms and pharmaceutically acceptable salts, and their use in medicine, in particular as opioid agonists. | 05-01-2014 |
20140275100 | PYRIDAZINE DERIVATIVES USEFUL IN THERAPY - The invention provides compounds of formula I, (I) wherein: R represents a cyclic group selected from phenyl, heteroaryl, heterocyclyl and C 3-6 cycloalkyl; 10 wherein each cyclic group is optionally substituted with from 1 to 3 substituents selected from halo, C -6 alkyl optionally substituted with 1-3 halogen atoms, phenyl, C -6 alkoxy optionally substituted with 1-3 halogen atoms, cyano, heteroaryl 1a and heterocyclyl 1a; and wherein each cyclic group is optionally fused to a benzene ring or a 5- or 16-membered heteroaromatic or heterocyclic ring each containing from 1 to 3 heteroatoms (selected from N, O and S); and when the group is substituted the substitution may occur anywhere on the optionally fused ring system as a whole; and wherein heterocyclyl and heterocyclyl 1a may additionally be substituted with ═O; 20 X represents a bond or C -6 alkylene (which may be straight or branched); R 2 represents H or C -6 alkyl; R 3 represents H or C -6 alkyl; Y represents a bond or C -6 alkylene (which may be straight or branched, and optionally substituted with OH or CF 3); 2 R 4 represents a cyclic group selected from phenyl, heteroaryl 4, heterocyclyl 4 and C 3-6 cycloalkyl; wherein each cyclic group is optionally substituted with from 1 to 3 substituents selected from halo, C -6 alkyl optionally substituted with 1-3 halogen atoms, TET01063WO 4 phenyl, C -6 alkyl substituted with phenyl, C -6 alkoxy optionally substituted with -3 halogen atoms, cyano, heteroaryl 4a and heterocyclyl 4a; and wherein each cyclic group is optionally fused to benzene ring or a 5- or 6-membered heteroaromatic or heterocyclic ring each containing from 1 to 3 heteroatoms (selected from N, O and S); and when the group is substituted the substitution may occur anywhere on the optionally fused ring system as a whole; and wherein heterocyclyl 4 and heterocyclyl 4a may additionally be substituted with ═O; heteroaryl, heteroaryl 1a, heteroaryl 4 and heteroaryl 4a independently represent a 5- or 6-membered heteroaryl group containing from 1 to 3 heteroatoms (selected from N, O and 10 S); and heterocyclyl, heterocyclyl 1a, heterocyclyl 4 and heterocyclyl 4a independently represent a 5- or 6-membered heterocyclyl group containing from 1 to 3 heteroatoms (selected from N, O and S); and pharmaceutically acceptable salts and solvates thereof.1 The compounds are useful as pharmaceuticals, particularly in the treatment of fibrotic diseases, cancer and pain. | 09-18-2014 |
Gareth William John Owen, Somerville, MA US
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20090252063 | Method & system for configuring a network communications device - A method and system for auto-provisioning communications devices, the system includes a network appliance associated with a software and/or hardware module with instructions for managing the automatic configuration of communications devices. | 10-08-2009 |
James M. Owen, Waltham, MA US
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20110022105 | Defibrillation system - A method of treating a patient for ventricular tachycardia using a wearable defibrillator includes monitoring the patient for a predetermined condition via one or more electrodes on the defibrillator, sending a message to the patient in response to the predetermined condition, activating the defibrillator so that the defibrillator delivers defibrillation energy to the patient, and storing at least one of the results of the monitoring, sending and activating steps in a memory on the defibrillator. The method also includes downloading information stored in the memory of the defibrillator to a base station having an external interface, and transmitting the information downloaded from the memory of the base station to an external location via the external interface of the base station. | 01-27-2011 |
20140364918 | DEFIBRILLATION SYSTEM - A method of treating a patient for ventricular tachycardia using a wearable defibrillator includes monitoring the patient for a predetermined condition via one or more electrodes on the defibrillator, sending a message to the patient in response to the predetermined condition, activating the defibrillator so that the defibrillator delivers defibrillation energy to the patient, and storing at least one of the results of the monitoring, sending and activating steps in a memory on the defibrillator. The method also includes downloading information stored in the memory of the defibrillator to a base station having an external interface, and transmitting the information downloaded from the memory of the base station to an external location via the external interface of the base station. | 12-11-2014 |
James G. Owen, Bolton, MA US
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20130205192 | TEXT IMPORT TOOL FOR A TECHNICAL COMPUTING ENVIRONMENT - A device receives text that includes data values, and parses the text to identify data types associated with the data values. The device generates, based on the data values and the data types, a graphical representation of the text that includes data cells corresponding to the data values, and provides the graphical representation for display. The device receives one or more selections of one or more data cells in the graphical representation, stores the one or more selections as a selection history, and provides the selection history for display. | 08-08-2013 |
20130339882 | GRAPHICAL DATA CONVERSION/TRANSLATION - One or more computer-readable storage media for storing computer-executable instructions executable by processing logic is provided. The media storing one or more instructions that when executed by the processing logic causes the processing logic to receive data in a first format for conversion to a second format different than the first format, wherein the data includes information having a first type and information having a second type and display the data in the first format via a graphical interface. One or more translation rules are received relating to processing the information having the first type or the information having the second type. The one or more translation rules are pre-applied to the data in the first format. Effects of the pre-applied rules on the displayed data are displayed via the graphical interface. The data in the first format is converted to the data in the second format based on the one or more translation rules. | 12-19-2013 |
20140115448 | GRAPHICAL DATA CONVERSION/TRANSLATION - One or more computer-readable storage media for storing computer-executable instructions executable by processing logic is provided. The media storing one or more instructions that when executed by the processing logic causes the processing logic to receive data in a first format for conversion to a second format different than the first format, wherein the data includes information having a first type and information having a second type and display the data in the first format via a graphical interface. One or more translation rules are received relating to processing the information having the first type or the information having the second type. The one or more translation rules are pre-applied to the data in the first format. Effects of the pre-applied rules on the displayed data are displayed via the graphical interface. The data in the first format is converted to the data in the second format based on the one or more translation rules. | 04-24-2014 |
20140122986 | TEXT IMPORT TOOL FOR A TECHNICAL COMPUTING ENVIRONMENT - A device receives text that includes data values, and parses the text to identify data types associated with the data values. The device generates, based on the data values and the data types, a graphical representation of the text that includes data cells corresponding to the data values, and provides the graphical representation for display. The device receives one or more selections of one or more data cells in the graphical representation, stores the one or more selections as a selection history, and provides the selection history for display. | 05-01-2014 |
James Gareth Owen, Bolton, MA US
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20120313953 | GRAPHICAL DATA CONVERSION/TRANSLATION - A computer-readable storage media for storing computer-executable instructions executable by processing logic causes the processing logic to receive data in a first format for conversion to a second format different than the first format, wherein the data includes information having a first type and information having a second type and display the data in the first format via a graphical interface. One or more translation rules are received relating to processing the information having the first type or the information having the second type. The one or more translation rules are pre-applied to the data in the first format. Effects of the pre-applied rules on the displayed data are displayed via the graphical interface. The data in the first format is converted to the data in the second format based on the one or more translation rules. | 12-13-2012 |
Jonathan Owen, Northborough, MA US
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20100250856 | METHOD FOR WAY ALLOCATION AND WAY LOCKING IN A CACHE - A system and method for data allocation in a shared cache memory of a computing system are contemplated. Each cache way of a shared set-associative cache is accessible to multiple sources, such as one or more processor cores, a graphics processing unit (GPU), an input/output (I/O) device, or multiple different software threads. A shared cache controller enables or disables access separately to each of the cache ways based upon the corresponding source of a received memory request. One or more configuration and status registers (CSRs) store encoded values used to alter accessibility to each of the shared cache ways. The control of the accessibility of the shared cache ways via altering stored values in the CSRs may be used to create a pseudo-RAM structure within the shared cache and to progressively reduce the size of the shared cache during a power-down sequence while the shared cache continues operation. | 09-30-2010 |
20100281231 | HIERARCHICAL MEMORY ARBITRATION TECHNIQUE FOR DISPARATE SOURCES - A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is at least partially based on an indicator of a previous memory request selected for placement in the merged memory request stream. | 11-04-2010 |
20120166890 | ERROR DETECTION IN FIFO QUEUES USING SIGNATURE BITS - A first in, first out (FIFO) queue includes logic to provide detection of operational errors in the FIFO queue. The FIFO queue includes entries to store data written to the FIFO queue and signature bits, each signature bit corresponding to one of the entries. A test pattern and a read signature register includes a number of bits greater than a depth of the FIFO queue. A comparator compares the test pattern to the read signature register and output an error signal indicating whether the test pattern matches the read signature register. | 06-28-2012 |
20120331226 | HIERARCHICAL MEMORY ARBITRATION TECHNIQUE FOR DISPARATE SOURCES - A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is based on an indicator of a previous memory request selected for placement in the merged memory request stream. | 12-27-2012 |
Jonathan M. Owen, Northborough, MA US
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20100014535 | DATA PROCESSING DEVICE INTERFACE AND METHODS THEREOF - A method of receiving communications at a data processing device includes receiving a packet from a virtual channel associated with a physical communication link. The packet is associated with a link virtual channel, and is stored in a storage location with the link virtual channel. Multiple internal virtual channels can be associated with the link virtual channel. A pointer to the storage location is enqueued in one of a plurality of FIFOs associated with one of the internal virtual channels. Each FIFO of the plurality of FIFOs stores pointers associated with a different internal virtual channel, allowing receiver arbitration logic to reorder between internal virtual channels based on internal resource availability and current priorities among virtual channels. This reduces the likelihood of communication deadlock and supports multiple classes of service. | 01-21-2010 |
20110078478 | METHOD AND APPARATUS FOR TRANSITIONING DEVICES BETWEEN POWER STATES BASED ON ACTIVITY REQUEST FREQUENCY - A method for transitioning power states in a device includes designating a first reduced power state as a target power state. A first expected residency for the target power state is determined based on a counting of activity requests associated with the device. The device is transitioned to the target power state responsive to the expected residency satisfying a first predetermined threshold. | 03-31-2011 |
20110112798 | CONTROLLING PERFORMANCE/POWER BY FREQUENCY CONTROL OF THE RESPONDING NODE - A processing node tracks probe activity level associated with its internal caching or memory system. If the probe activity level increases above a threshold probe activity level, the performance state of the processing node is increased above its current performance state to provide enhanced performance capability in responding to the probe requests. After entering the higher performance state in response to the probe activity level being above the threshold probe activity level, the processing nodes returns to a lower performance state in response to a reduction in probe activity. There may be multiple threshold probe activity levels and associated performance states. | 05-12-2011 |
20110283124 | METHOD AND APPARATUS FOR CACHE CONTROL - A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed. | 11-17-2011 |
20120290800 | METHOD AND APPARATUS TO REDUCE MEMORY READ LATENCY - A method and apparatus for training read latency of a memory are disclosed. A memory controller includes a command FIFO configured to convey commands to a memory, a data queue coupled to receive data from the memory, and a register configured to provide a value indicative of a number of cycles of a first clock signal after which data is valid. During a startup routine, the memory controller is configured to compare data received by the data queue to a known data pattern after a specified number of cycles of the first clock signal have elapsed. The memory controller is further to configured to decrement the first value and repeat conveying and comparing if the data received matches the data pattern. If the received data does not match the data pattern for any attempted read of the memory, the memory controller is configured to program a second value into the register. | 11-15-2012 |
20130227321 | METHOD AND APPARATUS FOR CACHE CONTROL - A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed. | 08-29-2013 |
Jonathan M. Owen, Northboro, MA US
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20080288799 | DYNAMIC PROCESSOR POWER MANAGEMENT DEVICE AND METHOD THEREOF - A processor can operate in different power modes. In an active power mode, the processor executes software. In response to receiving a halt indication from the software, hardware at the processor evaluates bus transactions for the processor. If the bus transactions meet a heuristic, hardware places a processor core in a lower power mode, such as a retention mode. Because the bus transactions are evaluated by hardware, rather than by software, and the software is not required to perform handshakes and other protocols to place the processor in the lower power mode, the processor is able to place the processor core into the lower power mode more quickly, thereby conserving power. | 11-20-2008 |
20090259874 | DATA TRANSFER DEVICE AND METHOD THEREOF - A data transfer device transfers data between two clock domains of a data processing device when the data processing device is in a test mode. The data transfer device receives clock signals associated with each clock domain. To transfer data from a first clock domain to a second clock domain the data transfer device identifies transitions of clock signals associated with each clock domain that are sufficiently remote from each other so that data can deterministically be provided by one clock domain and sampled by the other. This ensures that data can be transferred between the clock domains deterministically even when the phase relationship between the clock signals is indeterminate. | 10-15-2009 |
Timothy Owen, Watertown, MA US
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20150339572 | SYSTEMS AND TECHNIQUES FOR PREDICTIVE DATA ANALYTICS - Systems and techniques for predictive data analytics are described. In a method for selecting a predictive model for a prediction problem, the suitabilities of predictive modeling procedures for the prediction problem may be determined based on characteristics of the prediction problem and/or on attributes of the respective modeling procedures. A subset of the predictive modeling procedures may be selected based on the determined suitabilities of the selected modeling procedures for the prediction problem. A resource allocation schedule allocating computational resources for execution of the selected modeling procedures may be generated, based on the determined suitabilities of the selected modeling procedures for the prediction problem. Results of the execution of the selected modeling procedures in accordance with the resource allocation schedule may be obtained. A predictive model for the prediction problem may be selected based on those results. | 11-26-2015 |