Park, Kyoungki-Do
Dongsam Park, Kyoungki-Do KR
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20120273959 | Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Substrate for Vertical Interconnect in POP - A semiconductor device has a substrate with a first conductive layer over a surface of the substrate and a plurality of cavities exposing the first conductive layer. A first semiconductor die having conductive TSV is mounted into the cavities of the substrate. A first insulating layer is formed over the substrate and first semiconductor die and extends into the cavities to embed the first semiconductor die within the substrate. A portion of the first insulating layer is removed to expose the conductive TSV. A second conductive layer is formed over the conductive TSV. A portion of the first conductive layer is removed to form electrically common or electrically isolated conductive segments of the first conductive layer. A second insulating layer is formed over the substrate and conductive segments of the first conductive layer. A second semiconductor die is mounted over the substrate electrically connected to the second conductive layer. | 11-01-2012 |
20120273960 | Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Encapsulant with TMV for Vertical Interconnect in POP - A semiconductor device has a carrier or first conductive layer with a plurality of TSV semiconductor die mounted over the carrier or first conductive layer. An encapsulant is deposited around the first semiconductor die and over the carrier or first conductive layer to embed the first semiconductor die. A conductive TMV is formed through the encapsulant. A second conductive layer is formed over a first surface of the encapsulant. A first insulating layer is formed over the first surface of the encapsulant while exposing portions of the second conductive layer. A second insulating layer is formed over the second surface of the encapsulant while exposing portions of the first conductive layer. Alternatively, a first interconnect structure is formed over the first surface of the encapsulant. The carrier is removed and a second interconnect structure is formed over a second surface of the encapsulant. | 11-01-2012 |
Eun-Young Park, Kyoungki-Do KR
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20090168567 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device can ensure a sufficient margin between a column select signal and a column address signal when a delay time of the column select signal is increased to improve an address access time during a write operation. The semiconductor memory device includes a discrimination signal generating circuit configured to generate a discrimination signal activated in a write operation of the device, and a selective delay circuit configured to selectively delay a column address in response to the discrimination signal. | 07-02-2009 |
Hong-June Park, Kyoungki-Do KR
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20090002031 | Slew rate controlled output driver for use in semiconductor device - An output driver for use in a semiconductor is capable of maintaining its slew rate constantly regardless of PVT (Process/Voltage/Temperature) variation. The output driver includes a pre-driving unit for pre-driving a data signal; a main driving unit for driving an output pad in response to the output signal of the pre-driving unit; and a slew rate modeling unit for generating a pre-driver bias signal to constantly maintain effective resistances of a pull-up path and a pull-down path of the pre-driving unit by modeling the pre-driving unit. | 01-01-2009 |
Hyun-Sik Park, Kyoungki-Do KR
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20080220543 | Method for fabricating semiconductor device - A method for fabricating a semiconductor device includes forming a fuse over a substrate, the fuse having a barrier layer, a metal layer, and an anti-reflective layer stacked, selectively removing the anti-reflective layer, forming an insulation layer over a whole surface of the resultant structure including the fuse, and performing repair-etching such that part of the insulation layer remains above the fuse. | 09-11-2008 |
Jeong-Hoon Park, Kyoungki-Do KR
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20100221923 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a structure comprising at least two heterogeneous layers having different stress levels; and a stress relief layer disposed between the two heterogeneous layers to relive a difference in the stress levels. The stress relief layer may include: a first layer formed over a first heterogeneous layer; a second layer formed over the first layer; and a third layer formed between the second layer and a second heterogeneous layer. | 09-02-2010 |
Jong Bum Park, Kyoungki-Do KR
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20090230511 | METHOD FOR FORMING CAPACITOR IN A SEMICONDUCTOR DEVICE - A method for forming a capacitor of a semiconductor device ensures charging capacity and improves leakage current characteristic. In the capacitor forming method, a semiconductor substrate formed with a storage node contact is prepared first. Next, a storage electrode is formed such that the storage electrode is connected to the storage node contact. Also, a dielectric film comprised of a composite dielectric of a SrTiO3 film and an anti-crystallization film is formed on the storage electrode. Finally, a plate electrode is formed on the dielectric film. | 09-17-2009 |
Kee-Teok Park, Kyoungki-Do KR
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20080211551 | Semiconductor memory device - A semiconductor memory device performs a reset operation at a wafer state by using a signal input through an address pin in a test mode. The semiconductor memory device includes a buffer for transferring a reset command in response to a reset-active signal and a test reset signal, a test-reset entry signal generation unit for generating an internal test-reset entry signal in response to the test reset signal, and a rest signal driving unit for driving an active signal of an output signal of the buffer and the internal test-reset entry signal as an internal reset signal for a reset mode entry. | 09-04-2008 |
20080212383 | Circuit and method for parallel test of memory device - A test circuit in a memory device includes a first compression unit configured to compress data of a plurality of cells to transmit first compressed data to a plurality of input/output lines, and a second compression unit configured to compress the first compressed data on the plurality of input/output line to output second compressed data to at least one output pin, wherein the second compression unit operates in a low compressing mode and a high compressing mode in response to a data compression selecting signal. | 09-04-2008 |
20080219068 | ZQ CALIBRATION CONTROLLER AND METHOD FOR ZQ CALIBRATION - A ZQ calibration circuit performs a ZQ calibration additionally in an initial operation of a semiconductor memory device. The ZQ calibration controller of the ZQ calibration circuit includes a first signal generator, a second signal generator, and a control unit. The first signal generator generates a pre-calibration signal during an initialization of the semiconductor memory device. The second signal generator generates ZQ calibration signals in response to a ZQ calibration command. The control unit outputs signals to control a ZQ calibration in response to the pre-calibration signal and the ZQ calibration signals. | 09-11-2008 |
20090013225 | TEST MODE CONTROL CIRCUIT - Provided is a test mode control circuit capable of preventing an MRS (mode register set) from changing in a test mode exit after a test mode entry. In the test mode control circuit, an MRS controller logically combines an MRS signal, a bank address, an MRS address, and a test mode control signal to output a latch control signal. A test mode control unit detects a test mode entry and a test mode exit to selectively activate one of a test mode set signal and a test mode exit signal, and outputs the test mode control signal having different voltage levels according to an activation state of the test mode set signal or the test mode exit signal. An address latch latches an input address when the MRS signal is activated, and outputs the latched input address as the MRS address when the latch control signal is activated. | 01-08-2009 |
20090167413 | SEMICONDUCTOR DEVICE AND DATA OUTPUTTING METHOD OF THE SAME - Semiconductor device and data outputting method of the same includes an on die thermal sensor (ODTS) configured to output temperature information by detecting an internal temperature of the semiconductor device and an output driver configured to control a slew rate depending on the temperature information and output data. | 07-02-2009 |
20090168584 | SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A semiconductor memory device includes a clock synchronizing unit for receiving a first power voltage through a first power voltage terminal, and an additional power voltage providing unit for additionally providing a second power voltage to the first power voltage terminal for a predetermined period after leaving a power down mode. | 07-02-2009 |
20090273363 | OUTPUT DRIVER CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE OUTPUT DRIVER CIRCUIT, AND METHOD FOR OPERATING THE SEMICONDUCTOR MEMORY DEVICE - Output driver circuit, semiconductor memory device including the output driver circuit, and method for operating the semiconductor memory device, including a pre-driver to generate a pull-up control signal and a pull-down control signal according to a logic value of data to output, and to adjust and output a slew rate of the pull-up control signal and a slew rate of the pull-down control signal according to a termination resistance setting information, a pull-up driver to output logic high data in response to the pull-up control signal and a pull-down driver to output logic low data in response to the pull-down control signal. | 11-05-2009 |
20110255356 | SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A semiconductor memory device includes a clock synchronizing unit for receiving a first power voltage through a first power voltage terminal, and an additional power voltage providing unit for additionally providing a second power voltage to the first power voltage terminal for a predetermined period after leaving a power down mode. | 10-20-2011 |
Ki Chon Park, Kyoungki-Do KR
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20080198680 | SEMICONDUCTOR MEMORY DEVICE HAVING INPUT/OUTPUT SENSE AMPLIFICATION CIRCUIT WITH REDUCED JUNCTION LOADING AND CIRCUIT LAYOUT AREA - A semiconductor memory device includes an input/output sense amplifier that amplifies a read data and provides it to the external, when making a read operation. The semiconductor memory device includes a plurality of sense amplifiers that amplify data transferred from each bank and output them as amplified signals; a controller that judges the output states of the amplified signals in each sense amplifier to output driving signals corresponding to the output amplified signals; and a driver that drives an global input/output line with the driving signal, wherein the first and second sense amplifiers share the one driver, making it possible to reduce ‘tAA’ and get an advantage of a layout area. | 08-21-2008 |
20080239840 | SEMICONDUCTOR MEMORY DEVICE INCLUDING A GLOBAL INPUT/OUTPUT LINE OF A DATA TRANSFER PATH AND ITS SURROUNDING CIRCUITS - A semiconductor memory device includes an input/output line of a data transfer path and its surrounding circuits, comprising a controller which generates a control signal corresponding to command and address input in read and write operation; and a repeater which selects any one of the plurality of bank groups as the control signal to control data transfer between the selected bank group and an input/output pad. | 10-02-2008 |
20080239862 | Semiconductor memory device - The present invention provides a semiconductor memory device that can reduce unnecessary current consumption, as banks not accessing data maintain an inactivation state and do not receive an input address. A semiconductor memory device includes a plurality of banks grouped into a first group and a second group; and a bank control unit for selecting one of the first group and the second group in response to a bank address to transfer an address to the selected group. | 10-02-2008 |
20090067259 | SEMICONDUCTOR MEMORY DEVICE CONFIGURED TO REDUCE CURRENT CONSUMPTION ASSOCIATED WITH CRITICAL EVALUATING OF DATA WRITE OPERATIONS - A semiconductor memory device that utilizes a routing controller and various specific operational modes for reducing current consumption during data write pass operations. The semiconductor memory device includes write pass corresponding to first pad which transfer any one of general data and representative data corresponding to specific mode; and a routing controller routing the representative data to transfer pass corresponding to second pad according to the specific operational mode and upon deviating from the mode, interrupting the routing of the general data to the transfer pass. | 03-12-2009 |
20090168568 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device can output data according to a predetermined data output timing, in spite of a high frequency of system clock, even when a delay locked loop is disabled. The semiconductor memory device includes a delay locked loop configured to perform a delay locking operation on an internal clock to output delay locked clock, and a data output control unit configured to determine a data output timing, according to whether the delay locked loop is enabled or disabled, in response to a read command. | 07-02-2009 |
20090296499 | SEMICONDUCTOR MEMORY DEVICE INCLUDING A GLOBAL INPUT/OUTPUT LINE OF A DATA TRANSFER PATH AND ITS SURROUNDING CIRCUITS - A semiconductor memory device includes an input/output line of a data transfer path and its surrounding circuits, comprising a controller which generates a control signal corresponding to command and address input in read and write operation; and a repeater which selects any one of the plurality of bank groups as the control signal to control data transfer between the selected bank group and an input/output pad. | 12-03-2009 |
Ki-Seon Park, Kyoungki-Do KR
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20100014212 | CAPACITOR AND METHOD FOR FABRICATING THE SAME - A capacitor includes a lower electrode, a dielectric structure over the lower electrode, the dielectric structure including at least one crystallized zirconium oxide ZrO | 01-21-2010 |
Seongwon Park, Kyoungki-Do KR
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20120286418 | Semiconductor Device and Method of Forming Dummy Pillars Between Semiconductor Die and Substrate for Maintaining Standoff Distance - A semiconductor device has a semiconductor die with an insulation layer formed over an active surface of the semiconductor die. A conductive layer is formed over the first insulating layer electrically connected to the active surface. A plurality of conductive pillars is formed over the conductive layer. A plurality of dummy pillars is formed over the first insulating layer electrically isolated from the conductive layer and conductive pillars. The semiconductor die is mounted to a substrate. A height of the dummy pillars is greater than a height of the conductive pillars to maintain the standoff distance between the semiconductor die and substrate. The dummy pillars can be formed over the substrate. The dummy pillars are disposed at corners of the semiconductor die and a central region of the semiconductor die. A mold underfill material is deposited between the semiconductor die and substrate. | 11-15-2012 |
20130069221 | Semiconductor Device and Method of Forming Conductive Protrusions Over Conductive Pillars or Bond Pads as Fixed Offset Vertical Interconnect Structures - A semiconductor device has a semiconductor die mounted to a substrate. A plurality of conductive pillars is formed over a semiconductor die. A plurality of conductive protrusions is formed over the conductive pillars. Bumps are formed over the conductive protrusions and conductive pillars. Alternatively, the conductive protrusions are formed over the substrate. A conductive layer is formed over the substrate. The semiconductor die is mounted to the substrate by reflowing the bumps at a temperature that is less than a melting point of the conductive pillars and conductive protrusions to metallurgically and electrically connect the bumps to the conductive layer while maintaining a fixed offset between the semiconductor die and substrate. The fixed offset between the semiconductor die and substrate is determined by a height of the conductive pillars and a height of the conductive protrusions. A mold underfill material is deposited between the semiconductor die and substrate. | 03-21-2013 |
20130175701 | Semiconductor Device and Method of Forming Reduced Surface Roughness in Molded Underfill for Improved C-SAM Inspection - A semiconductor device includes a semiconductor die. An interconnect structure is formed over an active surface of the semiconductor die. An encapsulant is formed over the semiconductor die and interconnect structure including a first surface opposite the interconnect structure. A peripheral portion of the first surface includes a first roughness disposed outside a footprint of the semiconductor die. A semiconductor die portion of the first surface includes a second roughness less than the first roughness disposed over the footprint of the semiconductor die. The first surface of the encapsulant is disposed within a mold and around the semiconductor die to contact a surface of the mold that includes a third roughness equal to the first roughness and a fourth roughness equal to the second roughness. The first roughness includes a roughness of less than 1.0 micrometers. The second roughness includes a roughness in a range of 1.2-1.8 micrometers. | 07-11-2013 |
Yeongim Park, Kyoungki-Do KR
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20120292745 | Semiconductor Device and Method of Forming 3D Semiconductor Package with Semiconductor Die Stacked Over Semiconductor Wafer - A semiconductor device has a substrate and plurality of first semiconductor die having conductive vias formed through the first semiconductor die mounted with an active surface oriented toward the substrate. An interconnect structure, such as bumps or conductive pillars, is formed over the substrate between the first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The second semiconductor die is electrically connected through the interconnect structure to the substrate and through the conductive vias to the first semiconductor die. An underfill material is deposited between the first semiconductor die and substrate. Discrete electronic components can be mounted to the substrate. A heat spreader or shielding layer is mounted over the first and second semiconductor die and substrate. Alternatively, an encapsulant is formed over the die and substrate and conductive vias or bumps are formed in the encapsulant electrically connected to the first die. | 11-22-2012 |
Yisu Park, Kyoungki-Do KR
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20130299995 | Semiconductor Device and Method of Depositing Underfill Material With Uniform Flow Rate - A semiconductor device has a substrate and insulating layer formed over a surface of the substrate. A first conductive layer is formed over the surface of the substrate. A second conductive layer is formed over an opposing surface of the substrate. A conductive via is formed through the substrate. An opening is formed in the insulating layer while leaving the first conductive layer intact. The opening narrows with a non-linear side or linear side. The opening can have a rectangular shape. A semiconductor die is mounted over the surface of the substrate. An underfill material is deposited between the semiconductor die and substrate. The opening in the insulating layer reduces a flow rate of the underfill material proximate to the opening. The flow rate of the underfill material proximate to the opening is substantially equal to a flow rate of the underfill material away from the opening. | 11-14-2013 |
20130300004 | Semiconductor Device and Method of Controlling Warpage in Semiconductor Package - A semiconductor device has a substrate. An insulating layer is formed over a surface of the substrate. A semiconductor die is mounted over the surface of the substrate. A channel is formed in the insulating layer around the semiconductor die. An underfill material is deposited between the semiconductor die and the substrate and in the channel. A heat spreader is mounted over the semiconductor die with the heat spreader thermally connected to the substrate. A thermal interface material is formed over the semiconductor die. The underfill material is deposited between the semiconductor die and the substrate along a first edge of the semiconductor die and along a second edge of the semiconductor die opposite the first edge. The channel extends partially through the insulating layer formed over the substrate with the insulating layer maintaining coverage over the substrate within a footprint of the channel. | 11-14-2013 |