Patent application number | Description | Published |
20100289518 | CIRCUIT AND METHOD FOR DETECTING FAULTY DIODE - A circuit for detecting faulty diode is disclosed, wherein the circuit for detecting faulty diode comprises a diode having an anode connecting to a voltage supply; a first switch having a first end connected to a cathode of the diode; a testing current source connected to the second end of the first switch; a one-shot circuit connected to a control end of the first switch, by which an output signal is generated and transmitted to the control end; and a comparator connected to a reference voltage input terminal for receiving a reference voltage and connected to the second end of the first switch. When the one-shot circuit closes the first switch for a maintaining period to urge the comparator comparing the reference voltage with the voltage applied to the second end of the first switch, whereby a signal used to discriminate whether the diode is fail or not is generated. | 11-18-2010 |
20100289519 | CIRCUIT FOR DETECTING FAULTY DIODE - A circuit for detecting faulty diode comprises a diode having an anode connected to a voltage supply; a resistor having a first end connected to a cathode of the diode; a transistor having a drain connected to a second end of the resistor and a source that is grounded; a differential amplifier having a positive terminal connected to the drain of the transistor, a negative terminal connected to a reference voltage input terminal for receiving a reference voltage, and an output terminal connected to a gate of the transistor; and a buffer having an input terminal connected to the gate of the transistor, and a signal output terminal used to output a faulty signal. | 11-18-2010 |
20110043497 | LED DISPLAY SYSTEM AND MODE-DETERMINING METHOD OF SAME - A LED display system includes a display controller including an output port having a first output terminal and a second output terminal; a plurality of LED sets; and a plurality of driving circuits, coupled in series and coupled between the display controller and the plurality of LED sets, respectively. Each of the driving circuits includes a first signal-input terminal, a first signal-output terminal, a second signal-input terminal, and a second signal-output terminal, wherein the first signal-input terminal of a first one of the driving circuits is coupled to the first output terminal, the second signal-input terminal of the first one of the driving circuits is coupled to the second output terminal. The display controller asserts a transition period for switching the driving circuits from a first operation mode to a second operation mode by manipulating a first signal outputted to the driving circuits through the first output terminal. | 02-24-2011 |
20110043545 | LED DISPLAY SYSTEM AND DATA-TRANSMISSION CONTROL METHOD OF SAME - A LED display system includes a display controller includes an output/input port; a plurality of driving circuits coupled in series, wherein a first one of the driving circuits is coupled to the output/input port; and a plurality of LED sets respectively coupled to the plurality of driving circuits. A plurality of image data, outputted from the display controller, are shifted to the plurality of driving circuits, respectively, in a first direction through the first one of the driving circuits when the display controller is in a displaying mode; and a plurality of status data, respectively generated by the plurality of driving circuits, are shifted to the display controller in a second direction through the first one of the driving circuits when the display controller is in a detecting mode. | 02-24-2011 |
20120062657 | PIEZOELECTRIC INKJET HEAD STRUCTURE - A piezoelectric inkjet head structure includes an upper cover plate, a lower cover plate, a piezoelectric actuating module, a nozzle plate and a seal layer. The piezoelectric actuating module includes an upper piezoelectric chip, a lower piezoelectric chip, a first electrode, a second electrode, a conductive layer and a plurality of flow channels. The entrances of the flow channels of the upper piezoelectric chip and the lower piezoelectric chip are separated from each other by the same spacing interval. The entrances of the flow channels of the upper piezoelectric chip and the entrances of the flow channels of the lower piezoelectric chip are arranged in a staggered form. During operation of the piezoelectric actuating module, ink liquid is introduced into the flow channels of the piezoelectric actuating module from the upper cover plate and the lower cover plate, and then ejected out of the nozzles. | 03-15-2012 |
20130113865 | INK SUPPLY STRUCTURE AND FABRICATING METHOD THEREOF - An ink supply structure includes at least one ink cartridge, at least one dye ink chamber, and at least one pigment ink chamber. The at least one dye ink chamber is contained in the at least one ink cartridge for storing a dye ink. The at least one pigment ink chamber is contained in the at least one ink cartridge for storing a pigment ink. One of the dye ink within the dye ink chamber and the pigment ink within the pigment ink chamber is selectively supplied from the at least one ink cartridge. | 05-09-2013 |
20130328971 | INK-JET PRINTING MODULE - An ink-jet printing module is used for a page-width array ink-jet printer. The ink jet printing module includes a page-width array platen and a plurality of ink-jet cartridges. The page-width array platen has a plurality of receiving cavities arranged as an array. Each of the ink-jet cartridges is detachably and independently embedded into one of the receiving cavities, and includes a body for storing ink, an ink-jet chip to be driven for ejecting the ink, a plurality of nozzles disposed on the ink-jet chip, and a control node for receiving signal to drive the ink-jet chip. The ink-jet chip is disposed on a bottom of the page-width array platen and is driven to eject the ink through the nozzles onto a printing medium. | 12-12-2013 |
20130328972 | INK-JET PRINTING MODULE - An ink-jet printing module is used for a page-width array ink-jet printer. The ink jet printing module includes a page-width array platen and a plurality of ink-jet cartridges. The page-width array platen has a plurality of receiving cavities arranged as an array. Each of the ink-jet cartridges is detachably and independently embedded into one of the receiving cavities. | 12-12-2013 |
20140055526 | PAGE-WIDTH ARRAY PRINTING DEVICE - A page-width array printing device includes a page-width array printing mechanism including at least one page-width array printing module. The page-width array printing module includes a printing platform, a first page-width array printing unit and a second page-width array printing unit. The first page-width array printing unit includes a plurality of first inkjet cartridges. The second page-width array printing unit includes a plurality of second inkjet cartridges. The first page-width array printing unit and the second page-width array printing unit are in parallel with each other. The first inkjet cartridges and the second inkjet cartridges are staggered and independently and detachably disposed on the printing platform. Each of the first inkjet cartridges and the second inkjet cartridges includes an inkjet chip. The inkjet chip includes four ink supply channels and a plurality of nozzles so as to perform a monochromatic or polychromatic page-width array printing operation. | 02-27-2014 |
20150079213 | RAPID PROTOTYPING APPARATUS WITH PAGE-WIDTH ARRAY PRINTING MODULE - A rapid prototyping apparatus includes a construction platform, a movable platform, and a page-width array printing module. The construction platform includes a construction chamber. The movable platform and the construction platform are movable relative to each other. The page-width array printing module includes plural inkjet head structures. The printing platform and the movable platform are synchronously moved along a single direction in a reciprocating motion. The plural inkjet head structures are collaboratively defined as at least one page-width array printing unit. The plural inkjet head structures include respective inkjet chips. The inkjet chips are arranged in plural rows and in a staggered form, so that a printing width of the inkjet chips is larger than or equal to a width of a printed pattern. Moreover, at least one monochromatic print liquid is introduced into the construction chamber from the plural inkjet head structures. | 03-19-2015 |
20150079214 | PAGE-WIDTH PRINTING PLATFORM OF RAPID PROTOTYPING APPARATUS - A page-width printing platform comprises a plurality of inkjet head structures collaboratively defined as at least one page-width array printing unit. The inkjet head structures comprise respective inkjet chips disposed on the printing platform and arranged in plural rows and in a staggered form, so that a printing width of the inkjet chips is larger than or equal to a width of a printed pattern. Each of the inkjet chips comprises at least one liquid supply slot, wherein a plurality of liquid ejectors are located at one or two sides of the liquid supply slot along a long axis of the liquid supply slot. At least one monochromatic print liquid is introduced into the construction chamber from the plural inkjet head structures and printed on a construction material within the construction chamber, so that a rapid prototyping width-page printing operation is performed. | 03-19-2015 |
Patent application number | Description | Published |
20090114940 | Light-Emitting Device - The invention provides a light-emitting device, comprising a light-emitting element and a surface plasmon coupling element connected to the light-emitting element. In an embodiment of the invention, the surface plasmon coupling element comprises a dielectric layer connected to the light-emitting element and a metal layer on the dielectric layer. In another embodiment of the invention, the light-emitting device is a light-emitting diode, comprising an active layer between an n-type semiconductor layer and a p-type semiconductor layer, and a surface plasmon coupling element adjacent to the n-type semiconductor layer. In a further embodiment of the invention, a current spreading layer on a second type semiconductor layer of the light-emitting device includes a plurality of strip-shaped structures, and the surface plasmon coupling element is disposed on the current spreading layer and filled into the gap between the strip-shaped structures of the current spreading layer. | 05-07-2009 |
20100309638 | ELECTRONIC ELEMENT PACKAGING MODULE - An electronic element packaging module including a lead frame, an insulating layer and at least one electronic element is provided. The lead frame is a patterned metal sheet and has a first surface, a second surface opposite thereto and a through trench passing from the first surface to the second surface. A substrate portion and a plurality of lead portions around the substrate portion of the lead frame are defined by the through trench. The second surface of the lead frame is exposed outside the electronic element packaging module. The insulating layer disposed in the through trench has a third surface and a forth surface substantially coplanar with the first and the second surfaces, respectively. The electronic element disposed on the first surface is coupled to the lead frame. | 12-09-2010 |
20120268896 | METAL CORE PRINTED CIRCUIT BOARD AND ELECTRONIC PACKAGE STRUCTURE - An electronic package structure is provided which comprises a metal core PCB, an energy storage device and at least one electronic component. The at least one electronic component is disposed between the metal core PCB and the energy storage device. The metal core PCB defines at least a through hole. A thermal passage is disposed in the through hole. An insulating layer is disposed in the through hole and located between the metal layer of the metal core PCB and the thermal passage to prevent the electric coupling between the thermal passage and the metal layer. The energy storage device comprises at least a connecting pin in thermal contact with the thermal passage. | 10-25-2012 |
Patent application number | Description | Published |
20120104387 | Four-Terminal Metal-Over-Metal Capacitor Design Kit - A device includes a first MOM capacitor; a second MOM capacitor directly over and vertically overlapping the first MOM capacitor, wherein each of the first and the second MOM capacitors includes a plurality of parallel capacitor fingers; a first and a second port electrically coupled to the first MOM capacitor; and a third and a fourth port electrically coupled to the second MOM capacitor. The first, the second, the third, and the fourth ports are disposed at a surface of a respective wafer. | 05-03-2012 |
20120187494 | MOS Varactor Structure and Methods - Apparatus and methods for a MOS varactor structure are disclosed An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed. | 07-26-2012 |
20120293191 | HVMOS Reliability Evaluation using Bulk Resistances as Indices - A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance. | 11-22-2012 |
20130175655 | DUAL DNW ISOLATION STRUCTURE FOR REDUCING RF NOISE ON HIGH VOLTAGE SEMICONDUCTOR DEVICES - An isolation structure in a semiconductor device absorbs electronic noise and prevents substrate leakage currents from reaching other devices and signals. The isolation structure provides a duality of deep N-well (“DNW”) isolation structures surrounding an RF device or other source of electronic noise. The DNW isolation structures extend into the substrate at a depth of at least about 2.5 μm and may be coupled to V | 07-11-2013 |
20130260486 | MOS Varactor Structure and Methods - Apparatus and methods for a MOS varactor structure are disclosed. An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed. | 10-03-2013 |
20130299919 | MOS Devices with Mask Layers and Methods for Forming the Same - A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask. | 11-14-2013 |
20140001518 | Integrated Circuit Devices with Well Regions and Methods for Forming the Same | 01-02-2014 |
20140042506 | Transistors, Methods of Manufacture Thereof, and Image Sensor Circuits - Transistors, methods of manufacturing thereof, and image sensor circuits are disclosed. In one embodiment, a transistor includes a buried channel disposed in a workpiece, a gate dielectric disposed over the buried channel, and a gate layer disposed over the gate dielectric. The gate layer comprises an I shape in a top view of the transistor. | 02-13-2014 |
20140138749 | INTEGRATED CIRCUIT (IC) STRUCTURE - One or more techniques or systems for forming an integrated circuit (IC) or associated IC structure are provided herein. In some embodiments, the IC includes a junction gate field effect transistor (JFET) and a lateral vertical bipolar junction transistor (LVBJT). For example, the JFET and the LVBJT are formed in a same region, such as a substrate. In some embodiments, the JFET and the LVBJT are at least one of adjacent or share one or more features. In this manner, a reliable IC is provided, thus enabling power amplification, for example. | 05-22-2014 |
20140239364 | MOS Varactor Optimized Layout and Methods - Apparatus and methods for a MOS varactor structure are disclosed. An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed. | 08-28-2014 |
20140252542 | Structure and Method for an Inductor With Metal Dummy Features - The present disclosure provides a semiconductor device. The semiconductor device includes an inductor formed on a substrate and configured to be operable with a current of a frequency; and dummy metal features configured between the inductor and the substrate, the dummy metal features having a first width less than 2 times of a skin depth associated with the frequency. | 09-11-2014 |
20140264635 | RF Switch on High Resistive Substrate - A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch. | 09-18-2014 |
20140291806 | CAPACITOR ARRAYS FOR MINIMIZING GRADIENT EFFECTS AND METHODS OF FORMING THE SAME - Semiconductor devices having capacitor arrays. A semiconductor device is formed including a capacitor array formed in a plurality of cells in a two-dimensional grid. The capacitor array includes a plurality of operational capacitors formed in a first subset of the plurality of cells along a diagonal of the capacitor array. A first operational capacitor is formed in a cell at a first edge of the capacitor array and at a first edge of the diagonal of the capacitor array. The capacitor array also includes a plurality of dummy patterns formed about the plurality of operational capacitors in the capacitor array in a second subset of the plurality of cells to achieve symmetry in the grid about the diagonal. Each one of the plurality of operational capacitors is electrically coupled to another one of the plurality of operational capacitors. | 10-02-2014 |
20140295640 | CAPACITOR ARRAYS FOR MINIMIZING GRADIENT EFFECTS AND METHODS OF FORMING THE SAME - Methods of forming semiconductor devices. The method includes forming a capacitor array comprising a plurality of cells in a two-dimensional grid. The step of forming includes forming a plurality of operational capacitors in a first subset of the plurality of cells along a diagonal of the array, the plurality of operational capacitors comprising a first operational capacitor formed in a cell at a first edge of the capacitor array and at a first edge of the diagonal of the capacitor array. The step of forming also includes forming a plurality of dummy patterns about the plurality of operational capacitors in the capacitor array in a second subset of the plurality of cells to achieve symmetry in the grid about the diagonal. The method also includes electrically coupling each one of the plurality of operational capacitors to another one of the plurality of operational capacitors. | 10-02-2014 |
20140332857 | JUNCTION GATE FIELD-EFFECT TRANSISTOR (JFET), SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING - A junction gate field-effect transistor (JFET) includes a substrate, a source region formed in the substrate, a drain region formed in the substrate, a channel region formed in the substrate, and at least one gate region formed in the substrate. The channel region connects the source and drain regions. The at least one gate region contacts one of the source and drain regions at an interface, and the at least one gate region is isolated from the other of the source and drain regions. A dielectric layer covers the interface while exposing portions of the gate region and the one of the source and drain regions. | 11-13-2014 |
20140332858 | JUNCTION GATE FIELD-EFFECT TRANSISTOR (JFET), SEMICONDUCTOR DEVICE HAVING JFET AND METHOD OF MANUFACTURING - A junction gate field-effect transistor (JFET) includes a substrate, a source region formed in the substrate, a drain region formed in the substrate, a channel region formed in the substrate, and at least one gate region formed in the substrate. The channel region connects the source and drain regions. The at least one gate region is configured to cause a depletion region in one of the source and drain regions. | 11-13-2014 |