Patent application number | Description | Published |
20090122441 | Bit Patterned Magnetic Media Data Format - In an implementation, a media drive comprises bit patterned magnetic media and one or more modules. The one or more modules are to cause data to be written on the bit patterned magnetic media in a data sector that includes a synchronization mark disposed between data blocks of the data sector. | 05-14-2009 |
20090210771 | SYSTEMS AND METHODS FOR PERFORMING CONCATENATED ERROR CORRECTION - A system and method is provided for performing concatenated error correction. In one implementation, an apparatus for encoding data includes an outer encoder to generate a code word corresponding to received input data and a parity circuit to compute parities of logical cells of data, the logical cells of data being obtained from the code word and having a first logical cell. The apparatus also includes an inner encoder to generate an error correction bit for the first logical cell based on a first parity corresponding to the first logical cell, and to insert the error correction bit in the first logical cell. | 08-20-2009 |
20100011275 | Methods, Apparatuses, Systems, and Architectures for Quickly and Reliably Encoding and/or Decoding System Data - Methods, apparatuses, systems, and architectures for providing fast, independent, and reliable retrieval of system data (e.g., metadata) from a storage system, which enables minimal degradation in the reliability of user data. Methods generally include encoding the system data at least twice, at least once independently and at least once jointly along with user data. Methods can also include decoding the system data first, and upon a decoding failure, jointly decoding the system data and the user data. | 01-14-2010 |
20100017561 | SELECTIVELY ACCESSING MEMORY - Devices, systems, methods, and other embodiments associated with selectively accessing memory are described. In one embodiment, a method detects an indication indicative of whether to program fast access pages or slow access pages of a flash memory. In response to the detected indication, data is programmed from a volatile memory: (1) to the fast access pages of the flash memory while skipping the slow access pages, or (2) to the slow access pages while skipping the fast access pages. | 01-21-2010 |
20100017684 | DATA RECOVERY IN SOLID STATE MEMORY DEVICES - Embodiments herein provide data recovery techniques and configurations for solid state memory devices. For example, a method includes identifying a hard error associated with a cell of a solid state memory device, providing a location of the cell having the identified hard error to a decoder to recover data originally programmed to the cell, and recovering the data originally programmed to the cell using the decoder. Other embodiments may be described and/or claimed. | 01-21-2010 |
20100034018 | ACCESSING MEMORY USING FRACTIONAL REFERENCE VOLTAGES - Devices, systems, methods, and other embodiments associated with accessing memory using fractional reference voltage are described. In one embodiment, an apparatus includes comparison logic. The comparison logic compares a threshold voltage of a memory cell to at least one pair of fractional reference voltages to generate comparison results. The apparatus includes read logic to determine a bit value of the memory cell based, at least in part, on the comparison results. | 02-11-2010 |
20100205331 | Non-Volatile Memory That Includes An Internal Data Source - The present disclosure includes systems and techniques relating to a non-volatile memory that includes an internal data source. In some implementations, a device includes a buffer, a memory cell array, and processing circuitry coupled with the buffer and the memory cell array, and configured to selectively fill the buffer with auxiliary data from the internal data source specified by the controller and user data received from an external source, in response to instructions from the controller. | 08-12-2010 |
20100225506 | Multi-Mode Encoding for Data Compression - The present disclosure includes apparatus, systems and techniques relating to lossless data compression. In some implementations, an apparatus includes a memory module to store data. The memory module includes a first buffer portion to store encoded symbols of the data, and a second buffer portion to store symbols of the data to be encoded. The apparatus includes an encoder to compare the symbols stored in the second buffer portion with the encoded symbols stored in the first buffer portion and to compress the data. The encoder can operate in a first encoding mode to encode the symbols in the second buffer portion with corresponding codewords until detecting a repeated pattern of symbols in the second buffer portion that matches the encoded symbols in the first buffer portion. The encoder can operate in a second encoding mode responsive to detecting the repeated pattern. | 09-09-2010 |
20100309726 | REFERENCE VOLTAGE OPTIMIZATION FOR FLASH MEMORY - A system includes a voltage generator and a reference voltage setting module. The voltage generator is configured to generate K voltages to be applied to memory cells. The K voltages are used to determine a reference voltage used to read the memory cells, where K is an integer greater than 1. The reference voltage setting module is configured to selectively set the reference voltage to a value between two adjacent ones of the K voltages or one of the two adjacent ones of the K voltages. | 12-09-2010 |
20110055664 | SYSTEMS AND METHODS FOR COMPRESSING DATA IN NON-VOLATILE SEMICONDUCTOR MEMORY DRIVES - A non-volatile semiconductor memory (NVSM) storage system includes a NVSM drive interface configured to receive host data sectors (HDSs) from a host interface. A buffer managing module is configured to store the HDSs in a buffer. A compression module is configured to compress the HDSs to generate compressed HDSs of different lengths. A drive data sector (DDS) generating module is configured to add nuisance data to the compressed HDSs to generate DDSs. The DDSs are stored in NVSM. | 03-03-2011 |
20110082976 | METHOD AND SYSTEM FOR OBJECT-ORIENTED DATA STORAGE - In accordance with the present invention, data may be written and read differently in accordance with their attributes, which may include, inter alia, critical vs. non-critical data, streaming vs. non-streaming media, confidential vs. non-confidential, or read or write speed requirements. A data block to be written may be considered an object, and is examined, and from its attributes one or more memory device operating modes may be determined, such as different numbers of bits per cell, different numbers of error-correction code (ECC) parities per user data block, and encryption vs. lack of encryption. The storage controller then performs the writing process according to the mode(s) of operation determined by the attributes. Respective designated portions of the storage device may be selectively operated in respective ones of a plurality of operating modes to process each of the plurality of data objects based on a corresponding one or more of the attributes. | 04-07-2011 |
20110145681 | SOFT DECODING FOR QUANTIZIED CHANNEL - Systems, methods, and other embodiments associated with soft decoding for a quantized channel are described. According to one embodiment, an apparatus includes a soft decoder configured to decode a signal received from a quantized channel based, at least in part, on one or more log likelihood ratios (LLRs). The apparatus may also include a reliability memory configured to store one or more known LLRs, and a controller configured to repetitively and selectively provide the soft decoder with known LLRs chosen from the reliability memory, to control the soft decoder to decode the signal, and to selectively update the reliability memory upon determining that the soft decoder successfully decoded the signal. | 06-16-2011 |
20110202711 | ADAPTIVE READ AND WRITE SYSTEMS AND METHODS FOR MEMORY CELLS - An apparatus including: a plurality of multi-level memory cells configured to store data, wherein one or more of the multi-level memory cells are designated as pilot memory cells, and wherein each pilot memory cell is configured to store known, pre-determined data; an estimation block configured to, based on the known, pre-determined data, determine (i) estimated mean values of level distributions of the multi-level memory cells and (ii) estimated standard deviation values of level distributions of the multi-level memory cells; and a computation block configured to compute at least optimal or near optimal detection threshold values of level distributions of the multi-level memory cells based, at least in part, on (i) the estimated mean values and (ii) the estimated standard deviation values, wherein the optimal or near optimal detection threshold values are to be used in order to facilitate reading of the data stored in the multi-level memory cells. | 08-18-2011 |
20120008386 | Determining Optimal Reference Voltages For Progressive Reads In Flash Memory Systems - A system including a reference voltage module to select a first reference voltage between a first threshold voltage corresponding to a first state of a memory cell and a second threshold voltage corresponding to a second state of the memory cell, a second reference voltage less than the first reference voltage, and a third reference voltage greater than the first reference voltage. The system includes a read module to perform a first read operation to determine a state of the memory cell based on the first reference voltage, and in response to a first failure to decode data read from the memory cell in the first read operation, perform a second read operation to determine the state based on the second reference voltage and a third read operation to determine the state based on the third reference voltage. | 01-12-2012 |
20120102295 | DATA COMPRESSION AND ENCODING IN A MEMORY SYSTEM - Embodiments provide a method comprising receiving input data comprising a plurality of data sectors; compressing the plurality of data sectors to generate a corresponding plurality of compressed data sectors; splitting a compressed data sector of the plurality of compressed data sectors to generate a plurality of split compressed data sectors; and storing the plurality of compressed data sectors, including the plurality of split compressed data sectors, in a plurality of memory pages of a memory. | 04-26-2012 |
20120110410 | METHODS AND SYSTEMS FOR ENCODING AND DECODING IN TRELLIS CODED MODULATION SYSTEMS - Systems and methods for encoding and decoding for communications or storage systems utilizing coded modulation are provided. A first portion of data is encoded with a first at least one encoding scheme. A second portion of the data id encoded with a second encoding scheme. A coset is selected from a plurality of cosets based at least in part on the encoded first portion of the data, where the plurality of cosets corresponds to a partition of a signal constellation. A signal vector is selected within the selected coset based at least in part on the encoded second portion of the data. | 05-03-2012 |
20120119928 | SYSTEMS AND METHODS FOR PERFORMING EFFICIENT DECODING USING A HYBRID DECODER - Systems and methods for decoding data using a hybrid decoder are provided. A data signal that includes a codeword is received. A signal quality indicator for the data signal is computed. One of a plurality of decoders is selected based on the computed signal quality indicator. Each of the plurality of decoders is configured to decode information based on a different decoding technique. The codeword included in the data signal is decoded using the selected one of the plurality of decoders. | 05-17-2012 |
20120198135 | Mapping Data to Non-Volatile Memory - The present disclosure includes systems and techniques relating to non-volatile memory. A described system, for example, includes a non-volatile memory structure having a plurality of multi-level memory cells, a processing device, and a controller. The controller is configured to map a first portion of a first set of consecutive bits of a data segment to a first page associated with the plurality of multi-level memory cells, and map a second portion of the first set of consecutive bits of the data segment to a second page associated with the plurality of multi-level memory cells. The first page is associated with bits of a first significance, and the second page is associated with bits of a second significance. | 08-02-2012 |
20120198308 | METHODS AND SYSTEMS FOR EFFICIENT DECODING OF CONCATENATED ERROR CORRECTION CODES - Decoding data received includes decoding the received data using a first error correcting circuitry that decodes data in accordance with a first decoding process, terminating execution of the first decoding process used to correct the data before the first error correcting circuitry completes executing the first, decoding process and outputting partially decoded data, determining whether partially decoded data requires further decoding, and in response to determining whether partially decoded data requires further decoding, decoding the partially decoded data using a second error correcting circuitry that decodes data in accordance with a second decoding process. A system decodes data in accordance with the method. | 08-02-2012 |
20120198314 | SOFT DECODING SYSTEMS AND METHODS FOR FLASH BASED MEMORY SYSTEMS - Systems and methods for decoding data using a decoder that includes a primary decoder and an auxiliary decoder are provided. A codeword is retrieved from a storage device. A primary decoder attempts to decode the codeword using hard data associated with the codeword. If the primary decoder fails, an indication of the failure may be received by a decoder controller, which activates an auxiliary decoder. The auxiliary decoder attempts to decode the codeword using either hard data or soft data associated with the codeword. The primary decoder is designed to consume less power, consume less silicon area, and have a higher throughput than the auxiliary decoder. The primary decoder is configured to have a higher probability of successfully decoding a codeword, stored in the storage device, in the first attempt to decode the codeword, than failing and requiring the auxiliary decoder to decode the codeword. | 08-02-2012 |
20120213001 | RELIABILITY METRICS MANAGEMENT FOR SOFT DECODING - Embodiments provide a method for reading a target memory sector of a memory. The method comprises, based on read data corresponding to a plurality of memory sectors of the memory, estimating first one or more reference voltages and, using the first one or more reference voltages, performing a first read operation on the target memory sector. The method further comprises determining an error correcting code (ECC) decoding failure of the first read operation and, in response to determining the ECC decoding failure of the first read operation and based on read data corresponding to the target memory sector, updating the estimate of the first one or more reference voltages to generate second one or more reference voltages. The method also comprises using the second one or more reference voltages, performing a second read operation on the target memory sector. | 08-23-2012 |
20120236655 | Reference Voltage Optimization for Flash Memory - A system includes a voltage generator and a reference voltage setting module. The voltage generator is configured to generate K voltages to be applied to memory cells. The K voltages are used to determine a reference voltage used to read the memory cells, where K is an integer greater than 1. The reference voltage setting module is configured to selectively set the reference voltage to a value between two adjacent ones of the K voltages or one of the two adjacent ones of the K voltages. | 09-20-2012 |
20120290798 | Data Compression and Compacting for Memory Devices - Embodiments of the present disclosure provide apparatuses and methods for determining a compacting arrangement to store logical addressable units, which include compressed data sectors, into hardware addressable units of a storage device. The compacting arrangement is based on compression information associated with the logical addressable units. A write module is used to write the compressed data sectors to the storage device according to the compacting arrangement. | 11-15-2012 |
20120300545 | SYSTEMS AND METHODS FOR GENERATING SOFT INFORMATION IN NAND FLASH - Systems and methods are provided to generate soft information related to the threshold voltage of a memory cell. A range of threshold voltages for the memory cell is divided into subregions of threshold voltage values herein referred to as bins. An output of the memory cell in response to an applied reference signal is measured. The applied reference signal includes a voltage value and position information. A single bin is identified based on the position information of the reference signal. The identified bin is split into more than one bin based on the output of the memory cell and the voltage value of the reference signal. The newly split bins and all the other bins that were not split are assigned new bin indices. | 11-29-2012 |
20120331368 | SYSTEMS AND METHODS FOR PERFORMING CONCATENATED ERROR CORRECTION - A system and method is provided for performing concatenated error correction. In one implementation, an apparatus for encoding data includes an outer encoder to generate a code word corresponding to received input data and a parity circuit to compute parities of logical cells of data, the logical cells of data being obtained from the code word and having a first logical cell. The apparatus also includes an inner encoder to generate an error correction bit for the first logical cell based on a first parity corresponding to the first logical cell, and to insert the error correction bit in the first logical cell. | 12-27-2012 |
20130117637 | ADAPTIVE SYSTEMS AND METHODS FOR STORING AND RETRIEVING DATA TO AND FROM MEMORY CELLS - Adaptive systems include a memory device including a plurality of memory cells, a data quality monitoring block, and an adaptive data encoding block, the data quality monitoring block and the adaptive data encoding block both being operatively coupled to the memory device. The data quality monitoring block is configured to determine a quality value of a group of one or more memory cells included in the memory device, the determined quality value being indicative of a quality of the group of one or more memory cells. The adaptive data encoding block is configured to select a coding scheme from a plurality of coding schemes to encode data to be written to the group of one or more memory cells in the memory device, the selection of the coding scheme being based at least in part on the determined quality value of the group of one or more memory cells. | 05-09-2013 |
20130219104 | METHOD AND APPARATUS FOR COMPRESSING DATA SECTORS IN STORAGE DRIVE - A storage drive includes a non-volatile semiconductor memory, and interface, a compression module, a sector module, and a control module. The interface is configured to receive first data sectors transmitted from a host to the storage drive. The compression module is configured to compress the first data sectors to generate second data sectors. Lengths of the second data sectors vary. The first sector module is configured to generate third data sectors by adding nuisance data to (i) the second data sectors, or (ii) an encrypted version of the second data sectors, wherein lengths of the third data sectors do not vary. The control module is configured to store the third data sectors in the non-volatile semiconductor memory. | 08-22-2013 |
20130223146 | REFERENCE VOLTAGE OPTIMIZATION FOR FLASH MEMORY - A system including a reference voltage module to generate one or more reference voltages used to determine states of a plurality of memory cells of a nonvolatile memory. The memory cells have a threshold voltage distribution. A divider module selects, in response to a change in the threshold voltage distribution, a voltage range within which to update one of the reference voltages, and divide the voltage range into a plurality of regions. A counting module counts a number of the memory cells having threshold voltages within each of the plurality of regions. An update module selects one of the plurality of regions having the threshold voltages of a smallest number of the memory cells, and updates the one of the reference voltages to a voltage value associated with the selected one of the plurality of regions to compensate for the change in the threshold voltage distribution. | 08-29-2013 |
20130229869 | ACCESSING MEMORY USING REFERENCE VOLTAGES - Devices, systems, methods, and other embodiments associated with accessing memory using fractional reference voltage are described. In one embodiment, an apparatus includes comparison logic. The comparison logic compares a threshold voltage of a memory cell to at least one pair of reference voltages that are near an integral reference voltage to generate comparison results. The apparatus includes read logic to determine a bit value of the memory cell based, at least in part, on the comparison results. | 09-05-2013 |
20130297985 | DATA RECOVERY IN SOLID STATE MEMORY DEVICES - Embodiments herein provide data recovery techniques and configurations for solid state memory devices. For example, a method includes identifying a hard error associated with a cell of a solid state memory device, providing a location of the cell having the identified hard error to a decoder to recover data originally programmed to the cell, and recovering the data originally programmed to the cell using the decoder. Other embodiments may be described and/or claimed. | 11-07-2013 |
20140026014 | SOFT DECODING FOR QUANTIZIED CHANNEL - Systems, methods, and other embodiments associated with soft decoding for a quantized channel are described. According to one embodiment, a method includes repetitively controlling the soft decoder to attempt to decode the signal based, at least in part, on a reliability measure selected from a pre-determined collection of reliability measures. When the soft decoder fails to decode the signal, the method includes computing a new reliability measure and repetitively controlling the soft decoder to attempt to decode the signal based, at least in part, on the new reliability measure. When the soft decoder decodes the signal with the new reliability measure, the method includes adding the new reliability to the pre-determined collection of reliability measures. | 01-23-2014 |
20140126294 | UPDATING REFERENCE VOLTAGES TO COMPENSATE FOR CHANGES IN THRESHOLD VOLTAGE DISTRIBUTIONS OF NONVOLATILE MEMORY CELLS - A system including a reference voltage module configured to generate one or more reference voltages for determining states of a plurality of memory cells of a nonvolatile memory, where the plurality of memory cells have a threshold voltage distribution. A divider module divides, in response to a change in the threshold voltage distribution, a voltage range into a plurality of regions. An update module updates, to compensate for the change in the threshold voltage distribution, one of the reference voltages to a voltage value associated with one of the plurality of regions. | 05-08-2014 |
20140157068 | PROGRAMMING NONVOLATILE MEMORY BASED ON STATISTICAL ANALYSIS OF CHARGE LEVEL DISTRIBUTIONS OF MEMORY CELLS - A system includes a read module, a statistical data generating module, and a storing module. The read module reads charge levels of nonvolatile memory cells and generates read signals. The statistical data generating module generates statistical data based on the read signals. The storing module stores the statistical data. The read module generates the read signals based on the charge levels of the nonvolatile memory cells and the statistical data. | 06-05-2014 |
20140160855 | SYSTEMS AND METHODS FOR GENERATING SOFT INFORMATION IN NAND FLASH - Systems and methods are provided to generate soft information related to the threshold voltage of a memory cell. A range of threshold voltages for the memory cell is divided into subregions of threshold voltage values herein referred to as bins. An output of the memory cell in response to an applied reference signal is measured. The applied reference signal includes a voltage value and position information. A single bin is identified based on the position information of the reference signal. The identified bin is split into more than one bin based on the output of the memory cell and the voltage value of the reference signal. The newly split bins and all the other bins that were not split are assigned new bin indices. | 06-12-2014 |
20140185386 | Reliability Metrics Management for Soft Decoding - Embodiments provide a method for reading a target memory sector of a memory. The method comprises, based on read data corresponding to a plurality of memory sectors of the memory, estimating first one or more reference voltages and, using the first one or more reference voltages, performing a first read operation on the target memory sector. The method further comprises determining an error correcting code (ECC) decoding failure of the first read operation and, in response to determining the ECC decoding failure of the first read operation and based on read data corresponding to the target memory sector, updating the estimate of the first one or more reference voltages to generate second one or more reference voltages. The method also comprises using the second one or more reference voltages, performing a second read operation on the target memory sector. | 07-03-2014 |
20140321204 | METHOD AND APPARATUS FOR OPTIMIZING REFERENCE VOLTAGES IN A NONVOLATILE MEMORY - A system including a divider module, a read module, a counting module, and a reference voltage setting module. The divider module is configured to select a voltage range in which to adjust a reference voltage used to read memory cells of nonvolatile memory, and to divide the voltage range into a plurality of bins, where each of the bins is defined by a pair of voltages. The read module is configured to perform a plurality of read operations by applying, to the memory cells, the voltages defining the bins. The counting module is configured to generate, in each of the read operations, counts of a number of memory cells having threshold voltages in each of the bins. The reference voltage setting module is configured to adjust, based on the counts, the reference voltage to a voltage selected from one or more voltages associated with the bins. | 10-30-2014 |
20140372687 | MAPPING DATA TO NON-VOLATILE MEMORY - An apparatus includes, in at least one aspect, a memory interface configured to connect with a plurality of multi-level memory cells and a circuitry coupled with the memory interface. The plurality of multi-level memory cells include a first page and a second page. The first page is associated with bits of a first significance. The second page is associated with bits of a second significance. The circuitry is configured to map a first portion of an encoded data sector to the first page and map a second portion of the encoded data sector to the second page. The first portion excludes the second portion and the second portion excludes the first portion such that each of the first page and the second page contains different data from the encoded data sector. | 12-18-2014 |