Patent application number | Description | Published |
20080199813 | Method for forming a photoresist pattern on a semiconductor wafer using oxidation-based catalysis - According to one exemplary embodiment, a method for forming a photoresist pattern on a semiconductor wafer includes forming a photoresist including an organic polymer matrix on the semiconductor wafer. The method further includes exposing the photoresist to a patterned radiation. The method further includes baking the photoresist after exposing the photoresist to the pattern radiation. The method further includes applying an oxidizing reagent to the photoresist to create the photoresist pattern corresponding to the patterned radiation. | 08-21-2008 |
20080225245 | EUV debris mitigation filter and method for fabricating semiconductor dies using same - According to one exemplary embodiment, an extreme ultraviolet (EUV) source collector module for use in a lithographic tool comprises an EUV debris mitigation filter. The EUV debris mitigation filter can be in the form of an aerogel film, and can be used in combination with an EUV debris mitigation module comprising a combination of conventional debris mitigation techniques. The EUV debris mitigation filter protects collector optics from contamination by undesirable debris produced during EUV light emission, while advantageously providing a high level of EUV light transmittance. One disclosed embodiment comprises implementation of an EUV debris mitigation filter in an EUV source collector module utilizing a discharge-produced plasma (DPP) light source. One disclosed embodiment comprises implementation of an EUV debris mitigation filter in an EUV source collector module utilizing a laser-produced plasma (LPP) light source. | 09-18-2008 |
20080233494 | Method for forming a high resolution resist pattern on a semiconductor wafer - In one disclosed embodiment, a method for forming a high resolution resist pattern on a semiconductor wafer involves forming a layer of resist comprising, for example a polymer matrix and a catalytic species, over a material layer formed over a semiconductor wafer; exposing the layer of resist to patterned radiation; and applying a magnetic field to the semiconductor wafer during a post exposure bake process. In one embodiment, the patterned radiation is provided by an extreme ultraviolet (EUV) light source. In other embodiments, the source of patterned radiation can be an electron beam, or ion beam, for example. In one embodiment, the polymer matrix is an organic polymer matrix such as, for example, styrene, acrylate, or methacrylate. In one embodiment, the catalytic species can be, for example, an acid, a base, or an oxidizing agent. | 09-25-2008 |
20080292996 | Method for producing a high resolution resist pattern on a semiconductor wafer - In one disclosed embodiment, a method for producing a high resolution resist pattern on a semiconductor wafer comprises depositing a blanket layer of material on a semiconductor wafer, forming a resist interaction substrate on the blanket layer of material, forming a resist layer of a pre-determined thickness on the resist interaction substrate, exposing the resist layer to a patterned radiation, and developing the resulting high resolution resist pattern. In one embodiment, patterned radiation is provided by an extreme ultraviolet (EUV) light source. In other embodiments, patterned radiation may be provided by an electron beam, or ion beam, for example. In one embodiment, the resist layer comprises a chemically amplified resist utilizing a photogenerated acid (PGA), and having a sublayer. In other embodiments, the resist layer includes an additive, for example, fullerite. One disclosed embodiment involves use of an ultra-thin resist layer in combination with a gold resist interaction substrate. | 11-27-2008 |
20090011524 | Method for determining suitability of a resist in semiconductor wafer fabrication - In one disclosed embodiment, the present method for determining resist suitability for semiconductor wafer fabrication comprises forming a layer of resist over a semiconductor wafer, exposing the layer of resist to patterned radiation, and determining resist suitability by using a scatterometry process prior to developing a lithographic pattern on the layer of resist. In one embodiment, the semiconductor wafer is heated in a post exposure bake process after scatterometry is performed. In one embodiment, the patterned radiation is provided by an extreme ultraviolet (EUV) light source in a lithographic process. In other embodiments, patterned radiation is provided by an electron beam, or ion beam, for example. In one embodiment, the present method determines out-gassing of a layer of resist during exposure to patterned radiation. | 01-08-2009 |
Patent application number | Description | Published |
20080292991 | HIGH FIDELITY MULTIPLE RESIST PATTERNING - An integrated circuit fabrication process as described herein employs a double photoresist exposure technique. After creation of a first pattern of photoresist features on a wafer, a second photoresist layer is formed over the first pattern of photoresist features. The second photoresist layer is subjected to a reflow step that softens and relaxes the second photoresist material. This reflow step causes the exposed surface of the second photoresist layer to become substantially planar. Thereafter, the second photoresist layer can be exposed and developed to create a second pattern of photoresist features on the wafer. The planar surface of the second photoresist layer, which results from the reflow step, facilitates the creation of accurate, precise, and “high fidelity” photoresist features from the second photoresist material. | 11-27-2008 |
20090017628 | SPACER LITHOGRAPHY - Ultrafine dimensions are accurately and efficiently formed in a target layer using a spacer lithographic technique comprising forming a first mask pattern, forming a cross-linkable layer over the first mask pattern, forming a cross-linked spacer between the first mask pattern and cross-linkable layer, removing the cross-linkable layer, cross-linked spacer from the upper surface of the first mask pattern and the first mask pattern to form a second mask pattern comprising remaining portions of the cross-linked spacer, and etching using the second mask pattern to form an ultrafine pattern in the underlying target layer. Embodiments include forming the first mask pattern from a photoresist material capable of generating an acid, depositing a cross-linkable material comprising a material capable of undergoing a cross-linking reaction in the presence of an acid, and removing portions of the non-cross-linked layer and cross-linked spacer from the upper surface of the first mask pattern before removing the remaining portions of the first mask pattern and remaining noncross-linked layer. | 01-15-2009 |
20090023298 | INVERSE SELF-ALIGNED SPACER LITHOGRAPHY - Ultrafine dimensions, smaller than conventional lithographic capabilities, are formed employing an efficient inverse spacer technique comprising selectively removing spacers. Embodiments include forming a first mask pattern over a target layer, forming a spacer layer on the upper and side surfaces of the first mask pattern leaving intermediate spaces, depositing a material in the intermediate spacers leaving the spacer layer exposed, selectively removing the spacer layer to form a second mask pattern having openings exposing the target layer, and etching the target layer through the second mask pattern. | 01-22-2009 |
20100099045 | METHODS FOR PERFORMING PHOTOLITHOGRAPHY USING BARCS HAVING GRADED OPTICAL PROPERTIES - Photolithography methods using BARCs having graded optical properties are provided. In an exemplary embodiment, a photolithography method comprises the steps of depositing a BARC overlying a material to be patterned, the BARC having a refractive index and an absorbance. The BARC is modified such that, after the step of modifying, values of the refractive index and the absorbance are graded from first values at a first surface of the BARC to second values at a second surface of the BARC. The step of modifying is performed after the step of depositing. | 04-22-2010 |
20140178824 | OPTIMIZING LITHOGRAPHIC PROCESSES USING LASER ANNEALING TECHNIQUES - Approaches for utilizing laser annealing to optimize lithographic processes such as directed self assembly (DSA) are provided. Under a typical approach, a substrate (e.g., a wafer) will be subjected to a lithographic process (e.g., having a set of stages/phases, aspects, etc.) such as DSA. Before or during such process, a set of laser annealing passes/scans will be made over the substrate to optimize one or more of the stages. In addition, the substrate could be subjected to additional processes such as hotplate annealing, etc. Still yet, in making a series of laser annealing passes, the techniques utilized and/or beam characteristics of each pass could be varied to further optimize the results. | 06-26-2014 |