Patent application number | Description | Published |
20100008378 | Ethernet Controller Implementing a Performance and Responsiveness Driven Interrupt Scheme - A method of generating frame receive interrupts in an Ethernet controller including receiving incoming data frames and storing data frames into a receive queue, monitoring the number of received data frames, and when the number of received data frames exceeds a first threshold, generating a frame receive interrupt. In another embodiment, the method further includes monitoring the amount of received data stored in the receive queue and generating a frame receive interrupt when the first threshold is exceeded and when the amount of received data stored in the receive queue exceeds a second threshold. In yet another embodiment, the method further includes monitoring the time duration of the data frames stored in the receive queue, and generating a frame receive interrupt when the number of received data frames exceeds the first threshold or when the time duration of the data frames stored in the receive queue exceeds a third threshold. | 01-14-2010 |
20100011140 | Ethernet Controller Using Same Host Bus Timing for All Data Object Access - An Ethernet controller has a host interface for coupling to a host processor and a physical layer transceiver for coupling to a data network and includes multiple data objects having different access times where the data objects communicate with the host interface over an internal data bus. The Ethernet controller includes a data object interface module coupled between the host interface and the internal data bus where the data object interface module has a first access time for handling data requests for the data objects received on the host interface from the host processor, and a control logic circuit coupled to control the operation of the data object interface module. Data requests from the host processor for accessing data stored in the multiple data objects are carried out through the data object interface module using the first access time, regardless of the different access times of the multiple data objects. | 01-14-2010 |
20100020809 | True Ring Networks Using Tag VLAN Filtering - A method in a network device configured in a true ring network where the network device has a first port and a second port connected to the true ring network and a third port connected to a processor including: connecting the network device to transmit data packets in a single direction around the true ring network including an ingress port and an egress port; enabling ingress tag VLAN filtering on the ingress port only; configuring a VLAN table in the network device to terminate an incoming data packet when a VID tag (VLAN identifier tag) of the incoming data packet matches the local VID tag of the network device; and configuring the VLAN table in the network device to accept the incoming data packet when the VID tag of the incoming data packet does not match the local VID tag of the network device. | 01-28-2010 |
20100202470 | Dynamic Queue Memory Allocation With Flow Control - A method in an Ethernet controller for allocating memory space in a buffer memory between a transmit queue (TXQ) and a receive queue (RXQ) includes allocating initial memory space in the buffer memory to the RXQ and the TXQ; defining a RXQ high watermark and a RXQ low watermark; receiving an ingress data frame; determining if a memory usage in the RXQ exceeds the RXQ high watermark; if the RXQ high watermark is not exceeded, storing the ingress data frame in the RXQ; if the RXQ high watermark is exceeded, determining if there are unused memory space in the TXQ; if there are no unused memory space in the TXQ, transmitting a pause frame to halt further ingress data frame; if there are unused memory space in the TXQ, allocating unused memory space in the TXQ to the RXQ; and storing the ingress data frame in the RXQ. | 08-12-2010 |
Patent application number | Description | Published |
20090085127 | NON-VOLATILE SEMICONDUCTOR MEMORY BASED ON ENHANCED GATE OXIDE BREAKDOWN - A semiconductor memory structure based on gate oxide break down is constructed in a deep N-well. Thus, the electrical field over the programmable element during the transient procedure of gate oxide break down can be controlled to achieve the best memory programming results. The conductivity of the programmed memory cell is increased greatly and conductivity variation between the memory cells is reduced. This is achieved by adding a body bias during the programming process. The body here refers to a P-well formed within the deep N-Well. Furthermore, the read voltage offset is reduced greatly with this new memory configuration. These improved programming results will allow faster read speed and lower read voltage. This new structure also reduces current leakage from a memory array during programming. | 04-02-2009 |
20100054048 | METHOD AND APPARATUS FOR PROGRAMMING AUTO SHUT-OFF - A method and system for enabling auto shut-off of programming of a non-volatile memory cell is disclosed. The system includes a memory array having a plurality of memory cells, each cell storing one bit of data. During the programming process, programming signals are applied to the target memory cells. A predefined period of time after the programming signals are applied, the auto shut-off system begins sensing an output signal from the memory cell. After the system detects an output signal from the memory cell, the system waits for a second predefined period of time before turning off the programming voltages. The system may be configured to sense an output voltage from the memory cell. The system then compares the output voltage to a reference voltage in order to detect when the cell is programmed. Alternatively, the system may sense an output current from the memory cell. The system then compares the output current to a reference current to detect when the cell is programmed. | 03-04-2010 |
20110309421 | ONE-TIME PROGRAMMABLE MEMORY AND METHOD FOR MAKING THE SAME - A one time programmable nonvolatile memory formed from metal-insulator-semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting doped semiconductor lines formed in a semiconductor substrate. | 12-22-2011 |
20130161761 | ONE-TIME PROGRAMMABLE MEMORY AND METHOD FOR MAKING THE SAME - A one time programmable nonvolatile memory formed from metal-insulator-semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting doped semiconductor lines formed in a semiconductor substrate. | 06-27-2013 |
Patent application number | Description | Published |
20090080275 | REDUCING BIT LINE LEAKAGE CURRENT IN NON-VOLATILE MEMORIES - In example embodiments, methods are provided for reducing bit line leakage current. In an example embodiment, an unselected program word line is biased to a bias voltage. The unselected program word line is connected to a memory cell and the memory cell includes a plurality of transistors. In another example embodiment, an unselected memory cell is biased to a negative bias voltage during read operations. | 03-26-2009 |
20110298054 | One-time programmable memory - The present invention provides a programmable memory array including a plurality of memory cells. At least one and preferably each memory cell of the plurality of memory cells include an isolation layer formed of a dielectric material, a field effect transistor, and a programmable element. The programmable element includes a conductive gate, a gate insulator present beneath the conductive gate, and a semiconductor body present under the gate insulator. The semiconductor body of the programmable element is of a different doping type then the doping of the channel region of the field effect transistor. Apart from these components, the memory cell also includes a bit line connected to the source of the field effect transistor, a select word line connected to the gate of the field effect transistor and a program word line connected to the conductive gate of the programmable element. | 12-08-2011 |
20140217484 | ONE-TIME PROGRAMMABLE MEMORY AND METHOD FOR MAKING THE SAME - A one time programmable nonvolatile memory formed from metal-insulator-semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting doped semiconductor lines formed in a semiconductor substrate. | 08-07-2014 |
20150311215 | One-Time Programmable Memory and Method for Making the Same - A one time programmable nonvolatile memory formed from metal-insulator semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting lines formed in a semiconductor substrate. | 10-29-2015 |
Patent application number | Description | Published |
20080230372 | Deposition system with electrically isolated pallet and anode assemblies - A system for substrate deposition. The system includes a wafer pallet and an anode. The wafer pallet has a bottom and a top. The top of the wafer pallet is configured to hold a substrate wafer. The anode has a substantially fixed position relative to the wafer pallet and is configured to move with the wafer pallet through the deposition chamber. The anode is electrically isolated from the substrate wafer. | 09-25-2008 |
20080283490 | PROTECTION LAYER FOR FABRICATING A SOLAR CELL - A method for fabricating a solar cell is described. The method includes first providing, in a process chamber, a substrate having a light-receiving surface. An anti-reflective coating (ARC) layer is then formed, in the process chamber, above the light-receiving surface of the substrate. Finally, without removing the substrate from the process chamber, a protection layer is formed above the ARC layer. | 11-20-2008 |
20090022572 | Cluster tool with a linear source - Systems and methods combining a cluster chamber with linear sources are described. A plurality of wafers is mounted on a pallet. A central robot in a cluster chamber moves the pallet among chambers connected to the cluster chamber chamber. At least one of the chambers connected to the cluster chamber includes a linear deposition source, the pallet moveable relative to the linear deposition source. | 01-22-2009 |
20090151784 | Anti-Reflective Coating With High Optical Absorption Layer For Backside Contact Solar Cells - A multilayer anti-reflection structure for a backside contact solar cell. The anti-reflection structure may be formed on a front side of the backside contact solar cell. The anti-reflection structure may include a passivation level, a high optical absorption layer over the passivation level, and a low optical absorption layer over the high optical absorption layer. The passivation level may include silicon dioxide thermally-grown on a textured surface of the solar cell substrate, which may be an N-type silicon substrate. The high optical absorption layer may be configured to block at least 10% of UV radiation coming into the substrate. The high optical absorption layer may comprise high-k silicon nitride and the low optical absorption layer may comprise low-k silicon nitride. | 06-18-2009 |
20100071765 | METHOD FOR FABRICATING A SOLAR CELL USING A DIRECT-PATTERN PIN-HOLE-FREE MASKING LAYER - A method for fabricating a solar cell is described. The method includes first providing a substrate having a dielectric layer disposed thereon. A pin-hole-free masking layer is then formed above the dielectric layer. Finally, without the use of a mask, the pin-hole-free masking layer is patterned to form a patterned pin-hole-free masking layer. | 03-25-2010 |
20100129955 | PROTECTION LAYER FOR FABRICATING A SOLAR CELL - A method for fabricating a solar cell is described. The method includes first providing, in a process chamber, a substrate having a light-receiving surface. An anti-reflective coating (ARC) layer is then formed, in the process chamber, above the light-receiving surface of the substrate. Finally, without removing the substrate from the process chamber, a protection layer is formed above the ARC layer. | 05-27-2010 |
20120073650 | METHOD OF FABRICATING AN EMITTER REGION OF A SOLAR CELL - Methods of fabricating emitter regions of solar cells are described. Methods of forming layers on substrates of solar cells, and the resulting solar cells, are also described. | 03-29-2012 |
20120255606 | ANTI-REFLECTIVE COATING WITH HIGH OPTICAL ABSORPTION LAYER FOR BACKSIDE CONTACT SOLAR CELLS - A multilayer anti-reflection structure for a backside contact solar cell. The anti-reflection structure may be formed on a front side of the backside contact solar cell. The anti-reflection structure may include a passivation level, a high optical absorption layer over the passivation level, and a low optical absorption layer over the high optical absorption layer. The passivation level may include silicon dioxide thermally grown on a textured surface of the solar cell substrate, which may be an N-type silicon substrate. The high optical absorption layer may be configured to block at least 10% of UV radiation coming into the substrate. The high optical absorption layer may comprise high-k silicon nitride and the low optical absorption layer may comprise low-k silicon nitride. | 10-11-2012 |
20140014499 | DEPOSITION SYSTEM WITH ELECTRICALLY ISOLATED PALLET AND ANODE ASSEMBLIES - A system for substrate deposition is disclosed. The system includes a wafer pallet and an anode. The wafer pallet has a bottom and a top. The top of the wafer pallet is configured to hold a substrate wafer. The anode has a substantially fixed position relative to the wafer pallet and is configured to move with the wafer pallet through the deposition chamber. The anode is electrically isolated from the substrate wafer. | 01-16-2014 |
20140373910 | ANTI-REFLECTIVE COATING WITH HIGH OPTICAL ABSORPTION LAYER FOR BACKSIDE CONTACT SOLAR CELLS - A multilayer anti-reflection structure for a backside contact solar cell. The anti-reflection structure may be formed on a front side of the backside contact solar cell. The anti-reflection structure may include a passivation level, a high optical absorption layer over the passivation level, and a low optical absorption layer over the high optical absorption layer. The passivation level may include silicon dioxide thermally grown on a textured surface of the solar cell substrate, which may be an N-type silicon substrate. The high optical absorption layer may be configured to block at least 10% of UV radiation coming into the substrate. The high optical absorption layer may comprise high-k silicon nitride and the low optical absorption layer may comprise low-k silicon nitride. | 12-25-2014 |
Patent application number | Description | Published |
20110027261 | ANTI-HEPCIDIN ANTIBODIES AND USES THEREOF - Monoclonal antibodies are provided that selectively bind human hepcidin-25 and are characterized as having high affinity for human hepcidin-25 and strong human mature hepcidin neutralizing properties. The antibodies of the invention are useful therapeutically for increasing serum iron levels, reticulocyte count, red blood cell count, hemoglobin, and/or hematocrit in a human and for the treatment and diagnosis of mature hepcidin-promoted disorders such as anemia, in a human subject. | 02-03-2011 |
20130122013 | ANTI-FERROPORTIN 1 MONOCLONAL ANTIBODIES AND USES THEREOF - Provided are monoclonal antibodies and antigen-binding fragments thereof that bind to, and inhibit the activity of human FPN1, and which are effective in maintaining or increasing the transport of iron out of mammalian cells and/or maintaining or increasing the level of serum iron, reticulocyte count, red blood cell count, hemoglobin, and/or hematocrit in a subject in vivo. | 05-16-2013 |
20130164304 | ANTI-HEPCIDIN ANTIBODIES AND USES THEREOF - Monoclonal antibodies are provided that selectively bind human hepcidin-25 and are characterized as having high affinity for human hepcidin-25 and strong human mature hepcidin neutralizing properties. The antibodies of the invention are useful therapeutically for increasing serum iron levels, reticulocyte count, red blood cell count, hemoglobin, and/or hematocrit in a human and for the treatment and diagnosis of mature hepcidin-promoted disorders such as anemia, in a human subject. | 06-27-2013 |
Patent application number | Description | Published |
20110197431 | Manufacturing Methods for a Triple Layer Winding Pattern - A method of manufacturing a triple-winding layer arrangement for a three-phase, four pole motor is provided. | 08-18-2011 |
20110198960 | Dual Layer Winding Pattern and Methods of Manufacturing Same - A dual-winding layer arrangement for a three-phase, four pole motor is provided as well as a method of manufacturing the same. | 08-18-2011 |
20110198961 | Triple Layer Winding Pattern and Methods of Manufacturing Same - A triple-winding layer arrangement for a three-phase, four pole motor is provided as well as a method of manufacturing the same. | 08-18-2011 |
20110198963 | Dual Layer Winding Pattern - A dual-winding layer arrangement for a three-phase, four pole motor is provided. | 08-18-2011 |
20140339950 | Rotor Assembly with Electron Beam Welded End Caps - A rotor assembly and a method for fabricating the same are provided in which a pair of end caps, positioned at either end of the stack of laminated discs, are fusion welded to the rotor bars using an electron beam welder, thereby yielding improved electrical and mechanical characteristics in a low weight assembly. | 11-20-2014 |
20140375166 | Controlling End Ring Balance in Pre-Balancing Spinning Process - A rotor includes: a shaft; a core around the shaft; at least one end ring connected to rotor bars that are at least partially enclosed in the core; and means for balancing the end ring around the shaft in a pre-balancing spinning process. A method includes: assembling rotor bars so that they are at least partially enclosed in a core of a rotor; connecting an end ring to ends of the rotor bars; inserting a shaft into the core; step for balancing the end ring around the shaft in a pre-balancing spinning process that involves spinning the rotor; and spinning the rotor in the pre-balancing spinning process. | 12-25-2014 |
Patent application number | Description | Published |
20120210043 | Systems and Methods for Managing Data Input/Output Operations - Systems and methods for managing data input/output operations are described. In one aspect, a device driver identifies a data read operation generated by a virtual machine in a virtual environment. The device driver is located in the virtual machine and the data read operation identifies a physical cache address associated with the data requested in the data read operation. A determination is made regarding whether data associated with the data read operation is available in a cache associated with the virtual machine. | 08-16-2012 |
20120210066 | SYSTEMS AND METHODS FOR A FILE-LEVEL CACHE - A multi-level cache comprises a plurality of cache levels, each configured to cache I/O request data pertaining to I/O requests of a different respective type and/or granularity. The multi-level cache may comprise a file-level cache that is configured to cache I/O request data at a file-level of granularity. A file-level cache policy may comprise file selection criteria to distinguish cacheable files from non-cacheable files. The file-level cache may monitor I/O requests within a storage stage, and may service I/O requests from a cache device. | 08-16-2012 |
20120210068 | SYSTEMS AND METHODS FOR A MULTI-LEVEL CACHE - A multi-level cache comprises a plurality of cache levels, each configured to cache I/O request data pertaining to I/O requests of a different respective type and/or granularity. A cache device manager may allocate cache storage space to each of the cache levels. Each cache level maintains respective cache metadata that associates I/O request data with respective cache address. The cache levels monitor I/O requests within a storage stack, apply selection criteria to identify cacheable I/O requests, and service cacheable I/O requests using the cache storage device. | 08-16-2012 |
20120304171 | Managing Data Input/Output Operations - Systems and methods for managing data input/output operations are described that include virtual machines operating with a shared storage within a host. In such a system, a computer-implemented method is provided for dynamically provisioning cache storage while operating system applications continue to operate, including stalling the virtual machine's local cache storage operations, changing the provision of cache storage size; and resuming the operations of the virtual machine. | 11-29-2012 |
20130198459 | SYSTEMS AND METHODS FOR A DE-DUPLICATION CACHE - A de-duplication is configured to cache data for access by a plurality of different storage clients, such as virtual machines. A virtual machine may comprise a virtual machine de-duplication module configured to identify data for admission into the de-duplication cache. Data admitted into the de-duplication cache may be accessible by two or more storage clients. Metadata pertaining to the contents of the de-duplication cache may be persisted and/or transferred with respective storage clients such that the storage clients may access the contents of the de-duplication cache after rebooting, being power cycled, and/or being transferred between hosts. | 08-01-2013 |
20140012940 | Systems, Methods and Apparatus for a Virtual Machine Cache - A virtual machine cache provides for maintaining a working set of the cache during a transfer between virtual machine hosts. In response to the transfer, a previous host retains cache data of the virtual machine, which is provided to the new host of the virtual machine. The cache data may be transferred via a network transfer. | 01-09-2014 |
20140013059 | SYSTEMS, METHODS AND APPARATUS FOR CACHE TRANSFERS - A virtual machine cache provides for maintaining a working set of the cache during a transfer between virtual machine hosts. In response to a virtual machine transfer, the previous host of the virtual machine is configured to retain cache data of the virtual machine, which may include both cache metadata and data that has been admitted into the cache. The cache data may be transferred to the destination host via a network (or other communication mechanism). The destination host populates a virtual machine cache with the transferred cache data to thereby reconstruct the working state of the cache. | 01-09-2014 |
20140068183 | SYSTEMS, METHODS, AND INTERFACES FOR ADAPTIVE PERSISTENCE - A storage module may be configured to service I/O requests according to different persistence levels. The persistence level of an I/O request may relate to the storage resource(s) used to service the I/O request, the configuration of the storage resource(s), the storage mode of the resources, and so on. In some embodiments, a persistence level may relate to a cache mode of an I/O request. I/O requests pertaining to temporary or disposable data may be serviced using an ephemeral cache mode. An ephemeral cache mode may comprise storing I/O request data in cache storage without writing the data through (or back) to primary storage. Ephemeral cache data may be transferred between hosts in response to virtual machine migration. | 03-06-2014 |
20140068197 | SYSTEMS, METHODS, AND INTERFACES FOR ADAPTIVE CACHE PERSISTENCE - A storage module may be configured to service I/O requests according to different persistence levels. The persistence level of an I/O request may relate to the storage resource(s) used to service the I/O request, the configuration of the storage resource(s), the storage mode of the resources, and so on. In some embodiments, a persistence level may relate to a cache mode of an I/O request. I/O requests pertaining to temporary or disposable data may be serviced using an ephemeral cache mode. An ephemeral cache mode may comprise storing I/O request data in cache storage without writing the data through (or back) to primary storage. Ephemeral cache data may be transferred between hosts in response to virtual machine migration. | 03-06-2014 |
20140237147 | SYSTEMS, METHODS, AND INTERFACES FOR ADAPTIVE PERSISTENCE - A storage module may be configured to service I/O requests according to different persistence levels. The persistence level of an I/O request may relate to the storage resource(s) used to service the I/O request, the configuration of the storage resource(s), the storage mode of the resources, and so on. In some embodiments, a persistence level may relate to a cache mode of an I/O request. I/O requests pertaining to temporary or disposable data may be serviced using an ephemeral cache mode. An ephemeral cache mode may comprise storing I/O request data in cache storage without writing the data through (or back) to primary storage. Ephemeral cache data may be transferred between hosts in response to virtual machine migration. | 08-21-2014 |
20140281131 | SYSTEMS AND METHODS FOR PERSISTENT CACHE LOGGING - A cache log module stores an ordered log of cache storage operations sequentially within the physical address space of a non-volatile storage device. The log may be divided into segments, each comprising a set of log entries. Data admitted into the cache may be associated with respective log segments. Cache data may be associated with the log segment that corresponds to the cache storage operation in which the cache data was written into the cache. The backing store of the data may be synchronized to a particular log segment by identifying the cache data pertaining to the segment (using the associations), and writing the identified data to the backing store. Data lost from the cache may be recovered from the log by, inter alia, committing entries in the log after the last synchronization time of the backing store. | 09-18-2014 |
20150012692 | SYSTEMS AND METHODS FOR MANAGING DATA - Systems and methods for managing data input/output operations are described. In one aspect, a device driver identifies a data read operation generated by a virtual machine in a virtual environment. The device driver is located in the virtual machine and the data read operation identifies a physical cache address associated with the data requested in the data read operation. A determination is made regarding whether data associated with the data read operation is available in a cache associated with the virtual machine. | 01-08-2015 |
20150205535 | SYSTEMS AND METHODS FOR A FILE-LEVEL CACHE - A multi-level cache comprises a plurality of cache levels, each configured to cache I/O request data pertaining to I/O requests of a different respective type and/or granularity. The multi-level cache may comprise a file-level cache that is configured to cache I/O request data at a file-level of granularity. A file-level cache policy may comprise file selection criteria to distinguish cacheable files from non-cacheable files. The file-level cache may monitor I/O requests within a storage stage, and may service I/O requests from a cache device. | 07-23-2015 |
20150363324 | SYSTEMS AND METHODS FOR A DE-DUPLICATION CACHE - A de-duplication is configured to cache data for access by a plurality of different storage clients, such as virtual machines. A virtual machine may comprise a virtual machine de-duplication module configured to identify data for admission into the de-duplication cache. Data admitted into the de-duplication cache may be accessible by two or more storage clients. Metadata pertaining to the contents of the de-duplication cache may be persisted and/or transferred with respective storage clients such that the storage clients may access the contents of the de-duplication cache after rebooting, being power cycled, and/or being transferred between hosts. | 12-17-2015 |
20160062787 | SYSTEMS AND METHODS FOR MANAGING DATA INPUT/OUTPUT OPERATIONS IN A VIRTUAL COMPUTING ENVIRONMENT - Systems and methods for managing data input/output operations are described that include virtual machines operating with a shared storage within a host. In such a system, a computer-implemented method is provided for dynamically provisioning cache storage while operating system applications continue to operate, including stalling the virtual machine's local cache storage operations, changing the provision of cache storage size; and resuming the operations of the virtual machine. | 03-03-2016 |