Patent application number | Description | Published |
20100061005 | High speed digital signaling apparatus and method using reflected signals to increase total delivered current - A signaling apparatus and method are described that use reflected signals to increase the total current delivered to a receiver. Dynamic source-side transmission line termination control is employed to generate reflected signals that constructively add to a nonreflected signal to enhance the signal at the receiver. Switching controls selectively connect and disconnect the transmission line source-side termination resistors to either provide signal termination or remove it. Driver designs using either voltage or current sources for use in signaling systems (including, for example, magnetic storage devices with inductive coil based write heads) are described. | 03-11-2010 |
20100142096 | INTEGRATED SLIDER BIAS CONTROL - In a method of biasing a slider, a bias voltage is generated for biasing a slider. The bias voltage is integratedly coupled to a conductive body of the slider via an existing signal path of the slider such that the slider is biased with the bias voltage. The existing signal path is primarily used for conveying another signal to or from the slider but at least sometimes conveys the bias voltage to the conductive body in an integral fashion along with another signal. | 06-10-2010 |
20100157457 | Electrical Interconnect system with integrated transmission- line compensation components - Impedance compensation features are used along the transmission-line path between a transmitter/driver/source and the receiver/transducer to compensate for the impedance discontinuities or mismatches (for example, those caused by physical interconnection features) and/or to improve the frequency response of the signal transfer along the transmission line. The impedance compensation features are non-uniformities with impedance characteristics selected to compensate for the target impedance discontinuities. The compensation features can be non-uniformities (geometric structures designed to have specific impedance characteristics) in the electrically conductive traces that are integrated in the interconnect transmission line between the transmitter/driver/source and the receiver/transducer. The effective impedance level of the transmission line can be lowered or raised using the compensation features. | 06-24-2010 |
20110149443 | TUNABLE MICROSTRIP TRANSMISSION PATH IN A HARD DISK DRIVE - A disk pack, comprising at least one hard disk, is rotatably mounted to a housing. The disk pack defines an axis of rotation and a radial direction relative to the axis. At least one actuator mounted to the housing is coupled with a suspension and is movable relative to the disk pack. A slider, comprising a slider body and a head configured to read data from and write data to at least one hard disk, is coupled with the suspension. A first suspension electrical interconnect is configured to electrically couple a first signal conducting pathway with the slider and with a first non-terminated signal pathway. A second suspension electrical interconnect is configured to electrically couple a second signal conducting pathway with the slider and with a second non-terminated signal pathway. The length of the second non-terminated signal pathway is selected to achieve a desired impedance level. | 06-23-2011 |
20130124942 | Techniques For Storing Data in Stuck and Unstable Memory Cells - A data storage system includes a memory circuit and a control circuit. The control circuit is operable to receive data bits provided for storage in memory cells of the memory circuit. The control circuit is operable to compare each of the data bits provided for storage in a corresponding one of the memory cells having a stuck-at fault value to the stuck-at fault value. The control circuit is operable to generate encoded data bits by inverting each of the data bits having a different value than the stuck-at fault value of the corresponding one of the memory cells and by maintaining a digital value of each of the data bits having the stuck-at fault value of the corresponding one of the memory cells. The control circuit is operable to prevent any of the data bits from being stored in the memory cells determined to have unstable values. The control circuit is operable to generate redundant bits that indicate at least one operation to perform on the encoded data bits to regenerate the data bits. | 05-16-2013 |
20130124943 | Techniques For Storing Data in Stuck Memory Cells - A data storage system includes a memory circuit and a control circuit. The control circuit is operable to receive data bits provided for storage in memory cells of the memory circuit. The control circuit is operable to compare each of the data bits provided for storage in a corresponding one of the memory cells having a stuck-at fault to a value of the stuck-at fault, and to invert each of the data bits having a different value than the value of the stuck-at fault of the corresponding one of the memory cells to generate encoded data bits. The control circuit is operable to generate redundant bits that indicate the encoded data bits to invert to regenerate the data bits. | 05-16-2013 |
20140101516 | Encoding and Decoding Data to Accommodate Memory Cells Having Stuck-At Faults - A data storage system includes a memory circuit that has memory cells and a control circuit that is operable to receive data bits provided for storage in the memory cells. The control circuit is operable to receive a first matrix. Each row of the first matrix corresponds to a unique one of the data bits. The control circuit is operable to generate a second matrix having only the rows of the first matrix that correspond to the data bits provided for storage in a subset of the memory cells having stuck-at faults. The control circuit is operable to generate a third matrix having linearly independent columns of the second matrix. The control circuit is operable to encode the data bits to generate encoded data bits and redundant bits using the third matrix. | 04-10-2014 |
20140101517 | Encoding and Decoding Redundant Bits to Accommodate Memory Cells Having Stuck-At Faults - A data storage system has a memory circuit that comprises memory cells and a control circuit that receives data bits provided for storage in the memory cells. The control circuit encodes the data bits to generate a first set of redundant bits and encoded data bits, such that the encoded data bits selected for storage in a first subset of the memory cells with first stuck-at faults have digital values of corresponding ones of the first stuck-at faults. The control circuit encodes the first set of redundant bits to generate a second set of redundant bits. The control circuit performs logic functions on the second set of redundant bits and the encoded data bits to generate a third set of redundant bits, such that redundant bits in the third set of redundant bits selected for storage in a second subset of the memory cells with second stuck-at faults have digital values of corresponding ones of the second stuck-at faults. | 04-10-2014 |
20140164821 | Techniques For Encoding and Decoding Using a Combinatorial Number System - A data storage system includes a memory circuit having memory cells and a control circuit. The control circuit is operable to receive data bits provided for storage in the memory cells. A subset of the memory cells have predetermined stuck-at faults. The control circuit is operable to compute a binomial coefficient for each of the predetermined stuck-at faults based on a bit position of a corresponding one of the predetermined stuck-at faults within the memory cells. The control circuit is operable to add together the binomial coefficients to generate an encoded number using a combinatorial number system. The control circuit is operable to generate a first set of redundant bits that indicate the encoded number. The first set of redundant bits are used to decode bits read from the memory cells to regenerate the data bits. | 06-12-2014 |
20140164873 | Techniques For Storing Bits in Memory Cells Having Stuck-at Faults - A data storage system includes a memory circuit comprising memory cells and a control circuit. The control circuit generates a first set of redundant bits indicating bit positions of the memory cells having stuck-at faults in response to a first write operation if a first rate of the stuck-at faults in the memory cells is greater than a first threshold. The control circuit is operable to encode data bits to generate encoded data bits and a second set of redundant bits that indicate a transformation performed on the data bits to generate the encoded data bits in response to a second write operation if a second rate of stuck-at faults in the memory cells is greater than a second threshold. The encoded data bits stored in the memory cells having the stuck-at faults match digital values of corresponding ones of the stuck-at faults. | 06-12-2014 |
Patent application number | Description | Published |
20100007993 | INTEGRATED LEAD SUSPENSION WITH MULTIPLE CROSSOVER COPLANAR CONNECTION OF THE ELECTRICALLY CONDUCTIVE TRACES - An integrated lead suspension (ILS) or flexure has a connection scheme that allows for coplanar and interleaved conductive traces between read/write circuitry and a read/write head in a magnetic recording disk drive. The flexure has an electrically conductive substrate and insulator layer with the traces formed on the insulator layer. At each end of the flexure there is an island of substrate material with vias in the insulator layer that permit electrical connection to the islands. The conductive traces are grouped into two sets and extend generally parallel along the length of the flexure, with the traces from one set being interleaved with traces from the other set and each set carrying one of the positive or negative signals. At one of the ends, all of the traces from one set are connected through the vias to the island at that end, and at the other end all of the traces from the other set are connected through the vias to the island at that end. Each signal is distributed among the multiple traces of a set by means of connection through the vias to the island. | 01-14-2010 |
20100128397 | FLEX CABLE AND METHOD FOR LOWERING FLEX CABLE IMPEDANCE - A flex cable comprises a base film, a first adhesive layer coupled with the base film, and at least two signal traces coupled with the first adhesive layer. The flex cable comprises a second adhesive layer coupled with the signal traces and the first adhesive layer, and a cover film coupled with the second adhesive layer. The flex cable comprises an electrically conductive layer adjacent to the signal traces, and parallel with the base film and the cover film. | 05-27-2010 |
20100240327 | ANTENNA ARRAY WITH FLEXIBLE INTERCONNECT FOR A MOBILE WIRELESS DEVICE - An antenna array can be mounted on a flexible substrate and connected by a flexible interconnect to an integrated circuit such as a radio frequency front end. The antenna array can be mounted in a device housing that includes radio frequency interference (RFI) shielding. The antenna array is aligned with and next to an area of the housing that is not shielded against RFI. | 09-23-2010 |
20110090584 | Signaling method and apparatus for write assist of high coercivity media using integrated half coil - A signaling method and apparatus for providing two write assist components for perpendicular thin film heads writing to high coercivity media is disclosed. The two components provided by the present invention include a media writing assist component and a head switching assist component. Circuit wiring configurations and waveforms for driving an auxiliary half coil are disclosed. These include configurations for connecting the auxiliary half coil in parallel with the main data coil, or connecting the auxiliary half coil to the thermal flight control system. Provision for both common mode signals as well as differential mode signals are disclosed. RF sinusoidal waveforms between 1 and 5 GHz have been found suitable for head switching assist functions for either symmetric current feed and common mode current configuration, or asymmetric current feed and differential mode current configuration. RF sinusoidal waveforms between 10 and 50 GHz have been found suitable for media writing assist functions for either asymmetric or symmetric current feed and differential mode configuration. Data derived signals obtained by passing the data pulse train though high pass filtration has been found to provide both head switching assist and media writing assist functionality. Data derived signals can be used with or without the RF signals. | 04-21-2011 |
20110090596 | Integrated half coil structure for write assist of high coercivity media - A structure for providing two write assist components for perpendicular thin film heads writing to high coercivity media is disclosed. The two components provided by the present invention include a media writing assist component and a head switching assist component. The structure includes an auxiliary half coil surrounding the pole tip at the ABS, and includes conductive elements running parallel to the pole layer which are connected to the auxiliary half coil. Integrated heat sinks located at either the ABS or at a recessed position are provided. The conductive elements can prove either symmetric or asymmetric current feed geometries, which allow differential or common mode current flow to the half coil. | 04-21-2011 |
20110141626 | MAGNETIC RECORDING DISK DRIVE WITH INTEGRATED LEAD SUSPENSION HAVING MULTIPLE SEGMENTS FOR OPTIMAL CHARACTERISTIC IMPEDANCE - An integrated lead suspension (ILS) in a magnetic recording disk drive has the transmission line portion of the ILS between the flex cable and the gimbal formed of multiple interconnected segments, each with its own characteristic impedance. At the interface between any two segments there is a change in the widths of the electrically conductive traces of the transmission line. The change in impedance of a fixed-length segment is a function of the change in its trace width. The number of segments and their characteristic impedance values are selected to produce the largest frequency bandwidth with a substantially flat group delay from the write driver to the write head. | 06-16-2011 |
20110149428 | SLIDER FLY-HEIGHT CONTROL IN A HARD DISK DRIVE - In fly-height control system, a slider comprises a spin torque oscillator that is configured for generating an RF carrier signal which is out-of-band of a frequency band of read data, write data, and control signals in a hard disk drive. | 06-23-2011 |
20120163073 | Early detection of degradation in NOR flash memory - The embodiments of the invention in this disclosure describe techniques for early warning of degradation in NOR Flash memories by estimating the dispersion of the threshold voltages (V | 06-28-2012 |
20120163074 | Early degradation detection in flash memory using test cells - A Flash memory system and a method for data management using the embodiments of the invention use special test cells with Early Degradation Detection (EDD) circuitry instead of using the actual user-data storage cells are described. The Flash memory test cells can be made to serve as a “canary in a coal mine” by being made more sensitive than the standard cells by using experimentally determined sensitive write V | 06-28-2012 |
20120163084 | Early detection of degradation in NAND flash memory - Techniques for early detection of degradation in NAND Flash memories by measuring the dispersion of the threshold voltages (VT's), of a set (e.g. page) of NAND Flash memory cells during read operations are described. In an embodiment of the invention the time-to-completion (TTC) values for the read operation for the memory cells are used as a proxy for dispersion of the threshold voltages (VT's). A Dispersion Analyzer determines the dispersion of the set of TTC values. In one embodiment the delta between the maximum and minimum TTC values is used as the dispersion measurement. If the measured TTC dispersion differs by more than a selected amount from a reference dispersion value, a warning signal is provided to indicate that the page of memory has degraded. The warning signal can be used to take appropriate action such as moving the data to a new page. | 06-28-2012 |
20120166707 | Data management in flash memory using probability of charge disturbances - A Flash memory system and a method for data management using the system's sensitivity to charge-disturbing operations and the history of charge-disturbing operations executed by the system are described. In an embodiment of the invention, the sensitivity to charge-disturbing operations is embodied in a disturb-strength matrix in which selected operations have an associated numerical value that is an estimate of the relative strength of that operation to cause disturbances in charge that result in data errors. The disturb-strength matrix should also include the direction of the error which indicates either a gain or loss of charge. The disturb-strength matrix can be determined by the device conducting a self-test in which changes in the measured dispersion value are provoked by executing a selected operation until a detectable change occurs. In alternative embodiments the disturb-strength matrix is determined by testing selected units from a homogeneous population. | 06-28-2012 |
20120166897 | Data management in flash memory using probability of charge disturbances - A Flash memory system and a method for data management using the system's sensitivity to charge-disturbing operations and the history of charge-disturbing operations executed by the system are described. In an embodiment of the invention, the sensitivity to charge-disturbing operations is embodied in a disturb-strength matrix in which selected operations have an associated numerical value that is an estimate of the relative strength of that operation to cause disturbances in charge that result in data errors. The disturb-strength matrix can also include the direction of the error which indicates either a gain or loss of charge. The disturb-strength matrix can be determined by the device conducting a self-test in which charge-disturb errors are provoked by executing a selected operation until a detectable error occurs. In alternative embodiments the disturb-strength matrix is determined by testing selected units from a homogeneous population. | 06-28-2012 |
20120301746 | RADIATOR-COOLED NANOWIRE-BASED WRITE ASSIST - An apparatus for cooling a nanowire in a wire assisted magnetic recording head using a radiator in close proximity to a shield of the write pole. The radiator may further contain current restraints (e.g., slits, cuts, or resistive materials) that maximize current density in the nanowire at a location that corresponds to the current restraints. These current restraints may be further arranged to align with a write pole such that the current is forced to flow primarily through the nanowire when the nanowire is closest to the write pole. The nanowire may then be used either as main or auxiliary writing element for recording signals to a high coercivity media. Moreover, the nanowire and radiator may be combined into a single nanofoil which has a least two portions that perform a similar function as both the nanowire and radiator. | 11-29-2012 |
20130193399 | 3D SOLID-STATE ARRANGEMENT FOR SOLID STATE MEMORY - The present invention generally relates to the three-dimensional arrangement of memory cells. This 3D arrangement and orientation is made with macro cells that enable the programming, reading and/or querying of any memory cell in the 3D array without the need for overhead wiring or by utilizing a minimal amount of overhead wiring. The individual macro cells are electrically coupled together such that a single transistor on the substrate can be utilized to address multiple macro cells. In such an arrangement, all the auxiliary circuits for addressing memory elements are simplified thereby diminishing their integrated circuit area. | 08-01-2013 |
20130194855 | HIGH CURRENT CAPABLE ACCESS DEVICE FOR THREE-DIMENSIONAL SOLID-STATE MEMORY - The present invention generally relates to three-dimensional arrangement of memory cells and methods of addressing those cells. The memory cells can be arranged in a 3D orientation such that macro cells that are in the middle of the 3D arrangement can be addressed without the need for overhead wiring or by utilizing a minimal amount of overhead wiring. An individual macro cell within a memory cell can be addressed by applying three separate currents to the macro cell. A first current is applied to the memory cell directly. A second current is applied to the source electrode of the MESFET, and a third current is applied to the gate electrode of the MESFET to permit the current to travel through the channel of the MESFET to the drain electrode which is coupled to the memory element. | 08-01-2013 |
20130194864 | IMPLEMENTING ENHANCED DATA WRITE FOR MULTI-LEVEL CELL (MLC) MEMORY USING THRESHOLD VOLTAGE-DRIFT OR RESISTANCE DRIFT TOLERANT MOVING BASELINE MEMORY DATA ENCODING - A method and apparatus are provided for implementing enhanced performance for multi-level cell (MLC) memory using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding. A voltage baseline of a prior write is identified, and a data write uses the threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding for data being written to the MLC memory responsive to the identified voltage baseline. | 08-01-2013 |
20130194865 | IMPLEMENTING ENHANCED DATA READ FOR MULTI-LEVEL CELL (MLC) MEMORY USING THRESHOLD VOLTAGE-DRIFT OR RESISTANCE DRIFT TOLERANT MOVING BASELINE MEMORY DATA ENCODING - A method and apparatus are provided for implementing enhanced data read for multi-level cell (MLC) memory using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding. A data read back for data written to the MLC memory using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding is performed, higher voltage and lower voltage levels are compared, and respective data values are identified responsive to the compared higher voltage and lower voltage levels. | 08-01-2013 |
20130198436 | IMPLEMENTING ENHANCED DATA PARTIAL-ERASE FOR MULTI-LEVEL CELL (MLC) MEMORY USING THRESHOLD VOLTAGE-DRIFT OR RESISTANCE DRIFT TOLERANT MOVING BASELINE MEMORY DATA ENCODING - A method and apparatus are provided for implementing enhanced data partial erase for multi-level cell (MLC) memory using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding. A data partial erase for data written to the MLC memory using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding is performed, and a data re-write after the partial erase to the MLC memory is performed using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding. A data partial erase cycle includes a duration and voltage level based upon a degradation of the MLC memory cells. | 08-01-2013 |
20140101370 | APPARATUS AND METHOD FOR LOW POWER LOW LATENCY HIGH CAPACITY STORAGE CLASS MEMORY - A method and a storage system are provided for implementing enhanced solid-state storage class memory (eSCM) including a direct attached dual in line memory (DIMM) card containing dynamic random access memory (DRAM), and at least one non-volatile memory, for example, Phase Change memory (PCM), Resistive RAM (ReRAM), Spin-Transfer-Torque RAM (STT-RAM), and NAND flash chips. An eSCM processor controls selectively allocating data among the DRAM, and the at least one non-volatile memory primarily based upon a data set size. | 04-10-2014 |
20140204646 | HIGH CURRENT CAPABLE ACCESS DEVICE FOR THREE-DIMENSIONAL SOLID-STATE MEMORY - The present invention generally relates to three-dimensional arrangement of memory cells and methods of addressing those cells. The memory cells can be arranged in a 3D orientation such that macro cells that are in the middle of the 3D arrangement can be addressed without the need for overhead wiring or by utilizing a minimal amount of overhead wiring. An individual macro cell within a memory cell can be addressed by applying three separate currents to the macro cell. A first current is applied to the memory cell directly. A second current is applied to the source electrode of the MESFET, and a third current is applied to the gate electrode of the MESFET to permit the current to travel through the channel of the MESFET to the drain electrode which is coupled to the memory element. | 07-24-2014 |
20140373114 | APPARATUS AND METHOD FOR VALIDATION AND AUTHORIZATION OF DEVICE AND USER BY GLOBAL POSITIONING AND NON-PROMPTED EXCHANGE OF INFORMATION - An authorization and validation system and method for mobile financial transactions uses (1) historic Global Positioning System (GPS) and time at specific locations and (2) both visible and invisible prompts to allow access to assets and performance of financial transactions. Said system and method also determines when the mobile device, tablet or smart phone, is lost or is operated by an impersonator. Special attention is devoted when said system is engaged in determining whether the user is under threat or not. | 12-18-2014 |
20150026042 | SYSTEM AND METHOD FOR ELECTRONIC CASH-LIKE TRANSACTIONS - An electronic money system where ownership of each cent of properly created and labeled electronic money is manifested and confirmed by the ability of a client to change specific secret content in pre-determined field assigned to said cent of electronic money. Said ability is granted upon demonstration of knowledge of the current content of said pre-determined field. An electronic money system capable of purchases, transfers, deposits and remittances with anonymity and convenience similar to ordinary cash. An electronic system whose enabling client computational resources can be downloaded as a software application and can be operated under yearly subscription fee. | 01-22-2015 |