Patent application number | Description | Published |
20090300410 | SEMICONDUCTOR INTEGRATED CIRCUIT, CONTROL METHOD, AND INFORMATION PROCESSING APPARATUS - A semiconductor integrated circuit includes a circuit block connected to an arithmetic processing unit via a bus, a power supply noise data generator which is configured to generate a power supply noise data signal by converting power supply noise generated in power supply voltage of power supply operates the circuit block, an error detector which is configured to detect an error of data outputted from the circuit block to the bus, and a write controller which is configured to associate power supply noise information based on the power supply noise data signal with data on the bus and write the data in a storage unit, and to stop to write the data in response to the detection of the error by the error detector. | 12-03-2009 |
20100077262 | INFORMATION PROCESSING DEVICE AND ERROR PROCESSING METHOD - An information processing device having two processing units capable of operating in synchronization with each other, includes: a common unit capable of outputting an identical signal to the two processing units; detection units that are respectively provided for the processing units and each detects errors occurred in corresponding processing unit respectively; a comparison unit that compares outputs from the two processing units; and a control unit that controls signals from the processing units to the common unit, based on a detection result of the detection units and a comparison result of the comparison unit, and determines, if errors of an identical type are simultaneously detected by the detection units, that the errors are due to an error of the common unit. | 03-25-2010 |
20110047431 | Verification device, verification method, and verification program - A verification device includes a data verifying unit that verifies whether data in a packet has an error using a first or a second verification mode, a packet generating unit that generates a packet in accordance with a first packet generation mode or a second packet generation mode respectively corresponding to the first and the second verification modes, a failure monitoring unit that monitors a failure of a transmission line that requires a switching of the verification mode, a switching packet transmitting unit that transmits to a destination device, a switching packet for informing the switching of the verification mode used by the data verifying unit when the failure monitoring unit detects a failure or a removal of a failure, a generation mode switching unit that switches the generation mode, and a verification mode switching unit that switches the verification mode to the one informed by the switching packet. | 02-24-2011 |
20110320683 | Information processing system, resynchronization method and storage medium storing firmware program - An information processing system includes sets of multiple processors performing processing synchronously. The system includes: a ROM storing a firmware program activating the processors to a synchronized state; a RAM defined by one address map; a firmware copying section copying the firmware program in the ROM to the RAM, on system boot; and a RAM address register storing an address of the RAM and of a copy destination of the firmware program. The system further includes: a RAM address storing section storing the address of the RAM and of the copy destination of the firmware program; a loss-of-synchronism detection section detecting loss of synchronism of the processors; and an address replacing section referring to the RAM address register upon detection of the loss of synchronism, thereby replacing an address for reading the stored firmware program, with the address of the RAM and of the copy destination of the firmware program. | 12-29-2011 |
20110320885 | TRANSMISSION/RECEPTION DEVICE, TRANSMISSION DEVICE, RECEPTION DEVICE, AND DATA TRANSMISSION/RECEPTION METHOD - A transmission/reception device includes a transmission device that divides a plurality of connection lines into a plurality of groups, determines corresponding connection lines in the plurality of groups, determines a correspondence between test pattern and the connection line, and outputs the test pattern to the plurality of connection lines based on the correspondence between the test pattern and the connection line, and a reception device that receives the test pattern from the transmission device, compares bits in a same position of the test pattern received through a corresponding connection line in the plurality of groups based on the correspondence between the test pattern and the connection line, and generates erroneous connection line information indicating an erroneous connection line as a connection line in which an error has occurred in the plurality of connection lines based on a result of the comparison. | 12-29-2011 |
20120236843 | INFORMATION PROCESSING APPARATUS AND METHOD OF SWITCHING SETTINGS THEREOF - A method of switching internal settings in an information processing apparatus including a plurality of processors, a crossbar switch connected to the plurality of processors and having a first routing table and a second routing table used for routing between the plurality of processors and an external apparatus, and a management unit managing the plurality of processors. The method includes performing, by the processors, data communication with the external apparatus using the first routing table, updating, by the management unit, configuration information in the second routing table when a configuration of the information processing apparatus is changed, instructing, by the management unit, any one of the processors to switch the updated second routing table and the first routing table, and switching, by the processor instructed by the management unit, a routing table to be used for the data communication from the first routing table to the updated second routing table. | 09-20-2012 |
20130086335 | MEMORY SYSTEM AND MEMORY INTERFACE DEVICE - A memory access source regards a plurality of memory circuits as single memory circuit and transmits a row address and a column address in time division to an access control circuit. The access control circuit performs a speculative access to the plurality of memory circuits when receiving the row address, and performs an access to a memory circuit which is specified by the column address after receiving the column address and sends a cancel command of the speculative access to the other memory circuit out of target. Or, in the case of read access, the access control circuit receives read data from the plurality of memory circuits and discards the read data of the memory circuit out of the target by the column address. | 04-04-2013 |
20130166860 | MEMORY ACCESS CONTROL DEVICE AND COMPUTER SYSTEM - A memory interleaving device accesses a memory in an interleaved manner for changing the number of ways of interleaving during system operation. During a copy which changes a first configuration before changing the number of ways in the interleaving to a second configuration after changing the number of ways in the interleaving, a memory access control device reads the memory in the first configuration before changing the number of ways of the interleaving for an external read request and writes the memory in both of the first configuration before changing the number of ways in the interleaving and the second configuration after changing the number of ways in the interleaving for an external write request. | 06-27-2013 |
20130212333 | INFORMATION PROCESSING APPARATUS, METHOD OF CONTROLLING MEMORY, AND MEMORY CONTROLLING APPARATUS - An information processing apparatus provided with a plurality of nodes each including at least one processor, a system controller, and a main memory, includes a status storage unit that stores statuses of a plurality of cache lines and that is capable of reading statuses of a plurality of cache lines by one reading operation, a recording unit that is provided in a system controller in at least one node and that records all or part of the statuses stored in the status storage unit, wherein the system controller records obtained statuses in the recording unit on a condition that all of the statuses of the plurality of cache lines obtained by reading the status storage unit are invalid statuses or shared statuses in different nodes when the system controller has read the status storage unit in response to a request. | 08-15-2013 |
20130297882 | CACHE MEMORY DEVICE, CONTROL UNIT OF CACHE MEMORY, INFORMATION PROCESSING APPARATUS, AND CACHE MEMORY CONTROL METHOD - A cache memory device including a cache memory that includes a plurality of entries and includes at least one block including data and a status representing a status of the data for each entry and a control unit that performs replacement of the data on each block of the cache memory, wherein the control unit includes a counter that counts the number of replacements by which the data is replaced in each entry for each entry and a switching unit that switches a replacement scheme of the data according to the number of replacements. | 11-07-2013 |
20140006720 | DIRECTORY CACHE CONTROL DEVICE, DIRECTORY CACHE CONTROL CIRCUIT, AND DIRECTORY CACHE CONTROL METHOD | 01-02-2014 |
20140095792 | CACHE CONTROL DEVICE AND PIPELINE CONTROL METHOD - A cache control device includes an entering unit, a first searching unit, a reading unit, a second searching unit, and a rewriting unit. The entering unit alternately enters, into a pipeline, a load request for reading a directory received from a processor and a store request for rewriting a directory received from the processor. When the first searching unit determines that the directory targeted by the load request is present in the first cache memory or the second cache memory, the reading unit reads the directory from the cache memory in which the directory is present. When the second searching unit determines that the directory targeted by the store request is present in the first cache memory, the rewriting unit rewrites the directory that is stored in the first cache memory. | 04-03-2014 |
Patent application number | Description | Published |
20090064211 | Optical Disc Apparatus - To prevent an optical disc from being removed from a clamper even when an impact force is applied in an optical disc apparatus. A displacement amount by which a disc motor is sunk on the bottom case side is suppressed. In more detail, a convex portion which protrudes in the bottom cover direction is provided at a region including the whole or a part of an orthographically-projected surface of the disc motor on a surface of a bottom case opposed to a rear surface of the disc motor, and in a state of recording or reproducing, the sum of a distance between a motor fixing plate and a bottom cover and a distance between the bottom cover and the convex portion of the bottom case is smaller in the rotational axis direction of the disc motor than the sum of a distance between an optical disc and a tray and an insertion depth by which a clamper is inserted into a center hole of an optical disc. | 03-05-2009 |
20090064216 | Optical disc apparatus - In order to make a unit mechanical portion lighter and to cut down the cost of the unit mechanical portion in an optical disc apparatus, the optical disc apparatus of the present invention is configured to include: a chassis which includes a supporting portion that supports an optical pickup, a pickup moving mechanism, and a disc motor, and coupling portions that abut on and are coupled to a tray at plural points, which is formed of a synthetic resin material, and in which the supporting portion and the coupling portions are integrated with each other; and a flexible flat cable which electrically couples between a first circuit substrate fixed to the bottom case side and a second circuit substrate fixed to the tray or the chassis side, and which is arranged between a bottom cover and a bottom case while its plane surface is folded in a state where the tray is inserted into an apparatus body. | 03-05-2009 |
20090113462 | OPTICAL DISC APPARATUS - Disclosed herein is an optical disc apparatus wherein, in order that a flexible printed circuit board that connects a printed circuit board provided on the moving unit of the apparatus which includes a tray to a printed circuit board provided on the fixed unit of the apparatus is prevented from being caught between the bottom case of the apparatus and the bottom cover of the moving unit during the slide-in movement of the tray, convex portions are provided on the inner surface of the top cover that covers the top surface side of the apparatus such that the convex portions are directly opposite or directly above the flexible printed circuit board during the slide-in/slide-out movements of the tray and such that the convex portions are positioned further outwardly from the outer circumference of an optical disc with respect to the rotation center of the optical disc upon completion of the slide-in movement of the tray, and the convex portions guide or slide part of the flexible printed circuit board along the tip end surfaces of the convex portions in the direction of the slide-in movement of the tray when the part of the flexible printed circuit board comes into contact with the inner surface of the top cover during the slide-in movement of the tray. | 04-30-2009 |
20100103792 | OPTICAL DISK DEVICE - Provided is an optical disk device, including a top case and a bottom case which constitute a housing having a substantially box shape in which: the top case includes, on one side thereof, a hook which engages with the bottom case; the bottom case includes an engaging portion which is provided with a cutout which engages with the hook; and a shielding portion for preventing an air flow passing through the cutout is provided in an inside of the cutout. | 04-29-2010 |
20100262980 | OPTICAL DISK DRIVE - The present invention provides an optical disk drive that performs a stable lock operation with a small number of components at the time of the insertion of a tray. The optical disk drive has a locking mechanism which engages the inserted tray with the chassis, a reset arm provided in the tray to return the locking mechanism to the initial state, and an engaging boss that is provided in the chassis and is engaged with the reset arm. The tray has a projecting portion for controlling the engagement position between the reset arm and the engaging boss. The projecting portion comes into contact with a back surface of the engaging boss, to control the engaging amount between the reset arm and the engaging boss to be constant. | 10-14-2010 |
20110191793 | OPTICAL DISC DRIVE - There is provided an optical disc drive comprising: a chassis assembly formed in a box shape, including a chassis; and a tray on which an optical disc is loaded, wherein: the tray is able to move between a close state in the chassis assembly and a open state ejecting form the chassis assembly; the optical disc drive further comprises a flexible wiring member for connecting a first circuit board mounted on the chassis and a second circuit board mounted on the tray; the flexible wiring member includes a thicker reinforced part in a part of the flexible wiring member than in the other part of the flexible wiring member; and the reinforced part has a width which is narrower at an end on the chassis side than the other part of the reinforced part. | 08-04-2011 |