Patent application number | Description | Published |
20090305468 | Methods of manufacturing oxide semiconductor thin film transistor - Provided is a method of manufacturing an oxide semiconductor thin film transistor using a transparent oxide semiconductor as a material for a channel. The method of manufacturing the oxide semiconductor thin film transistor includes forming a passivation layer on a channel layer and performing an annealing process for one hour or more at a temperature of about 100° C. or above. | 12-10-2009 |
20090309843 | Touch panel using nano-wire - Provided is a touch panel using a zinc oxide (ZnO) nano wire. The touch panel may include a first transparent substrate, a first transparent electrode layer on the first transparent substrate, a light transmissive nano wire layer including a plurality of piezoelectric nano wires that may be arranged on the first transparent electrode layer so as to be perpendicular to the first transparent electrode layer, a second transparent electrode layer on the nano wire layer, and a second transparent substrate on the second transparent electrode layer. | 12-17-2009 |
20100006810 | Memory device and method of manufacturing the same - Provided are a memory device formed using one or more source materials not containing hydrogen as a constituent element and a method of manufacturing the memory device. | 01-14-2010 |
20100013797 | Touch panel including nanowire - A touch panel may include a plurality of piezoelectric nanowires between a plurality of first transparent electrodes and plurality second transparent electrodes that cross each other; an ultrasonic wave generator configured to generate ultrasonic waves from the piezoelectric nanowires; and at least one ultrasonic wave echo sensor configured to detect ultrasonic waves that are generated from the plurality of piezoelectric nanowires and return to the plurality of piezoelectric nanowires after colliding with an object approaching the plurality of piezoelectric nanowires. | 01-21-2010 |
20100025674 | Oxide semiconductor and thin film transistor including the same - An oxide semiconductor and a thin film transistor (TFT) including the same. The oxide semiconductor may be obtained by adding hafnium (Hf) to gallium-indium-zinc oxide (GIZO) and may be used as a channel material of the TFT. | 02-04-2010 |
20100079169 | Inverter, method of operating the same and logic circuit comprising inverter - Provided are an inverter, a method of operating the inverter, and a logic circuit including the inverter. The inverter may include a load transistor and a driving transistor, and at least one of the load transistor and the driving transistor may have a double gate structure. A threshold voltage of the load transistor or the driving transistor may be adjusted by the double gate structure, and accordingly, the inverter may be an enhancement/depletion (E/D) mode inverter. | 04-01-2010 |
20100090187 | Resistive memory device - Disclosed is a resistive memory device. In the resistive memory device, at least one variable resistance region and at least one switching device may be horizontally apart from each other, rather than being disposed on the same vertical axis. At least one intermediate electrode, which electrically connects the at least one variable resistance region and the at least one switching device, may be between the at least one variable resistance region and the at least one switching device. | 04-15-2010 |
20100159642 | Methods of manufacturing oxide semiconductor thin film transistor - Provided is a method of manufacturing an oxide semiconductor thin film transistor using a transparent oxide semiconductor as a material for a channel. The method of manufacturing the oxide semiconductor thin film transistor includes forming a passivation layer on a channel layer and performing an annealing process for one hour or more at a temperature of about 100° C. or above. | 06-24-2010 |
20110175647 | Method of operating inverter - A method of operating inverter may include providing a load transistor and a driving transistor connected to the load transistor wherein at least one of the load transistor and the driving transistor has a double gate structure, and varying a threshold voltage of the at least one of the load transistor and the driving transistor having the double gate structure. A threshold voltage of the load transistor or the driving transistor may be adjusted by the double gate structure, and accordingly, the inverter may be an enhancement/depletion (E/D) mode inverter. | 07-21-2011 |