Patent application number | Description | Published |
20090086525 | Multi-layered memory devices - A multi-layered memory device is provided. The multi-layered memory device includes two or more memory units and an active circuit unit arranged between each of the two or more memory units. The active circuit includes a decoder. Each memory unit includes one or more memory layers. Each memory layer includes a memory array. | 04-02-2009 |
20090262563 | Memory device capable of one-time data writing and repeated data reproduction, and method and display apparatus for operating the memory device - Provided are a memory device where data may be recorded one time and/or reproduced repeatedly, and a method and display apparatus for operating the memory device. The memory device may include a program area having a plurality of memory cells and a spare area having a plurality of memory cells. The memory device may include a memory cell layer having the program area and the spare area. The memory cell layer may include a plurality of vertically stacked memory cell layers. Each of the plurality of memory cell layers may include the program area and the spare area. The program area and the spare area may be either vertical or horizontal to one another. | 10-22-2009 |
20090302315 | Resistive random access memory - A resistive random access memory (RRAM) includes a switch region formed of a material having bi-polar properties; and a memory resistor formed of a material having uni-polar properties. The RRAM further includes a lower electrode formed below the switch region; an upper electrode formed on the memory resistor; and an intermediate electrode formed between the switch region and the memory resistor. | 12-10-2009 |
20090305468 | Methods of manufacturing oxide semiconductor thin film transistor - Provided is a method of manufacturing an oxide semiconductor thin film transistor using a transparent oxide semiconductor as a material for a channel. The method of manufacturing the oxide semiconductor thin film transistor includes forming a passivation layer on a channel layer and performing an annealing process for one hour or more at a temperature of about 100° C. or above. | 12-10-2009 |
20090315590 | Logic circuits, inverter devices and methods of operating the same - An inverter device includes at least a first transistor connected between a power source node and ground. The first transistor includes a first gate and a first terminal that are internally capacitive-coupled to control a boost voltage at a boost node. The first terminal is one of a first source and a first drain of the first transistor. | 12-24-2009 |
20090321738 | Display apparatus using oxide diode - Provided may be a display apparatus that uses oxide diodes having a nano rod structure, for example, nano-rod diodes formed of a ZnO group material. The display apparatus may include a substrate, a thin film transistor layer on the substrate, and a light emitting layer on the thin film transistor layer, wherein the light emitting layer may include a plug metal layer on the thin film transistor layer, a plurality of nano-rod diodes vertically formed on the plug metal layer, and a transparent electrode on the nano-rod diodes. | 12-31-2009 |
20090321776 | Multi-chip package for LED chip and multi-chip package LED device including the multi-chip package - Provided is a multi-chip package light emitting diode (LED) device including a plurality of LED chips within a single package. The LED device may include a base substrate, a multi-chip package for a LED on the base substrate, and a light radiator surrounding the multi-chip package and radiating light emitted by the multi-chip package for a LED, wherein the multi-chip package for a LED may include a plurality of LED chips on a single wafer substrate. | 12-31-2009 |
20100006810 | Memory device and method of manufacturing the same - Provided are a memory device formed using one or more source materials not containing hydrogen as a constituent element and a method of manufacturing the memory device. | 01-14-2010 |
20100013797 | Touch panel including nanowire - A touch panel may include a plurality of piezoelectric nanowires between a plurality of first transparent electrodes and plurality second transparent electrodes that cross each other; an ultrasonic wave generator configured to generate ultrasonic waves from the piezoelectric nanowires; and at least one ultrasonic wave echo sensor configured to detect ultrasonic waves that are generated from the plurality of piezoelectric nanowires and return to the plurality of piezoelectric nanowires after colliding with an object approaching the plurality of piezoelectric nanowires. | 01-21-2010 |
20100051986 | Light-emitting diodes using nano-rods and methods of manufacturing a light-emitting diode - Light-emitting diodes, and methods of manufacturing the light-emitting diode, are provided wherein a plurality of nano-rods may be formed on a reflection electrode. The plurality of nano-rods extend perpendicularly from an upper surface of the reflection electrode. Each of the nano-rods includes a first region doped with a first type dopant, a second region doped with a second type dopant that is an opposite type to the first type dopant, and an active region between the first region and the second region. A transparent insulating layer may be formed between the plurality of nano-rods. A transparent electrode may be formed on the plurality of nano-rods and the transparent insulating layer. | 03-04-2010 |
20100054015 | Non-volatile memory device and method of operating the same - Provided is a non-volatile memory device that may include a plurality of variable resistors, each of the variable resistors having first and second terminals, the plurality of variable resistors arranged as a first layer of a plurality of layers and having data storage capability, at least one common bit plane arranged as a second layer of the plurality of layers and coupled to the first terminal of each of the variable resistors of the first layer, and a plurality of bit lines coupled to the second terminal of each of the variable resistors of the first layer. | 03-04-2010 |
20100059744 | Transistor, inverter including the same and methods of manufacturing transistor and inverter - A transistor, an inverter including the transistor, and methods of manufacturing the inverter and the transistor. A gate insulating layer of the transistor has a charge trap region. A threshold voltage may be moved in a positive (+) direction by trapping charges in the charge trap region. The transistor may be an enhancement mode oxide thin-film transistor (TFT) and may be used as an element of the inverter. | 03-11-2010 |
20100085821 | Operation method of non-volatile memory - Example embodiments provide a method of operating a non-volatile memory in which the non-volatile memory may only be changed from a first state to a second state and may not be changed from the second state to the first state during a programming operation. | 04-08-2010 |
20100159642 | Methods of manufacturing oxide semiconductor thin film transistor - Provided is a method of manufacturing an oxide semiconductor thin film transistor using a transparent oxide semiconductor as a material for a channel. The method of manufacturing the oxide semiconductor thin film transistor includes forming a passivation layer on a channel layer and performing an annealing process for one hour or more at a temperature of about 100° C. or above. | 06-24-2010 |
20110089998 | Logic circuits, inverter devices and methods of operating the same - An inverter device includes at least a first transistor connected between a power source node and ground. The first transistor includes a first gate and a first terminal that are internally capacitive-coupled to control a boost voltage at a boost node. The first terminal is one of a first source and a first drain of the first transistor. | 04-21-2011 |
20110116297 | Multi-layered memory devices - A multi-layered memory device is provided. The multi-layered memory device includes two or more memory units and an active circuit unit arranged between each of the two or more memory units. The active circuit includes a decoder. Each memory unit includes one or more memory layers. Each memory layer includes a memory array. | 05-19-2011 |
20110116336 | Multi-layered memory devices - A multi-layered memory device is provided. The multi-layered memory device includes two or more memory units and an active circuit unit arranged between each of the two or more memory units. The active circuit includes a decoder. Each memory unit includes one or more memory layers. Each memory layer includes a memory array. | 05-19-2011 |