Patent application number | Description | Published |
20150048518 | METAL PAD OFFSET FOR MULTI-LAYER METAL LAYOUT - A semiconductor device includes a first layer including a number of first layer metal pads, a second layer formed on top of the first layer, the second layer including a number of second layer metal pads, and vias connecting the first layer metal pads to the second layer metal pads. A surface area overlap between the first layer metal pads and the second layer metal pads is below a defined threshold. | 02-19-2015 |
20150129940 | MECHANISM FOR FORMING GATE - Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate. The semiconductor device also includes an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate. The semiconductor device includes a gate over the semiconductor substrate. The gate has an intermediate portion over the active region and two end portions connected to the intermediate portion. Each of the end portions has a first gate length longer than a second gate length of the intermediate portion and is located over the isolation structure. | 05-14-2015 |
20150129987 | MECHANISM FOR FORMING SEMICONDUCTOR DEVICE WITH GATE - Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate. The semiconductor device also includes a gate over the semiconductor substrate, and the gate has an intermediate portion over the active region and two end portions connected to the intermediate portion, and the end portions are over the isolation structure. The semiconductor device further includes a support film over the isolation structure and covering the isolation structure and at least one of the end portions of the gate. The support film exposes the active region and the intermediate portion of the gate. | 05-14-2015 |
20150137247 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a p-type metal oxide semiconductor device (PMOS) and an n-type metal oxide semiconductor device (NMOS) disposed over a substrate. The PMOS has a first gate structure located on the substrate, a carbon doped n-type well disposed under the first gate structure, a first channel region disposed in the carbon doped n-type well, and activated first source/drain regions disposed on opposite sides of the first channel region. The NMOS has a second gate structure located on the substrate, a carbon doped p-type well disposed under the second gate structure, a second channel region disposed in the carbon doped p-type well, and activated second source/drain regions disposed on opposite sides of the second channel region. | 05-21-2015 |
20150200299 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate; a source/drain region having a first dopant in the substrate; a barrier layer having a second dopant formed around the source/drain region in the substrate. When a semiconductor device is scaled down, the doped profile in source/drain regions might affect the threshold voltage uniformity, the provided semiconductor device may improve the threshold voltage uniformity by the barrier layer to control the doped profile. | 07-16-2015 |
20150206945 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a metal oxide semiconductor device disposed over a substrate and an interconnect plug. The metal oxide semiconductor device includes a gate structure located on the substrate and a raised source/drain region disposed adjacent to the gate structure. The raised source/drain region includes a top surface above a surface of the substrate by a distance. The interconnect plug connects to the raised source/drain region. The interconnect plug includes a doped region contacting the top surface of the raised source/drain region, a metal silicide region located on the doped region, and a metal region located on the metal silicide region. | 07-23-2015 |
20150333007 | METAL PAD OFFSET FOR MULTI-LAYER METAL LAYOUT - A semiconductor device includes a first layer including a number of first layer metal pads, a second layer formed on top of the first layer, the second layer including a number of second layer metal pads, and vias connecting the first layer metal pads to the second layer metal pads. A surface area overlap between the first layer metal pads and the second layer metal pads is below a defined threshold. | 11-19-2015 |
Patent application number | Description | Published |
20090005977 | VEHICLE NAVIGATION SYSTEMS AND METHODS - A vehicle navigation system includes a GPS signal processor, an image processing module, a memory, a microprocessor, a navigation adjusting module, and a display module. The GPS signal processor receives GPS signals and obtains an unadjusted navigation position according to the GPS signals. The image processing module captures pictures of surrounding areas and acquires a reference position according to the pictures. The microprocessor calculates an offset between the reference position and the unadjusted navigation position and compares the offset with a predetermined offset. The navigation adjusting module adjusts the unadjusted navigation position according to the reference position and the offset comparison and displays a result on the display module. | 01-01-2009 |
20120146571 | WATERPROOF BATTERY CHARGER - A waterproof battery charger includes a housing and a charging assembly within the housing. The housing includes an upper housing defining a first recess and a lower housing defining a second recess. The lower housing are hinged together. The lower housing includes an elastic sealing layer that can be elastically deformed to provide a seal when the upper housing and the lower housing are closed together. | 06-14-2012 |
20120223972 | PROJECTING SYSTEM AND METHOD THEREOF - A projecting method is provided. The method is implemented by a projecting system. The system includes a projector and an electronic device. The projector includes a first wireless communication unit and a projecting unit. The electronic device includes a second wireless communication unit and a storage unit. First transmits the orientation information indicating the orientation of the projector and the distance through the first wireless communication unit to the second wireless communication unit. Then, compares a currently received orientation of the projector with a previously received orientation of the projector to calculate a rotation angle of the projector. Next, determines a movement distance and a movement direction of a projected area projected with a portion of the to-be-projected image. Then, obtains the portion of the to-be-projected image according to the movement distance, movement direction, and magnification ratio. Last, controls the projecting unit to project the portion of the to-be-projected image. | 09-06-2012 |
20130028444 | AUDIO DEVICE WITH VOLUME ADJUSTING FUNCTION AND VOLUME ADJUSTING METHOD - An audio device and a volume adjusting method are provided. The audio device includes a speed sensor, a first FIFO buffer unit, and a second FIFO buffer unit. The audio device generates audio signals by playing multimedia files and stores audio signals to the first FIFO buffer unit. The audio device collects ambient sound signals and stores collected sound signals to the second FIFO buffer unit. The audio device further analyzes stored audio signals and sound signals to determine a waveform of environmental noise signals, and determines a SPL of the environmental noise signals according to the determined waveform. The audio device then compares the determined SPL with a preset SPL and compares the sensed speed with a preset speed if the determined SPL is greater than the preset SPL, and adjusts the volume of audio signals according to a comparison result between the sensed speed and the preset speed. | 01-31-2013 |
20130029724 | MOBILE PHONE AND METHOD OF UTILIZING DIAL TELEPHONE IN COMMUNICATION - The disclosure provides a mobile phone and a method of utilizing a dial telephone in communication by the mobile phone. The mobile phone is electrically connected to the dial telephone via an audio interface and positioned on a dial plate of the dial telephone, and is rotated with the dial plate. The mobile phone stores a plurality of relationships between sensing parameters and numbers. A user of the mobile phone dials numbers via the dial plate, the mobile phone senses the number-dialing operations, dials out the dialed numbers, and makes a call via a receiver of the dial telephone, thus, it is no need to physically hold the mobile phone to communicate, thereby reducing the amount of radiation received by the user. | 01-31-2013 |
20130040469 | ELECTRICAL CONNECTOR - An electrical connector includes a first connector, and a second connector detachably coupled to the first connector. The first connector has a first magnetic body and at least one first conductive body. The second connector has a second magnetic body and at least one second conductive body. The first magnetic body is capable of magnetically attracting the second magnetic body to form a sealed enclosure to receive the at least one first conductive body and the at least one second conductive body. The at least one first conductive body electrically connects to the at least one second conductive body when the first magnetic body is magnetically bound to the second magnetic body. | 02-14-2013 |
Patent application number | Description | Published |
20140204466 | OPTICAL ELEMENT STRUCTURE AND OPTICAL ELEMENT FABRICATING PROCESS FOR THE SAME - An optical element structure and a fabricating process for the same are provided. The optical element fabricating process includes providing a substrate forming thereon a protrusion; and forming an over coating layer over the protrusion and the substrate by a deposition scheme to form an optical element. | 07-24-2014 |
20140212627 | SELF-ALIGNMENT DUE TO WETTABILITY DIFFERENCE OF AN INTERFACE - Some embodiments relate to a method of processing a workpiece. The workpiece includes a first surface region having a first wettability coefficient, and a second surface region having a second wettability coefficient that differs from the first wettability coefficient. A liquid, which corresponds to an optical structure, is dispensed on the first and second surface regions of the workpiece, wherein the liquid self-aligns to the second surface region due to the difference between the first and second wettability coefficients. The self-aligned liquid is hardened to form the optical structure. | 07-31-2014 |
20140355929 | WAVEGUIDE STRUCTURE AND METHOD FOR FABRICATING THE SAME - Embodiments of forming a waveguide structure are provided. The waveguide structure includes a substrate, and the substrate has an interconnection region and a waveguide region. The waveguide structure also includes a trench formed in the substrate, and the trench has a sloping sidewall surface and a substantially flat bottom. The waveguide structure further includes a bottom cladding layer formed on the substrate, and the bottom cladding layer extends from the interconnection region to the waveguide region, and the bottom cladding layer acts as an insulating layer in the interconnection region. The waveguide structure further includes a metal layer formed on the bottom cladding layer on the sloping sidewall surface. | 12-04-2014 |
20140376858 | Self-Alignment Due to Wettability Difference of an Interface - Some embodiments relate to a method of processing a workpiece. The workpiece includes a first surface region having a first wettability coefficient, and a second surface region having a second wettability coefficient that differs from the first wettability coefficient. A liquid, which corresponds to an optical structure, is dispensed on the first and second surface regions of the workpiece, wherein the liquid self-aligns to the second surface region due to the difference between the first and second wettability coefficients. The self-aligned liquid is hardened to form the optical structure. | 12-25-2014 |
20150016793 | Waveguide Structure - A waveguide structure includes a bottom dielectric layer, a core layer disposed over the bottom dielectric layer, an etch stop layer disposed over the core layer, and a cladding layer or a buffer layer disposed over the etch stop layer. The waveguide structure is configured to guide a light signal through different geography, such as straight, taper, turning, grating and tight coupling sections. | 01-15-2015 |
20150036970 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING - A semiconductor device includes a first chip, a dielectric layer over the first chip, and a second chip over the dielectric layer. A conductive layer is embedded in the dielectric layer and is electrically coupled to the first chip and the second chip. The second chip includes an optical component. The first chip and the second chip are arranged on opposite sides of the dielectric layer in a thickness direction of the dielectric layer. | 02-05-2015 |
20150036991 | METHOD OF MAKING A METAL GRATING IN A WAVEGUIDE AND DEVICE FORMED - A method of making a grating in a waveguide includes forming a waveguide material over a substrate, the waveguide material having a thickness less than or equal to about 100 nanometers (nm). The method further includes forming a photoresist over the waveguide material and patterning the photoresist. The method further includes forming a first set of openings in the waveguide material through the patterned substrate and filling the first set of openings with a metal material. | 02-05-2015 |
20150061126 | MANUFACTURE INCLUDING SUBSTRATE AND PACKAGE STRUCTURE OF OPTICAL CHIP - A manufacture includes a package structure, a first substrate, and a conductive member of a same material. The package structure includes a chip comprising a conductive pad, a conductive structure over the chip, and a passivation layer over the conductive structure. The passivation layer has an opening defined therein, and the opening exposes a portion of a planar portion of the conductive structure. The first substrate includes a first surface defining a first reference plane and a second surface defining a second reference plane. The conductive member extends across the first reference plane and the second reference plane and into the opening. The conductive member is electrically coupled to the exposed portion of the planar portion. | 03-05-2015 |
20150061137 | PACKAGE AND METHOD FOR INTEGRATION OF HETEROGENEOUS INTEGRATED CIRCUITS - A package for holding a plurality of heterogeneous integrated circuits includes a first chip having a first conductive pad and a first substrate including a first semiconductor, and a second chip having a second conductive pad and a second substrate including a second semiconductor. The second semiconductor is different from the first semiconductor. The package also includes a molding structure in which the first chip and the second chip are embedded, a conductive structure over the first chip and conductively coupled to the first conductive pad and over the second chip and conductively coupled to the second conductive pad, and a passivation layer over the conductive structure. The passivation layer comprises an opening defined therein which exposes a portion of the second chip. | 03-05-2015 |
20150104909 | APPARATUS AND METHOD FOR SELF-ALIGNING CHIP PLACEMENT AND LEVELING - An approach is provided for aligning and leveling a chip package portion. The approach involves filling, at least partially, a reservoir formed between a first sidewall portion having a first slanted surface and a second sidewall portion having a second slanted surface with a fluid. The approach also involves placing a chip package portion into the reservoir. The approach further involves draining the fluid from the reservoir to cause the chip package portion to align with respect to a center of the reservoir. The chip package portion aligns with respect to the center of the reservoir and levels based on a relationship between the chip package portion, an angle of the first slanted surface, an angle of the second slanted surface, and the fluid. The chip package portion is secured in the aligned and leveled state by a molding compound. | 04-16-2015 |
20150108667 | APPARATUS AND METHOD FOR CHIP PLACEMENT AND MOLDING - An approach is provided for placing and securing a chip package portion in an aligned position during a curing process. The approach involves providing an apparatus having a first reservoir configured to receive a first chip package, a second reservoir, and a third reservoir. The approach also involves placing the first chip package portion into the first reservoir, the second chip package portion into the second reservoir, and the third chip package portion into the third reservoir. The approach further involves causing the first chip package portion to be secured in a first curing position, the second chip package portion to be secured in a second curing position and the third chip package portion to be secured in a third curing position. | 04-23-2015 |
20150130045 | THERMALLY CONDUCTIVE STRUCTURE FOR HEAT DISSIPATION IN SEMICONDUCTOR PACKAGES - A method of forming a semiconductor package includes providing a substrate, wherein the substrate has at least one chip attached on an upper surface of the substrate. An insulating barrier layer is deposited above the substrate, wherein the at least one chip is at least partially embedded within the insulating barrier layer. A thermally conductive layer is formed over the insulating barrier layer to at least partially encapsulate the at least one chip. | 05-14-2015 |
20150130047 | THERMALLY CONDUCTIVE MOLDING COMPOUND STRUCTURE FOR HEAT DISSIPATION IN SEMICONDUCTOR PACKAGES - A method of forming a semiconductor package includes forming a thermal conductivity layer and attaching the thermal conductivity layer to a chip. The chip has a first surface and a second surface. The thermal conductivity layer is attached to the first surface of the chip. The thermal conductivity layer provides a path through which heat generated from the chip is dissipated to the ambient. A substrate is attached to the second surface of the chip. A molding compound is formed above the substrate to encapsulate the chip and the thermal conductivity layer. | 05-14-2015 |
20150131089 | OPTICAL SPECTROSCOPY DEVICE, PROCESS OF MAKING THE SAME, AND METHOD OF USING THE SAME - An optical spectroscopy device includes a first cladding layer is positioned over a photodetector. An optical core region is over the first cladding layer where the optical core region is configured to receive a light beam. The optical core region includes a first grating having a first pitch where the first pitch is positioned to direct a first wavelength of the light beam to a first portion of the photodetector. The optical core region further includes a second grating having a second pitch where the second grating is positioned to direct a second wavelength of the light beam to a second portion of the photodetector. The first pitch is different from the second pitch, the first wavelength is different from the second wavelength, and the first portion of the photodetector is different from the second portion of the photodetector. Additionally, a second cladding layer is over the optical core region. | 05-14-2015 |
20150131938 | LIGHT COUPLING FORMATION IN A WAVEGUIDE LAYER - An approach is provided for forming a light coupling in a waveguide layer. The approach involves forming a waveguide layer overlaying an upper surface of a substrate. The approach also involves placing a chip package portion within the waveguide layer in a selected position. The approach further involves forming a molding compound layer overlaying the waveguide layer and the chip package portion. The approach additionally involves curing the molding compound layer to form a cured package. The approach also involves releasing the cured package from the substrate and inverting the cured package. The approach further involves forming a ridge waveguide structure in the waveguide layer by removing a portion of the lower surface of the cured package. | 05-14-2015 |
20150131939 | APPARATUS AND METHOD OF FORMING CHIP PACKAGE WITH WAVEGUIDE FOR LIGHT COUPLING - An apparatus and method of forming a chip package with a waveguide for light coupling is disclosed. The method includes depositing an adhesive layer over a carrier. The method further includes depositing a laser diode (LD) die having a laser emitting area onto the adhesive layer and depositing a molding layer over the LD die and the adhesive layer. The method still further includes curing the molding layer and partially removing the molding layer to expose the laser emitting area. The method also includes depositing a ridge waveguide structure adjacent to the laser emitting area and depositing an upper cladding layer over the ridge waveguide structure. | 05-14-2015 |
20150132008 | VIA-LESS MULTI-LAYER INTEGRATED CIRCUIT WITH INTER-LAYER INTERCONNECTION - A multi-layer integrated circuit comprises a light source configured to input source light to a first optical transmitter. The first optical transmitter is configured to modify the source light and to output a first modulated light based on data received from a first circuit to a second optical receiver. The first modulated light indicates a first data set, the second optical receiver is configured to receive the first modulated light and communicate the first data set to a second circuit. | 05-14-2015 |
20150145082 | BACKSIDE-ILLUMINATED PHOTODETECTOR STRUCTURE AND METHOD OF MAKING THE SAME - A backside-illuminated photodetector structure comprising a first reflecting region, a second reflecting region and a semiconductor region. The semiconductor region is between the first reflecting region and the second reflecting region. The semiconductor region comprises a first doped region and a second doped region. | 05-28-2015 |
20150146203 | BIO-CHIP PACKAGE WITH WAVEGUIDE INTEGRATED SPECTROMETER - A bio-chip package comprises a substrate a first layer over the substrate comprising an image sensor. The bio-chip package also comprises a second layer over the first layer. The second layer comprises a waveguide system a grating coupler. The bio-chip package also comprises a third layer arranged to accommodate a fluid between a first-third layer portion and a second-third layer portion, and to allow the fluid to pass from a first side of the third layer to a second side of the third layer. The third layer comprises a material having a predetermined transparency with respect to a wavelength of a received source light, the waveguide system is configured to direct the received source light to the grating coupler, and the image sensor is configured to determine a change in the wavelength of the source light caused by a coupling between the source light and the fluid. | 05-28-2015 |
20150146268 | OPTICAL SCANNER INTEGRATED WITH SUBSTRATE METHOD OF MAKING AND METHOD OF USING THE SAME - An optical scanner includes a substrate, and a tunable laser on the substrate, wherein the tunable laser is configured to emit light, and to sweep a wavelength of the emitted light through a waveband. The optical scanner further includes a grating over a top surface of the substrate, the grating configured to diffract light emitted from the tunable laser, and an angled reflective surface configured to reflect the diffracted light from the grating. The optical scanner further includes a refractive element configured to receive the reflected light from the angled reflective surface. The refractive element is configured to focus the reflected light in a first direction and to diverge the reflected light in a second direction perpendicular to the first direction. | 05-28-2015 |
20150146275 | ELECTRO-OPTIC MODULATOR DEVICE AND METHOD OF MAKING THE SAME - An electro-optic modulator including a semiconductor region, a first reflecting region over the semiconductor region and an anti-reflecting region on an opposite surface of the semiconductor region from the first reflecting layer. The semiconductor region includes a first doped region and a second doped region. | 05-28-2015 |
20150147852 | VACUUM CARRIER MODULE, METHOD OF USING AND PROCESS OF MAKING THE SAME - A vacuum carrier module includes a substrate having at least one hole and an edge region. There is at least one support on a top surface of the substrate. Further, a gel film is adhered to the edge region of the substrate. The at least one hole fluidly connects a reservoir located above the top surface of the substrate. A method of using a vacuum carrier module includes planarizing a gel film by passing an alignment material through a hole in a substrate to contact a first surface of the gel film, positioning at least one chip on a second surface of the gel film opposite the first surface. The method further includes encasing the at least one chip in a molding material and applying a vacuum to the first surface of the gel film. | 05-28-2015 |
20150160413 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING - A semiconductor device includes a substrate, a trench in the substrate, the trench having an inclined sidewall, a reflective layer over the inclined sidewall, a grating structure over the substrate, and a waveguide in the trench. The waveguide is configured to guide optical signals between the grating structure and the reflective layer. | 06-11-2015 |
20150180210 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - A semiconductor arrangement and a method of forming the same are described. A semiconductor arrangement includes a first layer including a first optical transceiver and a second layer including a second optical transceiver. A first serializer/deserializer (SerDes) is connected to the first optical transceiver and a second SerDes is connected to the second optical transceiver. The SerDes converts parallel data input into serial data output including a clock signal that the first transceiver transmits to the second transceiver. The semiconductor arrangement has a lower area penalty than traditional intra-layer communication arrangements that do not use optics for alignment, and mitigates alignment issues associated with conventional techniques. | 06-25-2015 |
20150234137 | OPTICAL BENCH ON SUBSTRATE AND METHOD OF MAKING THE SAME - An optical bench includes a substrate having a trench therein, and a light emitting device within the trench. The optical bench further includes a light receiving device optically connected to the light emitting device. The optical bench further includes at least one active circuit electrically connected to the light emitting device. The optical bench further includes a waveguide in the trench, wherein the waveguide is optically between the light emitting device and the light receiving device. The optical bench further includes an optically transparent material between the light emitting device and the waveguide. | 08-20-2015 |
20150287705 | APPARATUS AND PACKAGE STRUCTURE OF OPTICAL CHIP - An apparatus includes a package structure. The package structure includes a chip, a conductive structure over the chip, a molding structure surrounding and underneath the chip, and a first passivation layer over the conductive structure. The chip includes an optical component and a chip conductive pad. The conductive structure is electrically coupled to the chip conductive pad. The conductive structure has a planar portion substantially in parallel with an upper surface of the chip. The first passivation layer has a first opening defined therein. The first opening exposes a portion of the planar portion. The package structure is configured to receive an electrical coupling through the first opening in the first passivation layer. | 10-08-2015 |
20150318239 | APPARATUS AND METHOD FOR CHIP PLACEMENT AND MOLDING - An apparatus includes a base portion having an upper surface and a lower surface opposite the upper surface. The apparatus also includes a first sidewall portion having a first upper portion distal the upper surface of the base portion and a first slanted sidewall between the first upper portion and the upper surface of the base portion. The apparatus further includes a second sidewall portion having a second upper portion distal the upper surface of the base portion and a second slanted sidewall between the second upper portion and the upper surface of the base portion. The first sidewall portion and the second sidewall portion define a first reservoir between the first slanted sidewall and the second slanted sidewall, the first reservoir being configured to receive a first chip package portion and to secure the first chip package portion in a first curing position. | 11-05-2015 |
20160026013 | ELECTRO-OPTIC MODULATOR DEVICE, OPTICAL DEVICE AND METHOD OF MAKING AN OPTICAL DEVICE - An electro-optic modulator device includes a modulation region, a reflecting region, a conductive line and an anti-reflecting region. The modulation region includes a doped region. The reflecting region is over the modulation region. The conductive line is connected to the doped region. The conductive line extends through the reflecting region. The anti-reflecting region is on an opposite surface of the modulation region from the reflecting region. | 01-28-2016 |