Patent application number | Description | Published |
20080218269 | POWER AMPLIFIER CIRCUIT, CONTROL METHOD THEREOF AND CONTROL PROGRAM THEREOF - A power amplifier circuit includes a first variable gain amplifier for amplifying an input signal, a second variable gain amplifier for amplifying an output signal of the first amplifier, and a control circuit for controlling the gain of the first variable gain amplifier based on the output signal of the first variable gain amplifier and the gain of the second variable gain amplifier. | 09-11-2008 |
20110026426 | TRANSMISSION CIRCUIT AND RADIO COMMUNICATION APPARATUS - In a transmission circuit used in a TDD scheme, a preset current is supplied from a current source to a detection diode via a switch that is made conductive during a reception period and made non-conductive during a transmission period. A determination is made if the output of the detection diode is within a predetermined specified range and, if the output is out of the specified range, a judgment is made that the detection diode is faulty. | 02-03-2011 |
20110237291 | POWER DETECTION CIRCUIT, TRANSMITTER, AND POWER DETECTION METHOD - From an antenna provided in a transmitter for transmitting a radio signal, the radio signal is transmitted in such a manner of: detecting transmission power of a transmission signal outputted to the antenna; detecting reflection power of a reflection signal reflected from the antenna; integrating the difference between the transmission power and the reflection power at a timing of transmitting a preamble signal of the radio signal; comparing the difference value obtained by the integration with a predetermined threshold value, and outputting an alarm in the case where the result of the comparison is that the difference value obtained by the integration is smaller than the threshold value. | 09-29-2011 |
Patent application number | Description | Published |
20100001397 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of NAND memory dies each including: a first wiring layer formed in the NAND memory die; a second wiring layer formed in the NAND memory die; a first insulation layer formed between the first wiring layer and the second wiring layer; and a first interlayer connector formed in the first insulation layer, a controller configured to control the NAND memory dies; a package housing the NAND memory dies and the controller; a connecting portion electrically connecting an inner side of the package and an outer side of the package; a first connecting wire; and a second connecting wire, wherein a resistance value per unit length of the first interlayer connector is larger than a resistance value per unit length of the first wiring layer, and wherein the first interlayer connector is cut off when a first current flows through the first interlayer connector. | 01-07-2010 |
20100301405 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device including first laminated bodies each having a plurality of first gate electrodes of first memory cells, second laminated bodies each having a plurality of second gate electrodes of second memory cells, gate insulating film portions located on side surfaces of the first and second laminated bodies, first semiconductor layers that are each located between the first and second laminated bodies, first select transistors connected to an uppermost one of the first memory cells, second select transistors connected to an uppermost one of the second memory cells, isolation insulating films to separate the first and second select transistors into portions on the first and second laminated body sides, and a substrate potential applying electrode located to penetrate the isolation insulating films from a front surface side to a back surface side and connected to the first semiconductor layers. | 12-02-2010 |
20110049608 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A memory string comprises: a first semiconductor layer including a columnar portion extending in a stacking direction on a substrate; a first charge storage layer surrounding the columnar portion; and a plurality of first conductive layers stacked on the substrate so as to surround the first charge storage layer. A select transistor comprises: a second semiconductor layer in contact with an upper surface of the columnar portion and extending in the stacking direction; a second charge storage layer surrounding the second semiconductor layer; and a second conductive layer deposited above the first conductive layer to surround the second charge storage layer. The second charge storage layer is formed from a layer downward of the second conductive layer to an upper end vicinity of the second conductive layer, and is not formed in a layer upward of the upper end vicinity. | 03-03-2011 |
20110075481 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises: a bit line; a source line; a memory string having a plurality of electrically data-rewritable memory transistors connected in series; a first select transistor provided between one end of the memory string and the bit line; a second select transistor provided between the other end of the memory string and the source line; and a control circuit configured to control a read operation. A plurality of the memory strings connected to one bit line via a plurality of the first select transistors. During reading of data from a selected one of the memory strings, the control circuit renders conductive the first select transistor connected to an unselected one of the memory strings and renders non-conductive the second select transistor connected to unselected one of the memory strings. | 03-31-2011 |
20120241846 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device comprises a first conductive layer, a second conductive layer, a first inter-electrode insulating film, and a third conductive layer stacked above the first conductive layer, a memory film, a semiconductor layer, an insulating member, and a silicide layer. The memory film and the semiconductor layer is formed on the inner surface of through hole provided in the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The insulating member is buried in a slit dividing the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The silicide layer is formed on surfaces of the second conductive layer and the third conductive layer in the slit. The distance between the second conductive layer and the third conductive layer along the inner surface of the slit is longer than that of along the stacking direction. | 09-27-2012 |