Patent application number | Description | Published |
20080252516 | Determining a Geolocation Solution of an Emitter on Earth Using Satellite Signals - Embodiments provide systems and methods for determining the geolocation of an emitter on earth. A solution is obtained from two TDOA measurements that need not be acquired at the same time. A solution is obtained from a TDOA measurement and an FDOA measurement that need not be acquired at the same time and need not be coming from the same satellite pair. A location of an emitter can be determined from minimizing a cost function of the weighted combination of the six solutions derived from the two TDOA measurements and the two FDOA measurements, where the weight of each solution in the combination is determined based on the intersection angle of the two curves that define the possible locations of the emitter based on the TDOA and/or FDOA measurements. | 10-16-2008 |
20080252525 | Determining a Geolocation Solution of an Emitter on Earth Based on Weighted Least-Squares Estimation - Embodiments provide systems and methods for determining the geolocation of an emitter on earth based on weighted least-squares estimation based on two TDOA and two FDOA measurements, none of which need to be acquired at the same time. The four TDOA and FDOA measurements and the errors in each of the measurements are determined. Weights for the errors in the TDOA and FDOA measurements are determined, and the weights are applied in a weighted errors function. The weights account for the errors in the measurements and the errors in the satellite positions and velocities, and are dependent on the localization geometry. The weighted errors function is minimized to determine the location estimate of the unknown emitter. | 10-16-2008 |
20100046672 | System for and Method of Detecting Interference in a Communication System - A system for and method of detecting interference in a communication system. In an embodiment, a receiver acquires a communication signal, the communication signal comprising a carrier signal and an in-band interference signal. A signal processor conditions the communication signal and extracts the in-band interference signal without interrupting the carrier signal to form an error signal. The error signal is representative of the in-band interference signal. The signal processor is further configured to process the error signal to obtain one or more spectral properties of the error signal in a manner suitable for display. | 02-25-2010 |
20110135043 | System for and method of removing unwanted inband signals from a received communication signal - A system for and method of removing one or more unwanted inband signals from a received communications signal is described. The inband signal or signals may comprise noise, interference signals, or any other unwanted signals that impact the quality of the underlying communications. A receiver receives a communication signal, the received communication signal including the desired communication signal and one or more inband signals. A signal processor processes the received signal to form an estimate of the desired communication signal and an estimate of the inband signals. The estimate of the inband signals is thereby removed from the received signal. The estimate of the desired communication signal and the estimate of the inband signals are formed without prior knowledge of characteristics of the inband signals and without obtaining a copy of any of the inband signals from any source other than the received signal. | 06-09-2011 |
20140153679 | System for and Method of Removing Unwanted Inband Signals from a Received Communication Signal - A system for and method of removing one or more unwanted inband signals from a received communications signal is described. The inband signal or signals may comprise noise, interference signals, or any other unwanted signals that impact the quality of the underlying communications. A receiver receives a communication signal, the received communication signal including the desired communication signal and one or more inband signals. A signal separator processes the received signal to form an estimate of the desired communication signal and an estimate of the inband signals. A performance improver processes the received signal and the estimate of the one or more inband signals to form an improved estimate of the desired communication signal and an improved estimate of the inband signals. | 06-05-2014 |
Patent application number | Description | Published |
20080232574 | Flexible Communication Systems and Methods - A method of initiating a telecommunication session for a communication device include submitting to one or more telecommunication carriers a proposal for a telecommunication session, receiving from at least one of the one or more of telecommunication carriers a bid to carry the telecommunications session, and automatically selecting one of the telecommunications carriers from the carriers submitting a bid, and initiating the telecommunication session through the selected telecommunication carrier. | 09-25-2008 |
20100020776 | Wireless network-based location approximation - The invention pertains to location approximation of devices, e.g., wireless access points and client devices in a wireless network. Location estimates may be obtained by observation/analysis of packets transmitted or received by the access point. For instance, data rate information associated with a packet is used to approximate the distance between a client device and the access point. This may be coupled with known positioning information to arrive at an approximate location for the access point. Confidence information and metrics about whether a device is an access point and the location of that device may also be determined. Accuracy of the location determination may be affected by factors including propagation and environmental factors, transmit power, antenna gain and diversity, etc. A location information database of access points may employ measurements from various devices over time. Such information may identify the location of client devices and provide location-based services to them. | 01-28-2010 |
20110227699 | PERSONALIZED LOCATION TAGS - Systems and methods are provided for creating and using personalized location information tags (geotags). Personalized geotags take the place of generic location information such as latitude/longitude coordinates or granular city/state information. Such geotags may be published to present to selected people, e.g., family and friends, a user's current location. Thus, the user's location may be shown as “Home” or “Gym,” providing user-specific information without having to list a street address or latitude/longitude coordinates. Personalized geotags may be inferred based upon historical location information of the user. Geotags may also be inferred based upon geotag selections from other users in a network. A matching engine may select an appropriate geotag given the current location of a user device or based upon historical location information associated with the user. | 09-22-2011 |
20150371269 | PROVIDING CONTENT BASED ON GEOGRAPHIC LOCATION DATA - Methods, system, and apparatus, including computer programs are encoded on a computer storage medium, for providing content based on geographic location data. In one aspect, a method includes receiving a request from a website for a map segment corresponding to a particular location. Keywords are extracted from the website as targeting criteria for the particular location. The targeting criteria is associated with the particular location. A subsequent request for advertising content associated with the particular location is received. One or more advertising content items are selected based on the targeting criteria. The selected advertising content items are provided responsive to the subsequent request. | 12-24-2015 |
Patent application number | Description | Published |
20130275827 | Multi-Section Non-Binary LDPC Decoder - Various embodiments of the present invention provide systems and methods for decoding codewords in a multi-section non-binary LDPC decoder. For example, an LDPC decoder is disclosed that includes a variable node processor operable to perform variable node updates based at least in part on check node to variable node messages and to generate variable node to check node messages, and a check node processor operable to process the variable node to check node messages in groups across each of a plurality of sections of an H matrix and to generate the check node to variable node messages. | 10-17-2013 |
20130305114 | Symbol Flipping LDPC Decoding System - Various embodiments of the present inventions provide a symbol flipping LDPC decoding system. For example, a symbol flipping data processing system is disclosed that includes a low density parity check decoder operable to decode codewords and to identify unsatisfied parity checks, a symbol flipping controller operable to change values of at least one symbol in the codewords based on the unsatisfied parity checks to assist the low density parity check decoder to decode the codewords, a scheduler operable to control a decoding and symbol flipping mode in the low density parity check decoder and the symbol flipping controller, and a hard decision queue operable to store hard decisions for converged codewords from the low density parity check decoder. | 11-14-2013 |
20140223114 | Buffer for Managing Data Samples in a Read Channel - The disclosure is directed to a system for managing data samples utilizing a time division multiplexing controller to allocate time slots for accessing a sample memory according to one or more modes of operation. The time division multiplexing controller is configured to allocate slots for concurrent access by a sample controller, a plurality of detectors, and a noise predictive calibrator when a normal mode is enabled. The time division multiplexing controller is further configured to allocate slots excluding at least one of the sample controller, the plurality of detectors, and the noise predictive calibrator from accessing the sample memory when a retry mode is enabled. In some embodiments, the time division multiplexing controller is further configured to allocate time slots for one or more clients other than the sample controller, the plurality of detectors, and the noise predictive calibrator. | 08-07-2014 |
20140337676 | Systems and Methods for Processing Data With Microcontroller Based Retry Features - A data processing system is disclosed including a data detector, a data decoder and a microcontroller. The data detector is operable to apply a data detection algorithm to generate detected values for data sectors. The data decoder is operable to apply a data decode algorithm to a decoder input derived from the detected values to yield decoded values. The microcontroller is operable to configure the data detector and the data decoder to apply the data detection algorithm and the data decode algorithm. | 11-13-2014 |
Patent application number | Description | Published |
20080244149 | Multiple module computer system and method - A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system. | 10-02-2008 |
20100174844 | MULTIPLE MODULE COMPUTER SYSTEM AND METHOD INCLUDING DIFFERENTIAL SIGNAL CHANNEL COMPRISING UNDIRECTIONAL SERIAL BIT CHANNELS - A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system. | 07-08-2010 |
20130024596 | Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits - A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system. | 01-24-2013 |
20130097352 | Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits - A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system. | 04-18-2013 |
20130198430 | Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits - A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system. | 08-01-2013 |
20140195713 | Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits - A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system. | 07-10-2014 |
20150026373 | Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits - A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system. | 01-22-2015 |
20150254205 | Low Cost, High Performance and High Data Throughput Server Blade - A server blade insertable into a chassis of a blade server system includes a main circuit board coupled to the chassis upon insertion, a plurality of connectors residing on the main circuit board, a plurality of grouped hard disk drives, and a plurality of computer modules, each insertable into a corresponding one of the connectors. Each of the grouped hard disk drives couples to one or more of the computer modules. Each of the grouped hard disk drives includes a first hard disk drive exposed proximate to a front side of the chassis, and a second hard disk drive positioned between the first hard disk drive and a back side of the chassis. A subset of the grouped hard disk drives includes a first grouped hard disk drive and a second grouped hard disk drive stacked on the first grouped hard disk drive. | 09-10-2015 |