Patent application number | Description | Published |
20110170563 | APPARATUS AND METHOD FOR ENABLING QUANTUM-DEFECT-LIMITED CONVERSION EFFICIENCY IN CLADDING-PUMPED RAMAN FIBER LASERS - Cladding-pumped Raman fiber lasers and amplifiers provide high-efficiency conversion efficiency at high brightness enhancement. Differential loss is applied to both single-pass configurations appropriate for pulsed amplification and laser oscillator configurations applied to high average power cw source generation. | 07-14-2011 |
20130294468 | DIFFRACTIVE OPTICAL ELEMENTS FOR TRANSFORMATION OF MODES IN LASERS - Spatial mode conversion modules are described, with the capability of efficiently transforming a given optical beam profile, at one plane in space into another well-defined optical beam profile at a different plane in space, whose detailed spatial features and symmetry properties can, in general, differ significantly. The modules are comprised of passive, high-efficiency, low-loss diffractive optical elements, combined with Fourier transform optics. Design rules are described that employ phase retrieval techniques and associated algorithms to determine the necessary profiles of the diffractive optical components. System augmentations are described that utilize real-time adaptive optical techniques for enhanced performance as well as power scaling. | 11-07-2013 |
20150340835 | DIFFRACTIVE OPTICAL ELEMENTS FOR TRANSFORMATION OF MODES IN LASERS - Spatial mode conversion modules are described, with the capability of efficiently transforming a given optical beam profile, at one plane in space into another well-defined optical beam profile at a different plane in space, whose detailed spatial features and symmetry properties can, in general, differ significantly. The modules are comprised of passive, high-efficiency, low-loss diffractive optical elements, combined with Fourier transform optics. Design rules are described that employ phase retrieval techniques and associated algorithms to determine the necessary profiles of the diffractive optical components. System augmentations are described that utilize real-time adaptive optical techniques for enhanced performance as well as power scaling. | 11-26-2015 |
Patent application number | Description | Published |
20090222710 | SELECTIVELY APPLIED HYBRID MIN-SUM APPROXIMATION FOR CONSTRAINT NODE UPDATES OF LDPC DECODERS - In accordance with one or more embodiments, a decoder may determine whether a lowest reliability value of a plurality of codeword bits that correspond to a particular output reliability value for a particular constraint node of a parity-check matrix is greater than a threshold value (e.g., an offset), and if so, selectively applies a modified min-sum approximation constraint node update with a reliability value modification (e.g., an offset or normalized min-sum approximation). | 09-03-2009 |
20100020429 | Converting Timing Errors Into Symbol Errors to Handle Write Mis-Synchronization in Bit-Patterned Media Recording Systems - A method includes: writing data to a bit-patterned media at times determined by a clock having a period that is offset from a bit island period by a fixed offset to create one insertion or one deletion approximately within a predetermined number of bit islands, reading the data, and correcting the read data using error correction. An apparatus that implements the method is also provided. | 01-28-2010 |
20100031115 | LOW DENSITY PARITY CHECK DECODER USING MULTIPLE VARIABLE NODE DEGREE DISTRIBUTION CODES - A decoding system comprises an iterative decoder that utilizes parity constraints to iteratively decode a block of data that consists of multiple code words, and a processor that controls the iterative decoder to selectively remove a subset of the parity constraints for a number of decoder iterations and include one or more of the selectively removed parity constraints in other decoder iterations. | 02-04-2010 |
20110096430 | Converting Timing Errors into Symbol Errors to Handle Write Mis-Synchronization in Bit-Patterned Media Recording Systems - A method includes writing data to a bit-patterned media at times determined by a clock having a period that is offset from a bit island period by a fixed offset to create one insertion or one deletion approximately within a predetermined number of bit islands, reading the data, and correcting the read data using error correction. An apparatus that implements the method is also provided. | 04-28-2011 |
20110296272 | OUTER CODE PROTECTION FOR SOLID STATE MEMORY DEVICES - Outer code words can span multiple data blocks, multiple die, or multiple chips of a memory device to protect against errors in the data stored in the blocks, die and/or chips. A solid state memory device is arranged in multiple data blocks, each block including an array of memory cells arranged in a plurality of pages. The data is encoded into inner code words and symbol-based outer code words. The inner code words and the symbol-based outer code words are stored in the memory cells of the multiple blocks. One or more inner code words are stored in each page of each block and one or more symbols of each outer code word are stored in at least one page of each block. The inner code words and the outer code words are read from the memory device and are used to correct the errors in the data. | 12-01-2011 |
20120278679 | Iterating Inner and Outer Codes for Data Recovery - A storage medium includes at least one data unit defining a plurality of symbol-based inner code words and a plurality of symbol-based outer code words. Each symbol included in one of the inner code words is also included in one of the outer code words. A processor is configured to perform a first iteration of inner code error correction on the plurality of symbol-based inner code words, a first iteration of outer code error correction on the plurality of symbol-based outer code words and a second iteration of inner code error correction on the plurality of symbol-based inner code words. In the first iteration of outer code error corrections, at least one of the outer code words is correctable. In the second iteration of inner code error correction, at least one of the inner code words is correctable. | 11-01-2012 |
20130006896 | Training Datasets for Memory Devices - Methods and systems involve the use of training datasets to determine one or more reference voltages used to read data in a memory unit. Approaches for accessing a memory device having multiple memory units includes storing a training dataset comprising at least one of a known data pattern and a codeword capable of being decoded in a training dataset field of each memory unit of a memory device. One or more reference voltages are determined using the training dataset stored in the memory unit. After the reference voltages have been determined using the training dataset, these reference voltages are used to read other fields of the memory unit. | 01-03-2013 |
20130094286 | DETERMINING OPTIMAL READ REFERENCE AND PROGRAMMING VOLTAGES FOR NON-VOLATILE MEMORY USING MUTUAL INFORMATION - Approaches for operating a memory device comprising memory cells are disclosed. Optimal values for one or more of programming voltages used to program memory cells of the memory device and read reference voltages used to read the memory cells are determined using a mutual information function, I(X; Y), where X represents data values programmed to the memory cells and Y represents data values read from the memory cells. The read reference and/or programming voltages used for reading and/or programming the memory cells are adjusted using the optimal values. | 04-18-2013 |
20130094288 | CATEGORIZING BIT ERRORS OF SOLID-STATE, NON-VOLATILE MEMORY - Bit errors affecting cells of a solid-state, non-volatile memory are assigned to at least a first or a second category based on a relative amount of voltage shift that caused the respective bit errors in the respective cells. A reference voltage used to access the respective cells is adjusted to manage the respective bit errors of the first category. Additional corrective measures are taken to manage the respective bit errors of the second category. | 04-18-2013 |
20130094289 | DETERMINATION OF MEMORY READ REFERENCE AND PROGRAMMING VOLTAGES - Symmetrical or asymmetrical noise distributions for voltages corresponding to symbols that can be stored in multi-level memory cells (MLCs) of a memory device are used to determine read reference and/or programming voltages. The read reference voltages and/or programming voltages for the MLCs are jointly determined using the symmetrical distributions and a maximum likelihood estimation (MLE) and/or by determining at least one of the read reference voltages and the programming voltages using the asymmetrical distributions. | 04-18-2013 |
20130094290 | SHIFTING CELL VOLTAGE BASED ON GROUPING OF SOLID-STATE, NON-VOLATILE MEMORY CELLS - Cells of a solid-state, non-volatile memory are assigned to one of a plurality of groups. Each group is defined by expected symbols stored in the cells in view of actual symbols read from the cells. Based on cell counts within the groups, it can be determined that a shift in a reference voltage will reduce a collective bit error rate of the cells. The shift can be applied to data access operations affecting the cells. | 04-18-2013 |
20130275829 | USING A SOFT DECODER WITH HARD DATA - A method for re-using a soft decoder involves receiving soft data and hard data from memory cells in a memory device, mapping the soft data to a first set of soft information, mapping the hard data to a second set of soft information, and using the soft decoder to decode both the first set and second set of soft information. | 10-17-2013 |
20140269059 | SHIFTING CELL VOLTAGE BASED ON GROUPING OF SOLID-STATE, NON-VOLATILE MEMORY CELLS - Cells of a solid-state, non-volatile memory are assigned to one of a plurality of groups. Each group is defined by expected symbols stored in the cells in view of actual symbols read from the cells. Based on cell counts within the groups, it can be determined that a shift in a reference voltage will reduce a collective bit error rate of the cells. The shift can be applied to data access operations affecting the cells. | 09-18-2014 |
20150074487 | Memory Device with Variable Code Rate - Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, the apparatus has a solid-state non-volatile memory and a processing circuit configured to write data to a selected location of the memory. The data are arranged in the form of multi-bit code words each comprising a user data payload and associated parity data configured to correct one or more bit errors in the user data payload. The processing circuit adjusts at least a selected one of a size of the code words, a size of the user data payloads or a size of the parity data responsive to at least a selected one of an accumulated count of access operations upon the selected location or an error rate associated with the selected location. | 03-12-2015 |
20150089278 | VARIABLE DATA RECOVERY SCHEME HIERARCHY - Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory has a plurality of solid-state non-volatile memory cells. A processing circuit is connected to the memory and configured to direct the execution of a plurality of read error recovery routines in response to at least one uncorrectable read error in a data set retrieved from the memory. The recovery routines are executed in a selected order based on an elapsed recovery time parameter for each of the recovery routines and an estimated probability of success of each of the recovery routines. | 03-26-2015 |
Patent application number | Description | Published |
20150095338 | SYSTEMS AND METHODS FOR CATEGORIZING EXCEPTIONS AND LOGS - Techniques for categorizing exceptions and logs are described. For example, exception data of an exception that occurred on a machine is accessed. The exception data includes a stack trace of the exception. A determination is made that the exception is unique based on the stack track of the exception. Responsive to the determination that the exception is unique, the exception is categorized, by a machine including a memory and at least one processor, into one or more categories based on the stack trace of the exception. | 04-02-2015 |
20150095892 | SYSTEMS AND METHODS FOR EVALUATING A CHANGE PERTAINING TO A SERVICE OR MACHINE - Techniques for evaluating the performance of a service or machine after a change that pertains to the service or machine are described. For example, an indication of a change that pertains to a service or machine is received. In response to the receiving of the indication of the change, using at least one computer processor, a performance of the service or machine after the change is evaluated. The evaluation may be based on a particular rule for evaluating the performance of the service or machine after the change. An evaluation result is generated based on the evaluating of the performance of the service or machine after the change. The evaluation result indicates the quality of the performance of the service or machine after the change. | 04-02-2015 |
20160036675 | IDENTIFYING A BOTTLENECK IN A DATA TRANSFER - A system, methods and apparatus are provided for determining the locus of a bottleneck in a data transfer between a data receiver (e.g., a client device) and a data sender (e.g., a computer server). The locus may be one of a receiver realm encompassing the data receiver (especially a receiver application that consumes the data), a sender realm encompassing the data sender (especially a sender application that produces the data), and a communication link realm that encompasses the communication link(s) over which the data are conveyed (and possibly network-layer protocols and lower that use the communication link(s)). A monitor entity may employ a state-machine model to represent and track progress of a given data transfer between states, using information collected from the data receiver and data sender to identify state transitions. Given a time at which a transfer was delayed or halted, the monitor outputs the locus of the problem. | 02-04-2016 |
Patent application number | Description | Published |
20090327815 | Process Reflection - Process reflection techniques are described in which a reflected process is created to facilitate analysis of a process. Events are detected to initiate reflection of a target process. Process reflection of a target process may be initiated by an external process or by the target process itself. A reflected process of the target process is created. In an implementation, data defining the target process is replicated, copied, or otherwise collected from the target process to create the reflected process. Then, analysis may be performed on the reflected process while execution of the target process continues. | 12-31-2009 |
20100064177 | NETWORK HANG RECOVERY - A method of detecting a network hang and restoring an application that communicates on a connection giving rise to the network hang. A user experience may be improved by providing the user with an option to restore the hung application without losing unsaved data or state information. The network hang may be detected when the user tries to terminate the application. The method may include determining whether the network hang is recoverable, which may involve diagnosing a type of the hang. If recoverable, a network connection reset mechanism may be triggered by instructing a network stack of the computer to terminate the network connection. | 03-11-2010 |
20110214015 | NETWORK HANG RECOVERY - A method of detecting a network hang and restoring an application that communicates on a connection giving rise to the network hang. A user experience may be improved by providing the user with an option to restore the hung application without losing unsaved data or state information. The network hang may be detected when the user tries to terminate the application. The method may include determining whether the network hang is recoverable, which may involve diagnosing a type of the hang. If recoverable, a network connection reset mechanism may be triggered by instructing a network stack of the computer to terminate the network connection. | 09-01-2011 |
20120137167 | SYSTEMATIC MITIGATION OF MEMORY ERRORS - A system and method for mitigating memory errors in a computer system. Faulty memory is identified and tested by a memory manager of an operating system. The memory manager may perform diagnostic tests while the operating system is executing on the computer system. Regions of memory that are being used by software components of the computer system may also be tested. The memory manager maintains a stored information about faulty memory regions. Regions are added to the stored information when they are determined to be faulty by a diagnostic test tool. Memory regions are allocated to software components by the memory manager after checking the stored information about faulty memory regions. This ensures a faulty memory region is never allocated to a software component of the computer system. | 05-31-2012 |
20140181577 | SYSTEMATIC MITIGATION OF MEMORY ERRORS - A system and method for mitigating memory errors in a computer system. Faulty memory is identified and tested by a memory manager of an operating system. The memory manager may perform diagnostic tests while the operating system is executing on the computer system. Regions of memory that are being used by software components of the computer system may also be tested. The memory manager maintains a stored information about faulty memory regions. Regions are added to the stored information when they are determined to be faulty by a diagnostic test tool. Memory regions are allocated to software components by the memory manager after checking the stored information about faulty memory regions. This ensures a faulty memory region is never allocated to a software component of the computer system. | 06-26-2014 |
20150243372 | SYSTEMATIC MITIGATION OF MEMORY ERRORS - A system and method for mitigating memory errors in a computer system. Faulty memory is identified and tested by a memory manager of an operating system. The memory manager may perform diagnostic tests while the operating system is executing on the computer system. Regions of memory that are being used by software components of the computer system may also be tested. The memory manager maintains a stored information about faulty memory regions. Regions are added to the stored information when they are determined to be faulty by a diagnostic test tool. Memory regions are allocated to software components by the memory manager after checking the stored information about faulty memory regions. This ensures a faulty memory region is never allocated to a software component of the computer system. | 08-27-2015 |
Patent application number | Description | Published |
20100170075 | Method of Manufacturing Multicolored Illuminator - A method of manufacturing a multicolored illuminator is disclosed. In an embodiment, a first transparent sheet ( | 07-08-2010 |
20100195349 | Light Source of Varying Thickness - An apparatus and method for a light source are disclosed. The apparatus comprises a light guide including light extracting features and at least one light source placed near an end of the light guide. Light from the light source gets deflected by the light extracting features and emanates in a predetermined pattern along a surface of the light guide. The light guide has different thicknesses in different parts. | 08-05-2010 |
20100283376 | Multicolored Linear Light Source - A multicolored linear light source is disclosed. In an embodiment the multicolored linear light source ( | 11-11-2010 |
20110316410 | PHOTOLUMINESCENT LIGHT SOURCE WITH LENSES - An apparatus for providing a photoluminescent light source is disclosed. In one embodiment, the apparatus comprises a light source that emanates light of a particular spectrum, photoluminescent material which converts light from the light source to light of another spectrum, and a selective mirror which reflects light generated by the light source and transmits light generated by the photoluminescent material. The photoluminescent material may be arranged so as to provide a plurality of light sources that emanate light of various colors. In an embodiment, the photoluminescent material is situated in small regions within a transparent material and lenses are used to collimate light emitted from the small regions. | 12-29-2011 |
20120207458 | CAMERA BEHIND A PHOTOLUMINESCENT LIGHT SOURCE - An apparatus for providing a photoluminescent light source is disclosed. In one embodiment, the apparatus comprises a light source that emanates light of a particular spectrum, a camera, and a selective mirror placed between the light source and camera. The selective mirror transmits light of a spectrum detected by the camera and reflects light of a spectrum generated by the light source. The light source is transparent to light incident on its face. | 08-16-2012 |
20120234486 | METHOD OF MANUFACTURING MULTICOLORED ILLUMINATOR - A method of manufacturing a multicolored illuminator is disclosed. In an embodiment, a first transparent sheet ( | 09-20-2012 |
20130069519 | MULTICOLORED LINEAR LIGHT SOURCE - A multicolored linear light source is disclosed. In an embodiment, the multicolored linear light source comprises a linear light source emanating light of a first spectrum, and regions of photoluminescent material. The light of the first spectrum interacts with regions of photoluminescent material to give light of a different spectrum. The composition of different regions of photoluminescent material is different, providing light of different spectra in different regions. Coupled to each region of photoluminescent material is a columnar light guide such that light produced by the regions traverses respective columnar light guides and gets extracted. | 03-21-2013 |
20140091703 | ENERGY EFFICIENT LIGHT SOURCE COMPRISING PHOTOLUMINESCENT MATERIAL AND A SELECTIVE MIRROR - An energy efficient light source comprising photoluminescent material and a selective mirror is disclosed. In an embodiment, a first light source emanates light of a particular spectrum, a layer of photoluminescent material surrounding the first light source absorbs light of the spectrum emanated by the first light source and emanates light of a different spectrum, and a selective mirror surrounding the layer of photoluminescent material reflects light emanated by the first light source and transmits light emanated by the photoluminescent material. | 04-03-2014 |
Patent application number | Description | Published |
20110219361 | CORRECT REFACTORING OF CONCURRENT SOFTWARE - Automated refactorings as implemented in modern IDEs for Java usually make no special provisions for concurrent code. Thus, refactored programs may exhibit unexpected new concurrent behaviors. We analyze the types of such behavioral changes caused by current refactoring engines and develop techniques to make them behavior-preserving, ranging from simple techniques to deal with concurrency-related language constructs to a framework that computes and tracks synchronization dependencies. By basing our development directly on the Java Memory Model we can state and prove precise correctness results about refactoring concurrent programs. We show that a broad range of refactorings are not influenced by concurrency at all, whereas other important refactorings can be made behavior-preserving for correctly synchronized programs by using our framework. Experience with a prototype implementation shows that our techniques are easy to implement and require only minimal changes to existing refactoring engines. | 09-08-2011 |
20120102471 | GENERATING SPECIFICATIONS OF CLIENT-SERVER APPLICATIONS FOR STATIC ANALYSIS - Systems and methods are provided for creating a data structure associated with a software application that is based on at least one framework. According to the method, source code and at least one configuration file of the software application is analyzed by at least one framework-specific processor so as to determine entry point information indicating entry points in the source code, request attribute access information indicating where attributes attached to a request data structure are read and written, and forward information indicating forwards performed by the software application. A data structure for a static analysis engine is created based on this information. The data structure includes a list of synthetic methods that model framework-related behavior of the software application, and a list of entry points indicating the synthetic methods and/or application methods of the software application that can be invoked by the framework. | 04-26-2012 |
20120102474 | STATIC ANALYSIS OF CLIENT-SERVER APPLICATIONS USING FRAMEWORK INDEPENDENT SPECIFICATIONS - Systems and methods are provided for statically analyzing a software application that is based on at least one framework. According to the method, source code of the software application and a specification associated with the software application are analyzed. The specification includes a list of synthetic methods that model framework-related behavior of the software application, and a list of entry points indicating the synthetic methods and/or application methods of the software application that can be invoked by the framework. Based on the source code and the specification, intermediate representations for the source code and the synthetic methods are generated. Based on the intermediate representations and the specification, call graphs are generated to model which application methods of the software application invoke synthetic methods or other application methods of the software application. The software application is statically analyzed based on the call graphs and the intermediate representations so as to generate analysis results for the software application. | 04-26-2012 |
20120110551 | SIMULATING BLACK BOX TEST RESULTS USING INFORMATION FROM WHITE BOX TESTING - Systems, methods are program products for simulating black box test results using information obtained from white box testing, including analyzing computer software (e.g., an application) to identify a potential vulnerability within the computer software application and a plurality of milestones associated with the potential vulnerability, where each of the milestones indicates a location within the computer software application, tracing a path from a first one of the milestones to an entry point into the computer software application, identifying an input to the entry point that would result in a control flow from the entry point and through each of the milestones, describing the potential vulnerability in a description indicating the entry point and the input, and presenting the description via a computer-controlled output medium. | 05-03-2012 |
20120131670 | Global Variable Security Analysis - A method includes determining selected global variables in a program for which flow of the selected global variables through the program is to be tracked. The selected global variables are less than all the global variables in the program. The method includes using a static analysis performed on the program, tracking flow through the program for the selected global variables. In response to one or more of the selected global variables being used in security-sensitive operations in the flow, use is analyzed of each one of the selected global variables in a corresponding security-sensitive operation. In response to a determination the use may be a potential security violation, the potential security violation is reported. Apparatus and computer program products are also disclosed. | 05-24-2012 |
20120174082 | REFACTORING PROGRAMS FOR FLEXIBLE LOCKING - Disclosed is a novel computer implemented system, on demand service, computer program product and a method that provides a set of lock usages that improves concurrency resulting in execution performance of the software application by reducing lock contention through refactoring. More specifically, disclosed is a method to refactor a software application. The method starts with accessing at least a portion of a software application that can execute in an operating environment where there are more two or more threads of execution. Next, a determination is made if there is at least one lock used in the software application to enforce limits on accessing a resource. In response to determining that there is a lock with a first type of construct with a given set of features, the software application is refactored with the lock to preserve behavior of the software application. | 07-05-2012 |
20120254839 | SIMULATING BLACK BOX TEST RESULTS USING INFORMATION FROM WHITE BOX TESTING - Systems, methods are program products for simulating black box test results using information obtained from white box testing, including analyzing computer software (e.g., an application) to identify a potential vulnerability within the computer software application and a plurality of milestones associated with the potential vulnerability, where each of the milestones indicates a location within the computer software application, tracing a path from a first one of the milestones to an entry point into the computer software application, identifying an input to the entry point that would result in a control flow from the entry point and through each of the milestones, describing the potential vulnerability in a description indicating the entry point and the input, and presenting the description via a computer-controlled output medium. | 10-04-2012 |
20130054221 | GENERATING SPECIFICATIONS FOR EXPRESSION LANGUAGE EXPRESSIONS AND TAG LIBRARIES - Systems and methods are provided for creating a data structure associated with a software application that is based on at least one framework. According to the method, at least one Java Server Page file associated with the software application is analyzed. The Java Server Page (JSP) file includes at least one call to at least one library tag, and at least one Expression Language (EL) expression. A set of tag library usage information for the JSP file is generated based. The set of tag library usage information includes at least one variable, and a value of the at least one variable created by the at least one call. The EL expression is evaluated based on the variable and the value of the variable. A data structure is created for a static analysis engine based on EL expression. The data structure includes at least one Java expression representing the EL expression. | 02-28-2013 |
20130091487 | SCALABLE PROPERTY-SENSITIVE POINTS-TO ANALYSIS FOR PROGRAM CODE - A novel system, computer program product, and method are disclosed for transforming a program to facilitate points-to analysis. The method begins with accessing at least a portion of program code, such as JavaScript. In one example, a method with at least one dynamic property correlation is identified for extraction. When a method m is identified for extraction with the dynamic property correlation, a body of the loop l in the method m is extracted. A new method m | 04-11-2013 |
20130275951 | RACE DETECTION FOR WEB APPLICATIONS - A method of executing a rendering engine including executing a web application including at least two operations a single thread of execution, generating an auxiliary map for instrumentation accesses of the web application, and detecting and reporting concurrent memory accesses of the web application as a race. | 10-17-2013 |
20130290786 | AUTOMATED TESTING OF APPLICATIONS WITH SCRIPTING CODE - A novel system, computer program product, and method are disclosed for feedback-directed automated test generation for programs, such as JavaScript, in which execution is monitored to collect information that directs the test generator towards inputs that yield increased coverage. Several instantiations of the framework are implemented, corresponding to variations on feedback-directed random testing, in a tool called Artemis. | 10-31-2013 |
20140143880 | Global Variable Security Analysis - A method includes determining selected global variables in a program for which flow of the selected global variables through the program is to be tracked. The selected global variables are less than all the global variables in the program. The method includes using a static analysis performed on the program, tracking flow through the program for the selected global variables. In response to one or more of the selected global variables being used in security-sensitive operations in the flow, use is analyzed of each one of the selected global variables in a corresponding security-sensitive operation. In response to a determination the use may be a potential security violation, the potential security violation is reported. Apparatus and computer program products are also disclosed. | 05-22-2014 |
20150220739 | Global Variable Security Analysis - A method includes determining selected global variables in a program for which flow of the selected global variables through the program is to be tracked. The selected global variables are less than all the global variables in the program. The method includes using a static analysis performed on the program, tracking flow through the program for the selected global variables. In response to one or more of the selected global variables being used in security-sensitive operations in the flow, use is analyzed of each one of the selected global variables in a corresponding security-sensitive operation. In response to a determination the use may be a potential security violation, the potential security violation is reported. Apparatus and computer program products are also disclosed. | 08-06-2015 |
Patent application number | Description | Published |
20100070973 | GENERIC WAIT SERVICE: PAUSING A BPEL PROCESS - A generic wait service for facilitating the pausing of service-oriented applications. In one set of embodiments, the generic wait service receives, from a paused instance of an application, an initiation message comprising a set of key attributes and an exit criterion. The key attributes uniquely identify the paused instance, and the exit criterion identifies a condition that should be satisfied before the paused instance is allowed to proceed. The generic wait service then receives, from one or more event producers, notification messages comprising status information (e.g., statuses of business events) and information correlating the notification messages to particular instances. If a notification message is determined to be correlated to the paused instance, the generic wait service evaluates the exit criterion based on the status information included in the message. If the exit criterion is satisfied, the paused instance is notified of the status information and is allowed to proceed. | 03-18-2010 |
20110218813 | CORRELATING AND MAPPING ORIGINAL ORDERS WITH NEW ORDERS FOR ADJUSTING LONG RUNNING ORDER MANAGEMENT FULFILLMENT PROCESSES - A computer-readable medium, computer-implemented method, and system are provided. In one embodiment, a new order header object and an original order header object that share a source order number are selected, and one or more new order line objects based on the new order header object are also selected. One or more original order line objects based on the original order header object are selected and the one or more new order line objects and the one or more original order line objects are compared. Where a new order line object and an original order line object match, a reference identity of the new order line object is set to an identity of an original order line object. | 09-08-2011 |
20110218922 | COST OF CHANGE FOR ADJUSTING LONG RUNNING ORDER MANAGEMENT FULFILLMENT PROCESSES FOR A DISTRIBUTED ORDER ORCHESTRATION SYTEM - A computer-readable medium, computer-implemented method, and system are provided. In one embodiment, a business process is created, and a cost of change value for the business process is defined. An executable process that is generated from the business process is executed, and a change request is received. It is determined whether the cost of change value is greater than a threshold value, and, when the cost of change value is not greater than the threshold value, the change request is initiated. | 09-08-2011 |
20110218923 | TASK LAYER SERVICE PATTERNS FOR ADJUSTING LONG RUNNING ORDER MANAGEMENT FULFILLMENT PROCESSES FOR A DISTRIBUTED ORDER ORCHESTRATION SYSTEM - A computer-readable medium, computer-implemented method, and system are provided. In one embodiment, a task layer service pattern is created, and a task layer service is created from the task layer service pattern. The task layer service is assigned to a step of an executable process, and the step of the executable process is executed. The task layer service is executed in order to invoke a fulfillment service. | 09-08-2011 |
20130318029 | DISTRIBUTED ORDER ORCHESTRATION SYSTEM WITH EXTENSIBLE FLEX FIELD SUPPORT - A distributed order orchestration system publishes one or more newly generated artifacts that are generated as a result of generating one or more extensible flex fields to a rule dictionary. The distributed order orchestration system then imports the one or more newly generated artifacts within the rule dictionary as one or more facts. The distributed order orchestration system then creates one or more rules for the rule dictionary that references the one or more facts. | 11-28-2013 |
20140282602 | GENERIC WAIT SERVICE: PAUSING A BPEL PROCESS - A method of pausing a plurality of service-oriented application (SOA) instances may include receiving, from an instance of an SOA entering a pause state, an initiation message. The initiation message may include an exit criterion that identifies a business condition that must be satisfied before the instance of the SOA exits the pause state. The method may also include receiving a notification from an event producer, the notification comprising a status of a business event and determining whether the status of the business event satisfies the business condition of the exit criterion. The method may additionally include sending, in response to a determination that the status of the business event satisfies the business condition of the exit criterion, an indication to the instance of the SOA that the business condition has been satisfied such that the instance of the SOA can exit the pause state. | 09-18-2014 |
Patent application number | Description | Published |
20120047353 | System and Method Providing Run-Time Parallelization of Computer Software Accommodating Data Dependencies - A system and method of parallelizing programs employs runtime instructions to identify data accessed by program portions and to assign those program portions to particular processors based on potential overlap between the access data. Data dependence between different program portions may be identified and used to look for pending “predicate” program portions that could create data dependencies and to postpone program portions that may be dependent while permitting parallel execution of other program portions. | 02-23-2012 |
20120066690 | System and Method Providing Run-Time Parallelization of Computer Software Using Data Associated Tokens - A system and method of parallelizing programs assigns write tokens and read tokens to data objects accessed by computational operations. During run time, the write sets and read sets for computational operations are resolved and the computational operations executed only after they have obtained the necessary tokens for data objects corresponding to the resolved write and read sets. A data object may have unlimited read tokens but only a single write token and the write token may be released only if no read tokens are outstanding. Data objects provide a wait list which serves as an ordered queue for computational operations waiting for tokens. | 03-15-2012 |
20120180062 | System and Method for Controlling Excessive Parallelism in Multiprocessor Systems - Execution of a computer program on a multiprocessor system is monitored to detect possible excess parallelism causing resource contention and the like and, in response, to controllably limit the number of processors applied to parallelize program components. | 07-12-2012 |
20130212321 | Apparatus, System, and Method for Auto-Commit Memory Management - Apparatuses, systems, methods, and computer program products are disclosed. A method includes receiving a request to copy data from a first location to a second location. The data may be associated with an identifier known to a client that initiated the request. One of the locations may include an auto-commit buffer of a non-volatile device. An auto-commit buffer may be configured to commit stored data from the auto-commit buffer to a non-volatile medium of a non-volatile device in response to a restart event. A method includes copying the data from the first location to the second location. A method includes preserving the identifier known to the client and an association between the identifier and a location of the data at the second location such that client can retrieve the data based on the identifier known to the client. | 08-15-2013 |
20140259024 | Computer System and Method for Runtime Control of Parallelism in Program Execution - A computer system and method are provided to assess a proper degree of parallelism in executing programs to obtain efficiency objectives, including but not limited to increases in processing speed or reduction in computational resource usage. This assessment of proper degree of parallelism may be used to actively moderate the requests for threads by application processes to control parallelism when those efficiency objectives would be furthered by this control. | 09-11-2014 |
Patent application number | Description | Published |
20120147266 | SHARED-PLL AUDIO CLOCK RECOVERY IN MULTIMEDIA INTERFACES - A bit stream includes playback data having an associated clock rate and a variable reference clock that is synchronized to the bit stream. A playback clock recovery signal and a data recovery signal are generated in response to the received reference clock. A playback clock frequency signal is generated in response to the playback clock recovery signal. A recovered playback clock is generated by using a divide by M divider, wherein the value of M used by the divide by M divider is determined in response to a programmable multiple of the clock rate associated with the playback information. | 06-14-2012 |
20130010990 | APPARATUS AND METHOD FOR DRIVING PARASITIC CAPACITANCES USING DIFFUSION REGIONS UNDER A MEMS STRUCTURE - A semiconductor microphone including a silicon substrate having a perimeter; an N-well diffused into the substrate at the perimeter; a deformable diaphragm disposed over at least a portion of the silicon substrate and in contact with at least a portion of the perimeter; and a signal channel in electrical communication with the diaphragm. The signal channel includes a microphone output channel and a feedback output channel. The diaphragm produces an electric signal on the signal channel in response to deformation of the diaphragm and a portion of the electric signal is transmitted on the feedback output channel to the N-well. | 01-10-2013 |
20130039500 | TRIM METHOD FOR CMOS-MEMS MICROPHONES - Systems and methods for adjusting a bias voltage and gain of the microphone to account for variations in a thickness of a gap between a movable membrane and a stationary backplate in a MEMS microphone due to the manufacturing process. The microphone is exposed to acoustic pressures of a first magnitude and a sensitivity of the microphone is evaluated according to a predetermined sensitivity protocol. The bias voltage of the microphone is adjusted when the microphone does not meet the sensitivity protocol. The microphone is then exposed to acoustic waves of a second magnitude that is greater than the first magnitude and a stability of the microphone is evaluated according to a predetermined stability protocol. The bias voltage and the gain of the microphone are adjusted when the microphone does not meet the stability protocol. | 02-14-2013 |
20140363025 | DIGITAL MICROPHONE INTERFACE SUPPORTING MULTIPLE MICROPHONES - Extending a microphone interface. One microphone interface extension includes a controller, a parent microphone, and a child microphone. The controller outputs a controller clock signal. The parent microphone receives the controller clock signal and generates a first data signal. The child microphone generates a second data signal and outputs the second data signal to the first parent microphone. The parent microphone receives the second data signal from the child microphone and outputs a combined data signal to the controller based on the first data signal and the second data signal. The parent microphone outputs the combined data signal to the controller on a phase of a microphone clock signal derived from the controller clock signal. | 12-11-2014 |
20150086043 | SYSTEM AND METHOD FOR ADJUSTING MICROPHONE FUNCTIONALITY - An adjustable microphone. The microphone includes a MEMS microphone, a charge pump, a preamplifier, a first analog-to-digital converter, a root mean square (RMS) power detector, and a logic circuit. The MEMS microphone is configured to provide a signal indicative of sound detected by the MEMS microphone. The charge pump provides a bias voltage to the MEMS microphone. The preamplifier receives the signal from the MEMS microphone, and outputs an amplified signal indicative of sound detected by the MEMS microphone. The first analog-to-digital converter receives the amplified signal and converts the amplified signal to a digital signal. The root mean square power detector is configured to detect a power level of the amplified signal and output an indication of the power of the amplified signal. The logic circuit receives the RMS power detector output and a control input, and adjusts the operation of the microphone based on the control input. | 03-26-2015 |
20150281818 | MICROPHONE SYSTEM WITH DRIVEN ELECTRODES - Systems and methods for controlling parameters of a MEMS microphone. The microphone system includes a MEMS microphone and a controller. The MEMS microphone includes a movable electrode, a stationary electrode, and a driven electrode. The movable electrode has a first side and a second side that is opposite the first side. The movable electrode is configured such that acoustic pressures acting on the first side and the second of the movable electrode cause movement of the movable electrode. The stationary electrode is positioned on the first side of the movable electrode. The driven electrode is configured to receive a control signal and alter a parameter of the MEMS microphone based on the control signal. The controller is configured to determine a voltage difference between the movable electrode and the stationary electrode. The controller is also configured to generate the control signal based on the voltage difference. | 10-01-2015 |
20150319538 | FREQUENCY MODULATED MICROPHONE SYSTEM - Systems and methods of sensing audio with a MEMS microphone that modulates a frequency of a phase-locked loop. The MEMS microphone includes a movable electrode and a stationary electrode. The movable electrode is configured such that acoustic pressures acting on the movable electrode cause movement of the movable electrode. A voltage-controlled oscillator of the phase-locked loop is coupled to the MEMS microphone and receives a control signal. The voltage-controlled oscillator also generates an oscillating signal based on the control signal and a capacitance between the movable electrode and the stationary electrode. A phase detector of the phase-locked loop receives and determines a phase difference between the oscillating signal and a reference signal. The phase detector further generates the control signal based on the phase difference. A controller is configured to receive the control signal and determine an audio signal based on the control signal. | 11-05-2015 |
Patent application number | Description | Published |
20150278327 | ASYNCHRONOUS GLOBAL INDEX MAINTENANCE DURING PARTITION MAINTENANCE - Techniques for maintaining a global index in response to a partition being dropped are provided. In response to an instruction to drop a partition, partition identification data that identifies the partition is stored. Index entries, in the global index, that correspond to the dropped partition become “orphaned” entries. Later, an execution plan for a query is processed, where the execution plan targets a global index. During execution of the execution plan, one or more index entries are accessed. For each accessed index entry, the partition identification data is analyzed to determine if the index entry is an orphaned entry. If so, then the index entry is ignored for purposes of the query. Later, the global index may be updated to delete each orphaned entry. Such deletion may occur much later, such as during a time when the database is not queried or updated frequently. | 10-01-2015 |
20150302035 | PARTIAL INDEXES FOR PARTITIONED TABLES - Techniques for creating and using partial indexes are provided. A partial index is an index that indexes one or more partitions of a partitioned table and does not index one or more other partitions of the partitioned table. Thus, if a partition of a partitioned table is rarely used, then an index may index all other partitions of the partitioned table or at least only those partitions that are written to or read from relatively frequently. Also, in preparation for loading data into a partition, indexing for the partition may be “turned off”, effectively making a full index a partial index. While the data is loaded into the partition, the partial index is still available for query processing. After the data is loaded into the partition, indexing for the partition is “turned on”, which causes the data in the partition to be indexed by the partial index. | 10-22-2015 |
20150347401 | MOVING DATA BETWEEN PARTITIONS - Techniques are provided for moving data between partitions. Such a process may be performed without requiring any locks that block transactions that target a partition from being executed. Instead, such transactions may proceed while a move operation is being performed. The move operation involves copying data from the targeted partition to another partition that is hidden from (or “invisible” to) those transactions that attempt to read from or write to the partition. During the move operation, changes that are made to the partition are also reflected in a journal. Eventually, the changes reflected in the journal are drained and applied to the hidden partition. Once the partition and the hidden partition are synchronized, the identities of the partitions are swapped so that future transactions will target the previously-hidden partition instead of the previously-viewable partition. | 12-03-2015 |
Patent application number | Description | Published |
20130262937 | NODE DEATH DETECTION BY QUERYING - Systems, methods, and other embodiments associated with detecting a node death in a clustered distributed system are described. In one embodiment, a method includes transmitting a ping message to a peer node in the network. If a reply to the ping message is not received from the peer node, a query is sent to table of port identifiers that lists ports in the cluster. In one embodiment, the query includes a port identifier associated with the peer node. The peer node is declared as inactive/dead when the query fails to locate a match in the table for the port identifier. When the query locates a match in the table for the port identifier, another ping message is periodically transmitted to the peer node. | 10-03-2013 |
20150089008 | INTELLIGENT NETWORK RESOURCE MANAGER - A method and apparatus for intelligent network resource manager for distributed computing systems is provided. A first priority is assigned to a first virtual channel set that includes at least two virtual channels of a plurality of virtual channels associated with a physical communication channel. A second priority is assigned to a second virtual channel set that includes at least one virtual channel of the plurality of virtual channels. The first virtual channel set has more virtual channels than the second virtual channel set. Outbound messages of the first priority are directed to virtual channels of the first virtual channel set. Outbound messages of the second priority are directed to virtual channels of the second virtual channel set. The virtual channels are processed in a round-robin order, where processing includes sending the outbound messages over the physical communication channel. | 03-26-2015 |
20150089140 | Movement Offload To Storage Systems - In a write by-peer-reference, a storage device client writes a data block to a target storage device in the storage system by sending a write request to the target storage device, the write request specifying information used to obtain the data block from a source storage device in the storage system. The target storage device sends a read request to the source storage device for the data block. The source storage device sends the data block to the target storage device, which then writes the data block to the target storage device. The data block is thus written to the target storage device without the storage device client transmitting the data block itself to the target storage device. | 03-26-2015 |
Patent application number | Description | Published |
20130346695 | INTEGRATED CIRCUIT WITH HIGH RELIABILITY CACHE CONTROLLER AND METHOD THEREFOR - An integrated circuit includes a register including a field for defining a high reliability mode of the integrated circuit and a cache and memory controller coupled to the register and responsive to the high reliability mode to access a memory to store, in a row of the memory, a first multiple number of cache lines, a first multiple number of tags corresponding to the first multiple number of cache lines, and reliability data corresponding to at least the first multiple number of cache lines. | 12-26-2013 |
20140156975 | Redundant Threading for Improved Reliability - In some embodiments, a method for improving reliability in a processor is provided. The method can include replicating input data for first and second lanes of a processor, the first and second lanes being located in a same cluster of the processor and the first and second lanes each generating a respective value associated with an instruction to be executed in the respective lane, and responsive to a determination that the generated values do not match, providing an indication that the generated values do not match. | 06-05-2014 |
20140181587 | Hardware Based Redundant Multi-Threading Inside a GPU for Improved Reliability - A system and method for verifying computation output using computer hardware are provided. Instances of computation are generated and processed on hardware-based processors. As instances of computation are processed, each instance of computation receives a load accessible to other instances of computation. Instances of output are generated by processing the instances of computation. The instances of output are verified against each other in a hardware based processor to ensure accuracy of the output. | 06-26-2014 |
20140181594 | Signature-Based Store Checking Buffer - A system and method for optimizing redundant output verification, are provided. A hardware-based store fingerprint buffer receives multiple instances of output from multiple instances of computation. The store fingerprint buffer generates a signature from the content included in the multiple instances of output. When a barrier is reached, the store fingerprint buffer uses the signature to verify the content is error-free. | 06-26-2014 |
20140331207 | Determining the Vulnerability of Multi-Threaded Program Code to Soft Errors - The described embodiments include a program code testing system that determines the vulnerability of multi-threaded program code to soft errors. For multi-threaded program code, two to more threads from the program code may access shared architectural structures while the program code is being executed. The program code testing system determines accesses of architectural structures made by the two or more threads of the multi-threaded program code and uses the determined accesses to determine a time for which the program code is exposed to soft errors. From this time, the program code testing system determines a vulnerability of the program code to soft errors. | 11-06-2014 |
20140368513 | Software Only Intra-Compute Unit Redundant Multithreading for GPUs - A system, method and computer program product to execute a first and a second work-item, and compare the signature variable of the first work-item to the signature variable of the second work-item. The first and the second work-items are mapped to an identifier via software. This mapping ensures that the first and second work-items execute exactly the same data for exactly the same code without changes to the underlying hardware. By executing the first and second work-items independently, the underlying computation of the first and second work-item can be verified. Moreover, system performance is not substantially affected because the execution results of the first and second work-items are compared only at specified comparison points. | 12-18-2014 |
20140373028 | Software Only Inter-Compute Unit Redundant Multithreading for GPUs - A system, method and computer program product to execute a first and a second work-group, and compare the signature variables of the first work-group to the signature variables of the second work-group via a synchronization mechanism. The first and the second work-group are mapped to an identifier via software. This mapping ensures that the first and second work-groups execute exactly the same data for exactly the same code without changes to the underlying hardware. By executing the first and second work-groups independently, the underlying computation of the first and second work-groups can be verified. Moreover, system performance is not substantially affected because the execution results of the first and second work-groups are compared only at specified comparison points. | 12-18-2014 |
20140376320 | SPARE MEMORY EXTERNAL TO PROTECTED MEMORY - A memory subsystem employs spare memory cells external to one or more memory devices. In some embodiments, a processing system uses the spare memory cells to replace individual selected cells at the protected memory, whereby the selected cells are replaced on a cell-by-cell basis, rather than exclusively on a row-by-row, column-by-column, or block-by-block basis. This allows faulty memory cells to be replaced efficiently, thereby improving memory reliability and manufacturing yields, without requiring large blocks of spare memory cells. | 12-25-2014 |
20150067278 | Using Redundant Transactions to Verify the Correctness of Program Code Execution - In the described embodiments, a processor core (e.g., a GPU core) receives a section of program code to be executed in a transaction from another entity in a computing device. The processor core sends the section of program code to one or more compute units in the processor core to be executed in a first transaction and concurrently executed in a second transaction, thereby creating a “redundant transaction pair.” When the first transaction and the second transaction are completed, the processor core compares a read-set of the first transaction to a read-set of the second transaction and compares a write-set of the first transaction to a write-set of the second transaction. When the read-sets and the write-sets match and no transactional error condition has occurred, the processor core allows results from the first transaction to be committed to an architectural state of the computing device. | 03-05-2015 |
Patent application number | Description | Published |
20140108885 | HIGH RELIABILITY MEMORY CONTROLLER - An integrated circuit includes a memory having an address space and a memory controller coupled to the memory for accessing the address space in response to received memory accesses. The memory controller further accesses a plurality of data elements in a first portion of the address space, and reliability data corresponding to the plurality of data elements in a second portion of the address space. | 04-17-2014 |
20140143495 | METHODS AND APPARATUS FOR SOFT-PARTITIONING OF A DATA CACHE FOR STACK DATA - A method of partitioning a data cache comprising a plurality of sets, the plurality of sets comprising a plurality of ways, is provided. Responsive to a stack data request, the method stores a cache line associated with the stack data in one of a plurality of designated ways of the data cache, wherein the plurality of designated ways is configured to store all requested stack data. | 05-22-2014 |
20140143498 | METHODS AND APPARATUS FOR FILTERING STACK DATA WITHIN A CACHE MEMORY HIERARCHY - A method of storing stack data in a cache hierarchy is provided. The cache hierarchy comprises a data cache and a stack filter cache. Responsive to a request to access a stack data block, the method stores the stack data block in the stack filter cache, wherein the stack filter cache is configured to store any requested stack data block. | 05-22-2014 |
20140143499 | METHODS AND APPARATUS FOR DATA CACHE WAY PREDICTION BASED ON CLASSIFICATION AS STACK DATA - A method of way prediction for a data cache having a plurality of ways is provided. Responsive to an instruction to access a stack data block, the method accesses identifying information associated with a plurality of most recently accessed ways of a data cache to determine whether the stack data block resides in one of the plurality of most recently accessed ways of the data cache, wherein the identifying information is accessed from a subset of an array of identifying information corresponding to the plurality of most recently accessed ways; and when the stack data block resides in one of the plurality of most recently accessed ways of the data cache, the method accesses the stack data block from the data cache. | 05-22-2014 |
20140173378 | PARITY DATA MANAGEMENT FOR A MEMORY ARCHITECTURE - A processor system as presented herein includes a processor core, cache memory coupled to the processor core, a memory controller coupled to the cache memory, and a system memory component coupled to the memory controller. The system memory component includes a plurality of independent memory channels configured to store data blocks, wherein the memory controller controls the storing of parity bits in at least one of the plurality of independent memory channels. In some implementations, the system memory is realized as a die-stacked memory component. | 06-19-2014 |
20140173379 | DIRTY CACHELINE DUPLICATION - A method of managing memory includes installing a first cacheline at a first location in a cache memory and receiving a write request. In response to the write request, the first cacheline is modified in accordance with the write request and marked as dirty. Also in response to the write request, a second cacheline is installed that duplicates the first cacheline, as modified in accordance with the write request, at a second location in the cache memory. | 06-19-2014 |
20150100848 | DETECTING AND CORRECTING HARD ERRORS IN A MEMORY ARRAY - Hard errors in the memory array can be detected and corrected in real-time using reusable entries in an error status buffer. Data may be rewritten to a portion of a memory array and a register in response to a first error in data read from the portion of the memory array. The rewritten data may then be written from the register to an entry of an error status buffer in response to the rewritten data read from the register differing from the rewritten data read from the portion of the memory array. | 04-09-2015 |
20150278016 | METHOD AND APPARATUS FOR ENCODING ERRONEOUS DATA IN AN ERROR CORRECTION CODE PROTECTED MEMORY - A method and device are described for encoding erroneous data in an error correction code (ECC) protected memory. In one embodiment, incoming data including a plurality of data symbols and a data integrity marker is received. At least one extra symbol is used to mark the incoming data as error-free data or erroneous data (i.e., poison) based on the data integrity marker. ECC may be created to protect the data symbols. The ECC may include a plurality of check symbols, a plurality of unused symbols and the at least one extra symbol. In another embodiment, an error marker may be propagated from a single ECC word to all ECC words of data block (e.g., a cache line, a page, and the like) to prevent errors due to corruption of the error marker caused by faulty memory in the erroneous ECC word. | 10-01-2015 |
20150293845 | MULTI-LEVEL MEMORY HIERARCHY - Described is a system and method for a multi-level memory hierarchy. Each level is based on different attributes including, for example, power, capacity, bandwidth, reliability, and volatility. In some embodiments, the different levels of the memory hierarchy may use an on-chip stacked dynamic random access memory, (providing fast, high-bandwidth, low-energy access to data) and an off-chip non-volatile random access memory, (providing low-power, high-capacity storage), in order to provide higher-capacity, lower power, and higher-bandwidth performance. The multi-level memory may present a unified interface to a processor so that specific memory hardware and software implementation details are hidden. The multi-level memory enables the illusion of a single-level memory that satisfies multiple conflicting constraints. A comparator receives a memory address from the processor, processes the address and reads from or writes to the appropriate memory level. In some embodiments, the memory architecture is visible to the software stack to optimize memory utilization. | 10-15-2015 |