Patent application number | Description | Published |
20130138840 | Efficient Memory and Resource Management - The present system enables passing a pointer, associated with accessing data in a memory, to an input/output (I/O) device via an input/output memory management unit (IOMMU). The I/O device accesses the data in the memory via the IOMMU without copying the data into a local I/O device memory. The I/O device can perform an operation on the data in the memory based on the pointer, such that I/O device accesses the memory without expensive copies. | 05-30-2013 |
20130145051 | Direct Device Assignment - A system is enabled for configuring an IOMMU to provide direct access to system memory data by at least one I/O device/peripheral. Further, the IOMMU is configured to pass a pointer to at least one I/O device without having to translate the pointer. Further, commands are sent from a process within a guest operating system (OS) directly to a peripheral without intervention from a hypervisor. Further, the IOMMU is configured to grant peripherals access permissions to memory blocks to maintain isolation among peripherals. | 06-06-2013 |
20130145055 | Peripheral Memory Management - The present system enables an input/output (I/O) device to request memory for performing a direct memory access (DMA) of system memory. Further, the system uses an input/output memory management unit (IOMMU) to determine whether or not the system memory is available. The IOMMU notifies an operating system associated with the system memory if the system memory is not available, such that the operating system allocates non-system memory for use by the I/O device to perform the DMA. | 06-06-2013 |
20130262736 | MEMORY TYPES FOR CACHING POLICIES - The present system enables receiving a request from an I/O device to translate a virtual address to a physical address to access the page in system memory. One or more memory attributes of the page defining a cacheability characteristic of the page is identified. A response including the physical address and the cacheability characteristic of the page is sent to the I/O device. | 10-03-2013 |
20140181460 | PROCESSING DEVICE WITH ADDRESS TRANSLATION PROBING AND METHODS - A data processing device is provided that employs multiple translation look-aside buffers (TLBs) associated with respective processors that are configured to store selected address translations of a page table of a memory shared by the processors. The processing device is configured such that when an address translation is requested by a processor and is not found in the TLB associated with that processor, another TLB is probed for the requested address translation. The probe across to the other TLB may occur in advance of a walk of the page table for the requested address or alternatively a walk can be initiated concurrently with the probe. Where the probe successfully finds the requested address translation, the page table walk can be avoided or discontinued. | 06-26-2014 |
20140181461 | REPORTING ACCESS AND DIRTY PAGES - A method and apparatus for reporting events into at least one event log are presented. An “access” event entry may be added to an event log stored in memory when a peripheral device accesses an address of a memory page described by a page table entry (PTE). A “dirty” event entry may be added to an event log stored in memory when a page writes to a memory page. The event log may reside in an input/output memory management unit (IOMMU) that includes a translation lookaside buffer (TLB). The IOMMU may report the event log entries to system memory. When there is no entry in the TLB and a direct memory access (DMA) read operation enters the IOMMU, a PTE may be loaded into the TLB after updating an access log to calculate an address. If the DMA operation is not a read operation, both dirty and access logs may be updated. | 06-26-2014 |
Patent application number | Description | Published |
20080209130 | Translation Data Prefetch in an IOMMU - In an embodiment, a system memory stores a set of input/output (I/O) translation tables. One or more I/O devices initiate direct memory access (DMA) requests including virtual addresses. An I/O memory management unit (IOMMU) is coupled to the I/O devices and the system memory, wherein the IOMMU is configured to translate the virtual addresses in the DMA requests to physical addresses to access the system memory according to an I/O translation mechanism implemented by the IOMMU. The IOMMU comprises one or more caches, and is configured to read translation data from the I/O translation tables responsive to a prefetch command that specifies a first virtual address. The reads are responsive to the first virtual address and the I/O translation mechanism, and the IOMMU is configured to store data in the caches responsive to the read translation data. | 08-28-2008 |
20080281964 | Server discovery, spawning collector threads to collect information from servers, and reporting information - Server discovery, spawning collector threads to collect information from servers, and reporting such information, is disclosed. A method of one embodiment determines a number of servers communicatively coupled to a network. For each server, a collector thread is spawned to collect information regarding the server by sending requests to the server and receiving responses from the server. The collector threads can be spawned by and run on a computing device other than the number of servers, such that no computer-executable code is installed on the servers for collecting the information. Upon completion of the collector thread for each server, the information regarding the server as collected is stored to a database by one or more writer threads. The information may include dynamic load-oriented and function-oriented information regarding the servers, as well as static configuration information, from which server utilization-oriented statistics may be distilled to identify candidate servers for server consolidation. | 11-13-2008 |
20090006597 | Trust Evaluation - A solution for evaluating trust in a computer infrastructure is provided. In particular, a plurality of computing devices in the computer infrastructure evaluate one or more other computing devices in the computer infrastructure based on a set of device measurements for the other computing device(s) and a set of reference measurements. To this extent, each of the plurality of computing devices also provides a set of device measurements for processing by the other computing device(s) in the computer infrastructure. | 01-01-2009 |
20110022818 | IOMMU USING TWO-LEVEL ADDRESS TRANSLATION FOR I/O AND COMPUTATION OFFLOAD DEVICES ON A PERIPHERAL INTERCONNECT - An IOMMU for controlling requests by an I/O device to a system memory of a computer system includes control logic and a cache memory. The control logic may translate an address received in a request from the I/O device. If the request includes a transaction layer protocol (TLP) packet with a process address space identifier (PASID) prefix, the control logic may perform a two-level guest translation. Accordingly, the control logic may access a set of guest page tables to translate the address received in the request. A pointer in a last guest page table points to a first table in a set of nested page tables. The control logic may use the pointer in a last guest page table to access the set of nested page tables to obtain a system physical address (SPA) that corresponds to a physical page in the system memory. The cache memory stores completed translations. | 01-27-2011 |
20110023027 | I/O MEMORY MANAGEMENT UNIT INCLUDING MULTILEVEL ADDRESS TRANSLATION FOR I/O AND COMPUTATION OFFLOAD - An input/output memory management unit (IOMMU) configured to control requests by an I/O device to a system memory includes control logic that may perform a two-level guest translation to translate an address associated with an I/O device-generated request using translation data stored in the system memory. The translation data includes a device table having a number of entries. The control logic may select the device table entry for a given request by the using a device identifier that corresponds to the I/O device that generates the request. The translation data may also include a first set of I/O page tables including a set of guest page tables and a set of nested page tables. The selected device table entry for the given request may include a pointer to the set of guest translation tables, and a last guest translation table includes a pointer to the set of nested page tables | 01-27-2011 |
20110202724 | IOMMU Architected TLB Support - Embodiments allow a smaller, simpler hardware implementation of an input/output memory management unit (IOMMU) having improved translation behavior that is independent of page table structures and formats. Embodiments also provide device-independent structures and methods of implementation, allowing greater generality of software (fewer specific software versions, in turn reducing development costs). | 08-18-2011 |
20120017063 | MECHANISM TO HANDLE PERIPHERAL PAGE FAULTS - A page service request is received from a peripheral device requesting that a memory page be loaded into system memory. Page service request information corresponding to the received page service request is written as a queue entry into a queue structure in system memory. The processor is notified that the page request is present in the queue. The processor may be notified with an interrupt of a new queue entry. The processor processes the page service request and the peripheral device is notified of the completion of the processing of the request. | 01-19-2012 |
20130007379 | SECURE AND VIRTUALIZABLE PERFORMANCE COUNTERS - A method includes updating contents of a value storage element indicating a number of occurrences of an event. The updating is based on contents of a match storage element storing event qualification information. The method includes providing the contents of the value storage element to a first software module executing on at least one processor. The providing is based on contents of a protect storage element indicating access information. In at least one embodiment, the method includes executing a first software module on the at least one processor in a first mode of operation. In at least one embodiment, the method includes executing a second software module on the at least one processor in a second mode of operation. In at least one embodiment, the second mode is more privileged than the first mode. | 01-03-2013 |
20130080714 | I/O MEMORY TRANSLATION UNIT WITH SUPPORT FOR LEGACY DEVICES - An apparatus, method, and medium are disclosed for managing memory access from I/O devices. The apparatus comprises a memory management unit configured to receive, from an I/O device, a request to perform a memory access operation to a system memory location. The memory management unit is configured to detect that the request omits a memory access parameter, determine a value for the omitted parameter, and cause the memory access to be performed using the determined value. | 03-28-2013 |
20130080726 | INPUT/OUTPUT MEMORY MANAGEMENT UNIT WITH PROTECTION MODE FOR PREVENTING MEMORY ACCESS BY I/O DEVICES - A memory management unit is configured to receive requests for memory access from a plurality of I/O devices. The memory management unit implements a protection mode wherein the unit prevents memory accesses by the plurality of I/O devices by mapping memory access requests (from the I/O devices) to the same set of memory address translation data. When the memory management unit is not in the protected mode, the unit maps memory access requests from the plurality of I/O devices to different respective sets of memory address translation data. Thus, the memory management unit may protect memory from access by I/O devices using fewer address translation tables than are typically required (e.g., none). | 03-28-2013 |
20130159576 | METHOD AND APPARATUS FOR CONTROLLING SYSTEM INTERRUPTS - A method and apparatus are provided for controlling system management interrupts is disclosed. An interrupt filter comprises a memory, a comparator and a logic circuit. The memory is adapted to contain a list indicating one or more devices with permission associated with an interrupt signal. The comparator is adapted to receive an interrupt signal containing type information from the one or more devices. The comparator is adapted to compare the interrupt type against the list to determine if the one or more devices is permitted to send the interrupt signal. The logic circuit blocks or passes the interrupt signal in response to the result of the comparison. | 06-20-2013 |
20130159581 | METHOD AND APPARATUS FOR REMAPPING INTERRUPT TYPES - A method and apparatus are provided for controlling system management interrupts is disclosed. The method comprises: receiving an interrupt signal; determining a type associated with the interrupt signal; using the determined type to access control information indicating an action to be applied to the determined type of interrupt; and blocking, passing or remapping the interrupt signal in response to the control information. The apparatus comprises a memory, an interrupt unit and a logic circuit. The memory is adapted to store control information regarding a plurality of types of interrupt signals. The interrupt unit is adapted to receive the interrupt signal, and use the interrupt type contained in the interrupt signal to access the control information stored in the memory. The logic circuit is adapted to block, pass or remap said interrupt signal in response to the control information. | 06-20-2013 |
20140040560 | All Invalidate Approach for Memory Management Units - An input/output memory management unit (IOMMU) having an “invalidate all” command available to clear the contents of cache memory is presented. The cache memory provides fast access to address translation data that has been previously obtained by a process. A typical cache memory includes device tables, page tables and interrupt remapping entries. Cache memory data can become stale or be compromised from security breaches or malfunctioning devices. In these circumstances, a rapid approach to clearing cache memory content is provided. | 02-06-2014 |
20140068137 | Virtual Input/Output Memory Management Unit Within a Guest Virtual Machine - A virtual input/output memory management unit (IOMMU) is configured to provide a firewall around memory requests associated with an input/output (I/O) device. The virtual IOMMU uses data structures including a guest page table, a host page table and a general control register (i.e., GCR3) table. The guest page table is implemented in hardware to support the speed requirements of the virtual IOMMU. The GCR3 table is indexed using a virtual DeviceID parameter stored in a device table. | 03-06-2014 |
20140089609 | INTERPOSER HAVING EMBEDDED MEMORY CONTROLLER CIRCUITRY - A system is provided that includes an interposer having memory controller circuitry embedded therein. The interposer includes conductive vias that are embedded within and that extend through the interposer. The memory controller circuitry can be coupled to some of the conductive vias. In some implementations, other ones of the conductive vias are configured to be coupled to a processor and a memory module that can be mounted along a surface of the interposer. Conductive links are disposed on a surface of the interposer to couple the processor and the memory module to the memory controller circuitry. | 03-27-2014 |
20140101405 | REDUCING COLD TLB MISSES IN A HETEROGENEOUS COMPUTING SYSTEM - Methods and apparatuses are provided for avoiding cold translation lookaside buffer (TLB) misses in a computer system. A typical system is configured as a heterogeneous computing system having at least one central processing unit (CPU) and one or more graphic processing units (GPUs) that share a common memory address space. Each processing unit (CPU and GPU) has an independent TLB. When offloading a task from a particular CPU to a particular GPU, translation information is sent along with the task assignment. The translation information allows the GPU to load the address translation data into the TLB associated with the one or more GPUs prior to executing the task. Preloading the TLB of the GPUs reduces or avoids cold TLB misses that could otherwise occur without the benefits offered by the present disclosure. | 04-10-2014 |
20140173152 | TECHNIQUES FOR IDENTIFYING AND HANDLING PROCESSOR INTERRUPTS - A method for identifying and reporting interrupt behavior includes incrementing a counter when an interrupt signal is a designated type and is not received from an approved peripheral device, and performing a corrective action when the counter reaches a threshold value. In some embodiments, the designated type of the interrupt signal comprises a System Management Interrupt (SMI), which has the capability of halting operations at all processors within a system to execute associated instructions within a protected circumstance, resuming normal operations for each of the plurality of processors when the corrective action has been completed. In another embodiment, the corrective action includes creating a report identifying, within the same protected circumstance, the interrupt signal as an SMI. In some embodiments, the method performs a different corrective action when an interrupt signal is a designated type and is received from an approved peripheral device and decrements a counter. In some embodiments, the interrupt signal includes information indicating its source. | 06-19-2014 |
20140173236 | SECURE COMPUTER SYSTEM FOR PREVENTING ACCESS REQUESTS TO PORTIONS OF SYSTEM MEMORY BY PERIPHERAL DEVICES AND/OR PROCESSOR CORES - A computer system is provided for preventing peripheral devices and/or processor cores from accessing restricted portions of system memory. For example, the computer system can include a host bridge, system memory coupled to the host bridge via a first access bus, a security processor coupled to the host bridge via a memory access bus that allows the security processor to access system memory and to access the peripheral device, and a security processor memory management unit (SPMMU) coupled between the peripheral device and the host bridge. The security processor is configured to program the SPMMU via the memory access bus to specify a first restricted range of physical addresses in the system memory that the peripheral device is not permitted to access. The SPMMU can then process access requests from the peripheral device and deny access requests that are determined to be within the first restricted range. | 06-19-2014 |
20140173265 | Protecting Memory Contents During Boot Process - Embodiments include methods, systems, and computer storage devices directed to identifying that a trusted boot mode (TBM) control bit is set in an input/output memory management unit (IOMMU) and configuring the IOMMU to block a DMA request received by the IOMMU from a peripheral in response to the identifying. | 06-19-2014 |
20140181361 | NON-VOLATILE HYBRID MEMORY - Memory units and computer systems are provided. The computer systems include a memory unit. The memory unit includes a stable storage unit, an unstable storage unit, and a controller. The unstable storage unit stores pending write operations for the stable storage unit. The controller is configured to determine the locations in the unstable storage that store the pending write information and to selectively write the pending write operations to the stable storage unit when power to the memory unit is interrupted. | 06-26-2014 |
20150019765 | VIRTUAL INTERRUPT FILTER - A system for processing interrupts in a virtualized computing environment includes a virtual interrupt controller to provide virtual interrupts from peripherals to virtual machines. The system also includes a virtual interrupt filter that has an estimator circuit to provide an estimate of what proportion of interrupts from one or more of the peripherals are virtual interrupts. A determination is made as to whether the estimate satisfies a criterion; if it does, incoming interrupts are blocked. | 01-15-2015 |