Patent application number | Description | Published |
20080201292 | Method and apparatus for preserving control information embedded in digital data - Control information embedded in digital data is preserved by inputting digital data into a data processor, wherein the digital data includes real-time samples of recorded data and control information, the control information being organized in a format within the digital data, separating at least some of the control information from the recorded data, and storing the separated control information in a memory so that it is preserved. | 08-21-2008 |
20090238212 | SYSTEM AND METHOD FOR TRANSFERRING HIGH-DEFINITION MULTIMEDIA SIGNALS OVER FOUR TWISTED-PAIRS - A system and method for transferring high-definition multimedia signals over four twisted-pairs. The system includes a multimedia source for transmitting multimedia data and source-to-sink management data to a multimedia sink over a first channel, a second channel and a third channel wherein the multimedia source is further being capable of transmitting a clock signal to the multimedia sink over a fourth channel; and a multimedia sink for transferring sink-to-source management data to the multimedia source over the fourth channel. The clock signal and the sink-to-source management data are simultaneously transmitted over the fourth channel. Each of the channels comprises a single twisted-pair, thereby the channels can bounded in a twisted pair type cable comprising at least one of: Category 5, Category 5e, Category 6, and Category 6e. | 09-24-2009 |
20090327652 | METHOD FOR CONSTRUCTING A VARIABLE BITWIDTH VIDEO PROCESSOR - A method for designing a video processor with a variable and programmable bitwidth parameter. The method comprises selecting logical operations having propagation delay that scales linearly with the bitwidth; determining a desired tradeoff curve; and grouping instances of a logic operation having same properties; for a single instance of each logic operation, matching an actual curve of the logic operation to the desired tradeoff curve, wherein the actual curve is determined by the propagation delay and bitwidth of the logic operation. | 12-31-2009 |
20100095188 | APPARATUS AND METHOD FOR DETECTING AND CORRECTING ERRORS IN CONTROL CHARACTERS OF A MULTIMEDIA INTERFACE - An apparatus and method for detecting and correcting errors in control characters of a multimedia interface. The apparatus comprises a hamming distance filter for detecting and correcting bits errors in a first subset of bits of an input control character including M bits; a glitch filter for detecting and correcting a second subset of bits being a complementary subset of bits of the control character; and an character alignment unit for detecting and correcting misalignment errors between the corrected first subset of bits and the corrected second subset of bits. | 04-15-2010 |
20110013772 | Method and Apparatus for Fast Switching Between Source Multimedia Devices - A multimedia sink apparatus and method thereof, for fast switching between a plurality of source multimedia devices. The apparatus comprises a plurality of input ports, each of the plurality of input ports is connected to a source multimedia device through a high bandwidth multimedia interface; and a plurality of high-bandwidth digital content protection (HDCP) receivers, each of the plurality of the HDCP receivers is connected to an input port, wherein each of the plurality of the HDCP receivers is adapted to perform a first authentication part of a HDCP authentication process, and upon reception of an indication that a respective source device connected to the respective input was selected, to perform a third authentication part of the HDCP authentication process. | 01-20-2011 |
20110317751 | ADAPTIVE EQUALIZER FOR HIGH-SPEED SERIAL DATA - An adaptive equalizer for high-speed serial data comprises a programmable equalizer for equalizing an input serial data signal to generate an equalized serial data signal, wherein the equalization is based on an optimal equalization mode; a signal quality meter for computing an eye width indication based on the equalized serial data signal, wherein the eye width indication is an indicative of the quality of the equalized serial data signal; and a decision unit for determining the optimal equalization mode based on the eye width indication. | 12-29-2011 |
20120194487 | Master Synchronization for Multiple Displays - In an embodiment, a display apparatus includes multiple physical interface circuits (PHYs) couple to respective displays. In a mirror mode, the PHYs may operate as masters. A primary master PHY may control a synchronization interface to one or more secondary master PHYs. The synchronization interface may include a start of frame signal that the primary master PHY may generate to indicate the beginning of a new frame. The secondary master PHYs may be configured to generate internal start of frame signals while independently processing the same display data as the primary master. If the internally-generated start of frame and the received start of frame occur within a window of tolerance of each other, then the secondary masters may continue to process the display data stream independently. A secondary master that detects the start of frames occur outside of the window of tolerance may resynchronize. | 08-02-2012 |
20130002703 | Non-Real-Time Dither Using a Programmable Matrix - A dither unit with a programmable kernel matrix in which each indexed location/entry may store one or more dither values. Each dither value in a respective entry of the kernel matrix may correspond to the number of bits that are truncated during dithering. During dithering of each pixel of an image, entries in the kernel matrix may be indexed according to the relative coordinates of the pixel within the image. A dither value for the pixel may be selected from the indexed entry based on the truncated least significant bits of the pixel component value. When the kernel matrix is storing more than one dither value per entry, the dither value may be selected based further on the number of truncated least significant bits. A dithered pixel component value may then be generated according to the dither value and the remaining most significant bits of the pixel component value. | 01-03-2013 |
20140125556 | Master Synchronization for Multiple Displays - In an embodiment, a display apparatus includes multiple physical interface circuits (PHYs) couple to respective displays. In a mirror mode, the PHYs may operate as masters. A primary master PHY may control a synchronization interface to one or more secondary master PHYs. The synchronization interface may include a start of frame signal that the primary master PHY may generate to indicate the beginning of a new frame. The secondary master PHYs may be configured to generate internal start of frame signals while independently processing the same display data as the primary master. If the internally-generated start of frame and the received start of frame occur within a window of tolerance of each other, then the secondary masters may continue to process the display data stream independently. A secondary master that detects the start of frames occur outside of the window of tolerance may resynchronize. | 05-08-2014 |